CHOPPER CIRCUIT FOR MULTIPATH CHOPPER AMPLIFIER AND CORRESPONDING METHOD OF CHOPPING

Abstract

A chopper circuit (100) for a multipath chopper amplifier (201) is described. The chopper circuit (100) comprises a first chopper device (110) in a first circuit path (111), wherein the first chopper device (110) is configured to be controlled by a first clock signal (315), which has a first frequency; and a second chopper device (120) in a second circuit path (121), parallel to the first circuit path (111), wherein the second chopper device (120) is configured to be controlled by a second clock signal (325), which has a second frequency, wherein the first frequency is greater than the second frequency. Furthermore, a corresponding method of chopping an input signal (102) is described.

Claims

1. A chopper circuit for a multipath chopper amplifier, comprising a first chopper device in a first circuit path, wherein the first chopper device is configured to be controlled by a first clock signal, which has a first frequency; and a second chopper device in a second circuit path, parallel to the first circuit path, wherein the second chopper device is configured to be controlled by a second clock signal, which has a second frequency, wherein the first frequency is greater than the second frequency.

2. The chopper circuit according to claim 1, wherein the first frequency is half a sampling frequency or a multiple of half the sampling frequency.

3. The chopper circuit according to claim 1, wherein the second frequency is in the range from 1 to 1.5 times the sum of a signal bandwidth plus a flicker noise corner frequency.

4. The chopper circuit according to claim 1, wherein the first frequency is a multiple of the second frequency.

5. The chopper circuit according to claim 1, wherein at least one of the first and second clock signals comprises at least one of upward clock edges, which occur with the frequency of the respective clock signal, and downward clock edges, which occur with the frequency of the respective clock signal.

6. The chopper circuit according to claim 1, wherein, in the first clock signal, upward clock edges are omitted with a frequency equal to the second frequency.

7. The chopper circuit according to claim 1, further comprising a third chopper device in a third circuit path, wherein the third chopper device is configured to be controlled by a third clock signal, which has a third frequency.

8. The chopper circuit according to claim 7, wherein the third frequency equals the second frequency.

9. The chopper circuit according to claim 7, wherein the third clock signal corresponds to the second clock signal shifted in time such that the time difference between an upward clock edge of the second clock signal and a downward clock edge of the third clock signal is one over twice the first frequency.

10. The chopper circuit according to claim 7, wherein a combined clock signal composed of the first, the second and the third clock signals has exactly one upward clock edge or downward clock edge occurring at the sampling frequency.

11. The chopper circuit according to claim 7, further comprising at least one further chopper device, each in a respective circuit path and each configured to be controlled by a respective clock signal having a respective frequency, wherein a combined clock signal has exactly one upward clock edge or downward clock edge occurring at the sampling frequency.

12. A chopper amplifier circuit comprising the chopper circuit according to claim 1.

13. An integrator circuit comprising the chopper amplifier circuit according to claim 12.

14. A method of chopping an input signal comprising splitting the input signal so that a first path signal for a first circuit path and a second path signal for a second circuit path are provided; chopping the first path signal by means of a first chopper device in the first circuit path, wherein the first chopper device is controlled by a first clock signal, which has a first frequency; and chopping the second path signal by means of a second chopper device in the second circuit path, wherein the second chopper device is controlled by a second clock signal, which has a second frequency, wherein the first frequency is greater than the second frequency.

15. The method according to claim 14, wherein a third path signal for a third circuit path is additionally provided, when the input signal is split, the method further comprising chopping the third path signal by means of a third chopper device in the third circuit path, wherein the third chopper device is controlled by a third clock signal, which has a third frequency.

16. The method according to claim 14, wherein the first frequency is half a sampling frequency or a multiple of half the sampling frequency.

17. The method according to claim 14, wherein the second frequency is in the range from 1 to 1.5 times the sum of a signal bandwidth plus a flicker noise corner frequency.

18. The method according to claim 15, wherein at least one of the first and second clock signals comprises at least one of upward clock edges, which occur with the frequency of the respective clock signal, and downward clock edges, which occur with the frequency of the respective clock signal.

19. The method according to claim 18, wherein the time difference between an upward clock edge of the second clock signal and a downward clock edge of the third clock signal is one over twice the first frequency.

20. The method according to claim 15, wherein a combined clock signal composed of the first, the second and the third clock signals has exactly one upward clock edge or downward clock edge occurring at a sampling frequency.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0034] FIG. 1 shows a chopper circuit according to an exemplary embodiment of the present disclosure.

[0035] FIG. 2 shows a chopper amplifier circuit according to an exemplary embodiment of the present disclosure.

[0036] FIG. 3 shows clock signals for a chopper circuit for comparison.

[0037] FIG. 4 shows clock signals for a chopper circuit according to an exemplary embodiment of the present disclosure.

[0038] FIGS. 5 to 7 illustrate the folding gain dependent on interferer frequency for different chopping methods according to exemplary embodiments of the present disclosure.

[0039] FIGS. 8 and 9 show the integration of a chopper circuit in an integrator circuit according to an exemplary embodiment of the present disclosure.

[0040] FIG. 10 illustrates input noise depending on frequency for different chopping methods.

[0041] The illustrations in the drawings are schematic. In different drawings, similar or identical elements may be provided with the same reference signs.

DESCRIPTION OF THE DRAWINGS

[0042] FIG. 1 shows a chopper circuit 100 for a multipath chopper amplifier according to an exemplary embodiment of the present disclosure, specifically a 3-path chopper circuit for a 3-path chopper amplifier. The chopper circuit 100 comprises (i) a first chopper device 110 in a first circuit path 111, wherein the first chopper device 110 is configured to be controlled by a first clock signal 315 (see FIG. 4), which has a first frequency; and (ii) a second chopper device 120 in a second circuit path 121, parallel to the first circuit path 111, wherein the second chopper device 120 is configured to be controlled by a second clock signal 325 (see FIG. 4), which has a second frequency. The first frequency is greater than the second frequency. The chopper circuit 100 further comprises (iii) a third chopper device in a third circuit path 131, which is parallel to the first and second circuit paths, wherein the third chopper device 130 is configured to be controlled by a third clock signal 335 (see FIG. 4), which has a third frequency.

[0043] An input signal 102, received by means of two signal conductors, is chopped by the chopper circuit 100. To that effect, the input signal 102 is split so that a first path signal for a first circuit path 111, a second path signal for a second circuit path 121 and a third path signal for a third circuit path 131 are provided. The first, second and third paths 111, 121, 131 are each realized by two signal conductors. The first path signal is chopped by means of the above-described first chopper device 110 in the first circuit path 111. Likewise, the second and third path signals are chopped by the second and third chopper devices 120, 130, respectively.

[0044] FIG. 2 shows a 3-path chopper amplifier circuit 201 according to an exemplary embodiment of the present disclosure. The chopper amplifier circuit 201 comprises the chopper circuit 100 of FIG. 1. An input signal 102 is received at an input of the chopper amplifier circuit 201. The input signal 102 is split into a first path signal, a second path signal and a third path signal for respective paths. Each path signal is chopped by a respective chopper device 111, 121, 131 and then amplified by respective amplifiers 212, 222, 232. The path signals are demodulated by respective demodulators 213, 223, 233, realized by output choppers, and then combined to yield an output signal 103. Parasitic capacitors 214, 224, 234 are shown next to the amplifiers 212, 222, 232 in the respective paths.

[0045] FIG. 3 shows a first clock signal 315, a second clock signal 325, and a third clock signal 335 for a 3-path chopper circuit for comparison. Each clock signal is a rectangular signal having upward clock edges 341 and downward clock edges 342. The clock signals 315, 325, 335 have the same frequency f.sub.s/6, where f.sub.s is the sampling frequency. They are identical signals shifted in time with respect to each other. The combined clock signal of the three clock signals 315, 325, 335 corresponds to the reference clock signal 340 with frequency f.sub.s/2 as indicated in an exemplary manner by the dashed lines.

[0046] In a corresponding 3-path chopper amplifier (cp. FIG. 2), when controlled by the clock signals 315, 325, 335 of FIG. 3, all the paths are chopped at an equal frequency of f.sub.s/6, and clock edges between different paths occur periodically. The chopping clock has a fixed duty cycle of 50%. So, all three paths are sampled an equal number of times. These sampled voltages can be different if there is a mismatch between the different paths used in the multi-path chopper amplifier. This mismatch is either due to the clocking skew or mismatch between the parasitic capacitors at the input choppers and output choppers. This can cause residual folding from multiples of f.sub.s/3. Quantization noise still folds from multiples of f.sub.s as there is one chopping transition in every sampling period (1/f.sub.s). Quantization noise is negligible at multiples of f.sub.s due to NTF zeros, i.e. zeros of the noise transfer function. Since each path is chopped at f.sub.s/6, quantization noise can fold from multiples of f.sub.s/3 if there is a mismatch between the three paths.

[0047] FIG. 4 shows a first clock signal 315, a second clock signal 325, and a third clock signal 335 for a 3-path chopper circuit for a chopper circuit according to an exemplary embodiment of the present disclosure. Each clock signal 315, 325, 335 is a rectangular signal having upward clock edges 341 and downward clock edges 342. The first clock signal 315 has a first frequency f.sub.1=f.sub.s/2, which is greater than the second frequency f.sub.2=f.sub.s/18 of the second clock signal 325 and the third frequency f.sub.3=f.sub.s/18 of the third clock signal 335. The time difference between a rising and/or a falling clock edge of the second clock signal 325 and a falling and/or rising clock edge of the third clock signal 335 is 1/f.sub.s, respectively. The second and third clock signals 325, 335 are identical signals shifted by 8/f.sub.s or 10/f.sub.s with respect to each other. In the first clock signal 315, certain upward and downward clock edges are omitted at instances, where there are corresponding clock edges in the second or third clock signals 325, 335. The combined clock signal of the three clock signals 315, 325, 335 corresponds to the reference clock signal 340 with frequency f.sub.s/2 as indicated in an exemplary manner by the dashed lines.

[0048] If a 3-path chopper amplifier (see e.g. FIG. 2) is controlled by the clocking scheme depicted in FIG. 4, two paths are chopped at a lower frequency (low-frequency chopper). In order not to fold quantization noise, there should be exactly one chopping edge in every sampling period (1/f.sub.s). So, whenever there is a chopping clock edge in the low-frequency chopping paths (associated with clock signals 325, 335), there is no chopping edge in the high-frequency chopping path (associated with clock signal 315).

[0049] Since there are more chopping edges in the path where there is a higher frequency chopper, most of the time, sampling happens from that path. In principle, if the frequency of the low-frequency chopping paths is further reduced, a single path is sampled more often. The lowest frequency possible may be f.sub.BW (bandwidth)+f.sub.flick(flicker noise corner) so that the flicker noise is modulated outside the signal bandwidth. Since sampling happens from one path more often than from the other paths, the magnitude of folding is reduced if there is a mismatch between the different paths.

[0050] FIGS. 5 to 7 illustrate the folding gain (dB) 551 dependent on interferer frequency (GHz) 550 for different chopping methods according to an exemplary embodiment of the present disclosure.

[0051] FIG. 5 shows the folding gain 552 from the input signal level to the folded signal level in a continuous-time delta-sigma modulator with a chopper with out-of-band interferers. As chopping at f.sub.s/2 causes sampling of the virtual ground at f.sub.s, signal content around f.sub.s at the virtual ground fold backs to in-band frequencies. There is no folding of quantization noise because of nulls created by the noise transfer function around multiples of f.sub.s. But, out-of-band interferers around f.sub.s can fold back to in-band frequencies. Regarding the folding gain 553 of a 3-path chopper amplifier, folding from f.sub.s reduces by a factor of 3 (9 dB). 3-path chopper amplifiers also cause additional residual folding from multiples of f.sub.s/3 with 1% mismatch.

[0052] FIG. 6 shows the interferer folding gain 654 with a clocking technique, where the frequencies of a second and third clock signal are smaller than the frequency of a first clock signal. Frequency of the low-frequency choppers is f.sub.s/38. With 1% mismatch, interferers fold from multiples of f.sub.s/19. There is about 9 dB improvement in the overall folding signal level with the proposed clocking technique. This can further be improved by reducing the frequency of the low-frequency choppers, which in this design is limited by the low over-sampling ratio of 28.

[0053] FIG. 7 shows for comparison the folding gain 755 of another technique, FIR DAC, to reduce the chopping frequency in a continuous-time delta-sigma modulator without fold the quantization noise. An N-tap FIR DAC creates notches in the DAC output at multiples of f.sub.s/N. By choosing the chopping frequency as f.sub.s/2N, there is no folding of quantization noise due to the nulls created by FIR DAC.

[0054] Signal swing at the virtual ground of the first integrator is determined both from the input and the feedback DAC path. Since there are nulls created only in the feedback path, out-of-band interferers from multiples of f.sub.s/N can fold back to the signal bandwidth. FIG. 7 shows the interferer folding gain 755 with a 3-tap FIR DAC. There is a degradation of 42 dB in the folding amplitude compared to the folding gain 553 of a conventional 3-path chopper amplifier with 1% mismatch between the paths.

[0055] FIGS. 8 and 9 show the implementation of a chopper circuit, which comprises a chopper device 110, but could comprise further chopper devices, in an integrator circuit 860 according to an exemplary embodiment of the present disclosure. The integrator circuit 860 comprises a chopper amplifier circuit. The chopper amplifier circuit comprises the chopper device 110, an amplifier 212 and a demodulator 213. The chopper amplifier circuit may further comprise a common-mode feedback (CMFB) circuit 861 including CMFB resistors 864. The integrator circuit 860 further comprises input resistors 861 and DAC resistors 862.

[0056] In FIG. 9, the chopper device 110 and the demodulator (output chopper) 213 plus the corresponding parasitic capacitors (see FIG. 2) are replaced by respective switch-capacitor equivalent resistors 965. R.sub.in_ch and R.sub.out ch are switch-capacitor equivalent resistors 965 of input and output choppers with R.sub.in_ch=(¼ C.sub.g f.sub.ch), where C.sub.g is the capacitance of the parasitic capacitor associated with the chopper device 110 and f.sub.ch is the frequency of chopper device 110.

[0057] Chopping the first integrator in a continuous-time delta-sigma modulator can cause the aliasing of the high-pass-shaped quantization noise from multiples of twice the chopping frequency into the signal bandwidth. Chopping at half the sampling frequency (f.sub.s/2) can avoid this noise folding due to the NTF zeros at multiples of f.sub.s. The disadvantage of this high-frequency chopping is increased amplifier's thermal noise when referred to the input of the delta-sigma ADC and reduced effective amplifier gain, which increases swing at the virtual ground and degrades linearity.

[0058] FIG. 10 illustrates input noise (nV/√Hz) 1070 or input referred noise dependent on frequency (Hz) 1071 for different chopping methods for comparison. FIG. 10 shows the input-referred noise of the integrator of FIGS. 8 and 9. For the input noise 1072 without chopping, flicker noise is dominant till a few 10s MHz. For the input noise after chopping 1073, 1074, the flicker noise of the first stage is modulated to the chopping frequency and its odd harmonics. There is an increase in thermal noise after chopping due to the input switch-capacitor equivalent resistor. The expression for amplifier noise when referred to the input of the integrator, i.e. input referred amplifier noise, is: (4KTγ/g.sub.m)(R/R.sub.in∥R.sub.DAC∥R.sub.CMFB∥R.sub.in_ch).sup.2, where g.sub.m is transconductance of the amplifier, R.sub.in is the resistance of the input resistor 862, R.sub.DAC is the resistance of the DAC resistor 863, R.sub.CMFB is the resistance of the CMFB resistor 864 and R.sub.in_ch is the resistance of the switch-capacitor equivalent resistor 965 of the (input) chopper device 110.

[0059] Input and output switch capacitor resistors increase with reducing the chopping frequency. So, the thermal noise and amplifier's gain improve by reducing the chopping frequency (compare input noise 1073 for chopping at f.sub.s and input noise 1074 for chopping at f.sub.s/2). Unfortunately, reducing the chopping frequency below f.sub.s/2 can cause the aliasing of quantization noise into the signal band. Multi-path chopping as described in the present disclosure is a technique to improve these chopping artifacts while effectively chopping at f.sub.s/2.

[0060] In this specification, embodiments have been presented in terms of a selected set of details. However, a person of ordinary skill in the art would understand that many other embodiments may be practiced which include a different selected set of these details. It is intended that the following claims cover all possible embodiments.

REFERENCE NUMERALS

[0061] 100 chopper circuit [0062] 102 input signal [0063] 103 output signal [0064] 110 first chopper device [0065] 111 first circuit path [0066] 120 second chopper device [0067] 121 second circuit path [0068] 130 third chopper device [0069] 131 third circuit path [0070] 201 chopper amplifier circuit [0071] 212 first path amplifier [0072] 213 first path demodulator [0073] 214 first path parasitic capacitor [0074] 222 second path amplifier [0075] 223 second path demodulator [0076] 224 second path parasitic capacitor [0077] 232 third path amplifier [0078] 233 third path demodulator [0079] 234 third path parasitic capacitor [0080] 315 first clock signal [0081] 325 second clock signal [0082] 335 third clock signal [0083] 340 reference clock signal [0084] 341 upward clock edge [0085] 342 downward clock edge [0086] 550 interferer frequency [0087] 551 folding gain [0088] 552 folding gain (f.sub.s/2) [0089] 553 folding gain (f.sub.s/6, three-path chopping) [0090] 654 folding gain (chopping clocks with different frequencies) [0091] 755 folding gain (3-tap FIR) [0092] 860 integrator circuit [0093] 861 common-mode feedback (CMFB) circuit [0094] 862 input resistor [0095] 863 DAC resistor [0096] 864 CMFB resistor [0097] 965 switch-capacitor equivalent resistor [0098] 1070 input noise [0099] 1071 frequency [0100] 1072 input noise (without chopping) [0101] 1073 input noise (chopping at f.sub.s) [0102] 1074 input noise (chopping at f.sub.s/2)