DIGITAL-TO-ANALOG CONVERTER (DAC) ARCHITECTURE OPTIMIZATION

Abstract

A digital-to-analog converter (DAC) comprises circuitry configured to generate, based on a mapping, L signals representing an N-bit digital input, wherein N and L are positive integers, and wherein N<L<2.sup.N−1, and circuitry configured to control current flow from L weighted current sources using the L respective signals, thereby generating an analog output that uniquely represents the N-bit digital input, wherein the weighted current sources have weights configured to minimize at least one error metric associated with the analog output.

Claims

1. A digital-to-analog converter (DAC) comprising: circuitry configured to generate, based on a mapping, L signals representing an N-bit digital input, wherein N and L are positive integers, and wherein N<L<2.sup.N−1; and circuitry configured to control current flow from L weighted current sources using the L respective signals, thereby generating an analog output that uniquely represents the N-bit digital input, wherein a weight ratio of at least one pair of the weighted current sources is a positive real number different from an integer power of two.

2. The DAC as claimed in claim 1, wherein the weighted current sources have weights configured to minimize at least one error metric associated with the analog output.

3. The DAC as claimed in claim 2, wherein the at least one error metric represents errors caused by statistical rise/fall asymmetry between currents flowing from the weighted current sources.

4. The DAC as claimed in claim 2, wherein the at least one error metric represents errors caused by statistical amplitude mismatches between currents flowing from the weighted current sources.

5. The DAC as claimed in claim 2, wherein the at least one error metric represents errors caused by statistical timing offsets of OFF-to-ON and ON-to-OFF transitions between currents flowing from the weighted current sources.

6. The DAC as claimed in claim 2, wherein the mapping is configured to minimize the at least one error metric.

7. The DAC as claimed in claim 2, wherein the mapping is configured to minimize a DAC-specific error metric representing errors caused by circuit component mismatches measured in the DAC.

8. The DAC as claimed in claim 7, wherein the circuit component mismatches comprise one or more of rise/fall asymmetry between currents flowing from the weighted current sources; amplitude mismatches between currents flowing from the weighted current sources; and timing offsets of OFF-to-ON and ON-to-OFF transitions between currents flowing from the weighted current sources.

9. The DAC as claimed in claim 1, wherein weights of the weighted current sources do not solely consist of a combination of unary weights and binary weights.

10. The DAC as claimed in claim 1, wherein the digital input comprises a pre-compensated digital signal generated based on a distortion model representing circuit component mismatches in the DAC.

11. A method for digital-to-analog conversion comprising: generating, based on a mapping, L signals representing an N-bit digital input, wherein N and L are positive integers, and wherein N<L<2.sup.N−1; and controlling current flow from L weighted current sources of a digital-to-analog converter (DAC) using the L respective signals, thereby generating an analog output that uniquely represents the N-bit digital input, wherein a weight ratio of at least one pair of the weighted current sources is a positive real number different from an integer power of two.

12. The method as claimed in claim 11, wherein the weighted current sources have weights configured to minimize at least one error metric associated with the analog output.

13. The method as claimed in claim 12, wherein the at least one error metric represents glitch errors caused by statistical rise/fall asymmetry between currents flowing from the weighted current sources.

14. The method as claimed in claim 12, wherein the at least one error metric represents errors caused by statistical amplitude mismatches between currents flowing from the weighted current sources.

15. The method as claimed in claim 12, wherein the at least one error metric represents glitch errors caused by statistical timing offsets of OFF-to-ON and ON-to-OFF transitions between currents flowing from the weighted current sources.

16. The method as claimed in claim 12, wherein the mapping is configured to minimize the at least one error metric.

17. The method as claimed in claim 12, further comprising calculating the mapping by minimizing a DAC-specific error metric representing errors caused by circuit component mismatches measured in the DAC.

18. The method as claimed in claim 17, wherein the circuit component mismatches comprise one or more of rise/fall asymmetry between currents flowing from the weighted current sources; amplitude mismatches between currents flowing from the weighted current sources; and timing offsets of OFF-to-ON and ON-to-OFF transitions between currents flowing from the weighted current sources.

19. The method as claimed in claim 11, wherein weights of the weighted current sources do not solely consist of a combination of unary weights and binary weights.

20. The method as claimed in claim 11, wherein the digital input comprises a pre-compensated digital signal generated based on a distortion model representing circuit component mismatches in the DAC.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0013] FIG. 1 is a block diagram illustration of an example transmitter;

[0014] FIG. 2 illustrates a digital-to-analog converter (DAC) architecture comprising unary-weighted current sources in accordance with PRIOR ART;

[0015] FIG. 3 illustrates a DAC architecture comprising binary-weighted current sources in accordance with PRIOR ART;

[0016] FIG. 4 illustrates a segmented DAC architecture in accordance with PRIOR ART;

[0017] FIG. 5 illustrates a plot of rise/fall asymmetry in a switchable current source in accordance with some examples;

[0018] FIG. 6 illustrates a first optimized DAC architecture in accordance with some examples of the proposed technology;

[0019] FIG. 7 illustrates a second optimized DAC architecture in accordance with some examples of the proposed technology;

[0020] FIG. 8 illustrates a plot of normalized mean squared error (MSE) due to rise/fall asymmetry as a function of basis length for several optimized DAC architectures in accordance with some examples of the proposed technology, relative to several segmented DAC architectures;

[0021] FIG. 9 illustrates a plot of signal-to-noise-distortion ratio (SNDR) due to rise/fall asymmetry as a function of basis length for several optimized DAC architectures in accordance with some examples of the proposed technology, relative to several segmented DAC architectures;

[0022] FIG. 10 illustrates a plot of current amplitude mismatches between switchable current sources in accordance with some examples;

[0023] FIG. 11 illustrates a plot of normalized MSE due to current amplitude mismatches as a function of basis length for several optimized DAC architectures in accordance with some examples of the proposed technology, relative to several segmented DAC architectures;

[0024] FIG. 12 illustrates a plot of SNDR due to current amplitude mismatches as a function of basis length for several optimized DAC architectures in accordance with some examples of the proposed technology, relative to several segmented DAC architectures;

[0025] FIG. 13 illustrates a plot of OFF-to-ON timing offsets between switchable current sources in accordance with some examples;

[0026] FIG. 14 illustrates a plot of normalized MSE due to timing offsets as a function of basis length for several optimized DAC architectures in accordance with some examples of the proposed technology, relative to several segmented DAC architectures;

[0027] FIG. 15 illustrates a plot of SNDR due to timing offsets as a function of basis length for several optimized DAC architectures in accordance with some examples of the proposed technology, relative to several segmented DAC architectures;

[0028] FIG. 16 illustrates a method for digital-to-analog conversion in accordance with some examples of the proposed technology;

[0029] FIG. 17 illustrates a schematic showing digital pre-compensation of DAC distortion in accordance with some examples of the proposed technology;

[0030] FIG. 18 illustrates a schematic showing aspect of a signal path between a transmitter device and a receiver device in accordance with some examples of the proposed technology;

[0031] FIG. 19 illustrates a schematic showing a first distortion model representing rise/fall asymmetry in a DAC in accordance with some examples of the proposed technology;

[0032] FIG. 20 illustrates a plot of SNDR due to rise/fall asymmetry as a function of rise/fall asymmetry for several DAC architectures with and without pre-compensation in accordance with some examples of the proposed technology;

[0033] FIG. 21 illustrates a schematic showing a second distortion model representing current amplitude mismatches in a DAC in accordance with some examples of the proposed technology;

[0034] FIG. 22 illustrates a plot of SNDR due to current amplitude mismatches as a function of the standard deviation of the current amplitude mismatches for several optimized DAC architectures with and without pre-compensation in accordance with some examples of the proposed technology;

[0035] FIG. 23 illustrates a schematic showing a third distortion model representing timing offsets in a DAC in accordance with some examples of the proposed technology;

[0036] FIG. 24 illustrates a plot of SNDR due to timing offsets as a function of the standard deviation of the timing offsets with and without pre-compensation in accordance with some examples of the proposed technology;

[0037] FIG. 25 illustrates a schematic showing a fourth distortion model representing rise/fall asymmetry, current amplitude mismatches, and timing offsets in a DAC in accordance with some examples of the proposed technology;

[0038] FIG. 26 illustrates a plot of SNDR due to rise/fall asymmetry, current amplitude mismatches, and timing offsets as a function of the standard deviation of the timing offsets with and without pre-compensation in accordance with some examples of the proposed technology; and

[0039] FIG. 27 illustrates a method for digital pre-compensation of distortion in a DAC in accordance with some examples of the proposed technology.

DETAILED DESCRIPTION

[0040] FIG. 1 is a block diagram illustration of an example transmitter 100. The transmitter 100 is an optical transmitter that employs polarization-division multiplexing (PDM). A laser 102 is operative to generate a continuous wave (CW) optical carrier 104. A polarizing beam splitter 106 is operative to split the CW optical carrier 104 into orthogonally-polarized components 108, 110 (nominally referred to as the “X-polarization” component and the “Y-polarization” component) that are modulated by respective electrical-to-optical modulators 112, 114 to produce modulated polarized optical signals 116, 118 that are combined by a beam combiner 120, thus yielding an optical signal 122.

[0041] A symbol source 124 is operative to generate a stream of symbols representing data to be transmitted in the optical signal 122. A digital signal processor (DSP) 126 is operative to process the symbols output from the symbol source 124, for example, performing one or more of pulse shaping, subcarrier multiplexing, chromatic dispersion pre-compensation, and distortion pre-compensation on the symbols. The DSP 126 is operative to generate I and Q digital drive signals 128, 129 for the X-polarization to be converted by DACs 130, 131, respectively, into I and Q analog drive signals 132, 133 for the X-polarization that, after amplification by respective amplifiers 134, 135, are used to drive the electrical-to-optical modulator 112. The DSP 126 is operative to generate I and Q digital drive signals 136, 137 for the Y-polarization to be converted by DACs 138, 139, respectively, into I and Q analog drive signals 140, 141 for the Y-polarization that, after amplification by respective amplifiers 142, 143, are used to drive the electrical-to-optical modulator 114. Each of the DACs 130, 131, 138, 139 is operative to produce a high-bandwidth analog signal having a sample period of T. In some implementations, the DSP 126 and the DACs 130, 131, 138, 139 are comprised in a complementary metal-oxide-semiconductor (CMOS) module, and the amplifiers 134, 135, 142, 143 are comprised in a bipolar CMOS (BiCMOS) module.

[0042] In general, a DAC is configured to convert a digital input x into an analog output X using a plurality of switchable current sources (i.e., current sources controlled by respective switches). A current source may comprise a direct current source, or may be realized by a voltage reference and a resistor. High-speed applications often employ current-steering DACs, which use metal-oxide semiconductor field-effect transistors (MOSFETS) as the switchable current sources. The technology presented herein is described in the context of current-steering DACs, but may be applied to any DAC architecture comprising switchable current sources. The DAC architectures described in this document may be used in devices such as the optical transmitter 100, or any other type of electronic apparatus that is configured for digital-to-analog conversion.

[0043] A DAC may be characterized by a basis length L, which denotes the number of switchable current sources comprised in the DAC. A DAC of basis length L comprises L current sources which are weighted by L respective weights, B.sub.i, for i=1 . . . L. The relationship between the digital input x and the analog output X may be expressed as:

X=W.sup.T(x)B  [1]

where W.sup.T(x) denotes the transpose of a binary vector W(x) of size L which is a function of the digital input x, and where B is a vector of length L comprising the weights of the L current sources, herein referred to as a basis vector. The binary vector W(x) may be understood as a set of L signals used to control the L switches. Given a digital input x comprising N bits, where N is a positive integer, the architecture of the DAC (including the binary vector W(x) and the basis vector B) is designed to have a resolution of 2.sup.N, meaning that the DAC outputs an analog output X that uniquely represents any one of the 2.sup.N possible values of the digital input x. Various DAC architectures may be used to achieve this. The following examples involve a digital input x comprising N=8 bits, but other examples are contemplated.

[0044] FIG. 2 illustrates a DAC architecture 200 in accordance with an example of PRIOR ART. The DAC architecture 200 has unary weighting, meaning that the current sources have identical weights. This type of architecture may also be referred to as a thermometer-coded DAC. In this case, the current sources comprise unit current sources 202, such that B.sub.i=1 for i=1 . . . L. With a unary-weighted DAC, a basis length of L=2.sup.N−1 is used to convert an N-bit digital input to a 2.sup.N-level analog output. Thus, for a given digital input 204 comprising N=8 bits, L=255 unit current sources 202 are controlled by L=255 respective switches (denoted by S1, . . . , S255) to generate an analog output 206 that is representative of the digital input 204. The 255 switches are controlled by 255 bits 208 generated by an 8-to-255 decoder 210 based on the 8-bit digital input 204. In this example, the analog output 206 is the voltage measured across a resistor 212. The bits 208 used to control the switches may be represented by the binary vector W in Equation 1. It will be apparent that there is redundancy in the unary-weighted DAC architecture 200. That is, multiple different binary vectors W may be used to generate the same analog output 206. For this reason, a unary-weighted DAC with L=2.sup.N−1 may be described as having a fully over-complete basis.

[0045] FIG. 3 illustrates a DAC architecture 300 in accordance with an example of PRIOR ART. The DAC architecture 300 has binary weighting, meaning that the current sources have different weights which, when normalized by their minimum value, form a basis vector B=[1, 2, 4, 8, . . . , 2.sup.N−1]. According to one example, a non-unit current source may be implemented by a plurality of unit current sources arranged in parallel. For example, a current source of weight 8 may be implemented by 8 parallel unit current sources. With a binary-weighted DAC, a basis of length L=N is used to convert an N-bit digital input to a 2.sup.N-level analog output. Thus, for the digital input 204 comprising N=8 bits, L=8 weighted current sources 302 having respective weights B=[1, 2, 4, 8, 16, 32, 64, 128] are controlled by L=8 respective switches (denoted by S1, . . . , S8) to generate an analog output 306 that is representative of the digital input 204. The 8 switches are controlled directly by the 8 bits of the digital input 204, with the least significant bit (LSB) controlling the switch S1 (which in turn controls the current source having the lowest weight, B.sub.I=1), and with the most significant bit (MSB) controlling the switch S8 (which in turn controls the current source having the highest weight, B.sub.8=128). There is no redundancy in the binary-weighted DAC architecture 300. That is, any given analog output 306 may be generated using only one binary vector W (corresponding to the 8-bit digital input 204). For this reason, a binary-weighted DAC with L=N may be described as having a complete basis.

[0046] Unary-weighted DACs may achieve excellent performance with little distortion, but this is at the expense of circuit area and complexity. Binary-weighted DACs take up less space and have lower complexity than unary DACs, but may suffer from significant distortions. For example, the 8-bit binary-weighted DAC architecture 300 comprises only eight switchable current sources (compared to the 255 switchable current sources required to implement the 8-bit unary-weighted DAC architecture 200), but may be less accurate due to the high precision required for each individual current source. A hybrid between a unary-weighted DAC and a binary-weighted DAC, herein referred to as a segmented DAC, may be used to balance complexity with performance. Examples of segmented DAC architectures are described by Versterbacka in “Linear-Coded D/A Converters with Small Relative Error Due to Glitches,” Proceedings of the 44.sup.th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001, vol. 1, August 2001; and by Tesch et al. in “A Low Glitch 14-b 100-MHz D/A Converter,” IEEE Journal of Solid-State Circuits, vol. 32, no. 9, September 1997.

[0047] FIG. 4 illustrates a segmented DAC architecture 400 in accordance with an example of PRIOR ART. The DAC architecture 400 comprises a combination of binary-weighted current sources and unary-weighted current sources, where the binary weighting is used for lower-order or least significant bits (LSBs) and the unary weighting is used for higher-order or most significant bits (MSBs). This type of segmented architecture may be realized in various ways, depending on how many bits are treated as LSBs and how many bits are treated as MSBs. In this example, two bits of the 8-bit digital input 204 are classified as MSBs, while the remaining six bits are classified as LSBs. For the six LSBs 412, six binary-weighted current sources 404 having respective weights B=[1, 2, 4, 8, 16, 32] are controlled by six respective switches (denoted by S1, . . . , S6). The least significant of the six LSBs 412 (i.e., the least LSB or LLSB) controls the switch S1 (which in turn controls the current source having the lowest weight, B.sub.1=1), and the most significant of the six LSBs 412 (i.e., the most LSB or MLSB) controls the switch S6 (which in turn controls the current source having the highest weight, B.sub.6=32). For the two MSBs of the 8-bit digital input 204, three unary-weighted current sources 402 are controlled by switches S7, S8, S9, respectively. The switches S7, S8, S9 are in turn are controlled by bits 408 generated by a 2-to-3 decoder 410 based on the two MSBs. Each of the unary-weighted current sources 402 has an identical weight that is a factor of two greater than highest weight of the binary-weighted current sources 404. Thus, since B.sub.6=32, it follows that B.sub.7=B.sub.8=B.sub.9=64. A segmented DAC has an over-complete basis with some redundancy, where N<L<2.sup.N−1. The segmented architecture may offer a tradeoff between the advantages and disadvantages of the unary- and binary-weighted implementations. For example, the 8-bit segmented DAC architecture 400 (which comprises only nine switches) may achieve better performance than the 8-bit binary DAC architecture 300, but without the complexity of the 8-bit unary DAC architecture 200 (which comprises 255 switches).

[0048] The performance of current-steering DACs, such as those illustrated in FIGS. 2, 3, and 4 may be degraded by distortions caused by mismatches or inconsistencies between circuit components/elements. For example, when there is a transition from a first digital input x to a second digital input y, a DAC may briefly generate an analog output that is representative of some value other than x or y. This type of transient nonlinear distortion, herein referred to as a glitch error, may result from differences between rise/fall asymmetry within the switches and/or timing offsets between the switches. Such distortion sources may also be excited through a specific pattern of consecutive ON/OFF transitions for a specific current switch. For example, a specific pattern of ON-OFF-ON for a current switch may generate a different distortion source than a pattern of OFF-OFF-ON. In another example, signal degradation may arise from amplitude mismatches of the currents generated by the switchable current sources, which may impact static performance of the DAC. Current amplitude mismatch errors may be a dominant source of impairment in low speed applications, while glitch errors may have a higher impact as the data rate increases. Rise/fall asymmetry, current amplitude differences, and timing offsets between switchable current sources are examples of circuit component mismatches that may result in DAC distortion.

[0049] DAC distortion may be reduced using various techniques that exploit redundancy in the DAC architecture. For example, dynamic element matching (DEM) techniques have been shown to significantly improve the spurious free dynamic range (SFDR), (see, for example, Shen et al., “Random Swapping Dynamic Element Matching Technique for Glitch Energy Minimization in Current-Steering DAC,” IEEE Transactions on Circuits and Systems II. Express Briefs, vol. 57, no. 5, pp. 369-373, 2010; Vesterbacka et al., “Dynamic Element Matching in D/A Converters with Restricted Scrambling,” in ICECS 2000, 7.sup.th IEEE International Conference on Electronics, Circuits and Systems, vol. 1, 2000; Baird et al., “Linearity Enhancement of Multibit ΔΣ A/D and D/A Converters Using Data Weighted Averaging,” IEEE Transactions on Circuits and Systems II. Analog and Digital Signal Processing, vol. 42, no. 12, 1995; Galton, “Why Dynamic-Element-Matching DACs Work,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 57, no. 2, 2010; Rudberg et al., “Glitch Minimization and Dynamic Element Matching in D/A Converters,” in ICECS 2000. 7.sup.th IEEE International Conference on Electronics, Circuits and Systems, vol. 2, 2000). However, such techniques have not improved the signal-to-noise distortion ratio (SNDR). In another example, mapping algorithms that use amplitude errors or timing errors to determine an optimized mapping of unary-weighted current sources or cells have been shown to improve performance (see, for example, Nakamura et al., “A 10-b 70-MS/s CMOS D/A Converter,” IEEE Journal of Solid-State Circuits, vol. 26, no. 4, 1991; Bastos et al., “A 12-bit Intrinsic Accuracy High-Speed CMOS DAC,” IEEE Journal of Solid-State Circuits, vol. 33, no. 12, 1998; Van Der Plas et al., “A 14-bit Intrinsic Accuracy Q.sup.2 Random Walk CMOS DAC,” IEEE Journal of Solid-State Circuits, vol. 34, no. 12, 1999; Cong et al., “Switching Sequence Optimization for Gradient Error Compensation in Thermometer-Decoded DAC Arrays,” IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 47, no. 7, 2000). However, such techniques are complex and have high power consumption.

[0050] There remains a need for DAC architectures that are capable of high performance (i.e., low distortion) but with low complexity, low power consumption, and small footprint.

[0051] In accordance with some examples of the technology described herein, efficient DAC architectures are proposed based on the minimization of various statistical error metrics. The proposed DAC architectures may achieve similar performance to segmented DACs but using fewer switches than the segmented DACs. Three types of errors are considered in the examples below: (1) glitch errors arising from rise/fall asymmetry; (2) static errors arising from current amplitude mismatches; and (3) glitch errors arising from timing offsets. However, it should be understood that DAC architectures may be designed by minimizing other statistical error metrics.

[0052] In each of the following examples, the optimized DAC architectures are designed to have an over-complete basis, where N<L<2.sup.N−1. However, in contrast to a segmented architecture, where one portion of the current sources are unary-weighted and the other portion of the current sources are binary-weighted, all of the current sources in the proposed DAC architectures have weights configured to minimize a statistical error metric associated with the analog output of the DAC.

[0053] Glitch Errors Arising from Rise/Fall Asymmetry

[0054] Glitch errors may be caused by rise/fall asymmetry within the switches of the DAC, that is, differences between the current response to a switch transitioning from OFF (or OPEN) to ON (or CLOSED) (i.e., the transient rise of the current) and the current response to the switch transitioning from ON to OFF (i.e., the transient fall of the current).

[0055] FIG. 5 illustrates a plot 500 of rise/fall asymmetry in a switchable current source in accordance with some examples. The solid line shows the output current of the switchable current source resulting from a transition of the switch from OFF to ON, and the dashed line shows the output current of the switchable current source resulting from a transition of the switch from ON to OFF. For the purposes of the following example, it is assumed that all the switchable current sources of the DAC exhibit the same settling transients (i.e., the shapes of the two curves are identical), but that there is a static time offset τ.sub.ON/OFF between the OFF-to-ON transient and the ON-to-OFF transient, where the value of τ.sub.ON/OFF represents the rise/fall asymmetry. It is also assumed that each switchable current source is characterized by the same value of τ.sub.ON/OFF. As a result of the rise/fall asymmetry, a transition from a first digital input x to a second digital input y may cause the DAC to briefly generate an analog output that is representative of some value other than x or y (i.e., a glitch error).

[0056] The DAC architecture may be configured to minimize the power of glitch errors that arise from rise/fall asymmetry in the responses of the switchable current sources. In “Modeling Glitches due to Rise/Fall Asymmetry in Current-Steering Digital-to-Analog Converters,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 52, no. 11, pp. 2265-2275, November 2005, Andersson et al. proposed the following metric for glitch errors caused by rise/fall asymmetry:

e.sub.1(x,y)=|W.sup.T(y)−W.sup.T(x)|B  [2]

where x and y denote two different digital inputs, each comprising N bits, where N is a positive integer, where W.sup.T(x), W.sup.T(y) denote the transpose of binary vectors W(x), W(y), respectively, each of size L, which are functions of x, y, respectively, where B denotes a basis vector of size L (containing the weights of all current sources in the DAC), and where N<L<2.sup.N−1.

[0057] The expected value of glitch error power or mean squared error (MSE) may be expressed as:

[00001]$\begin{array}{cc}𝔼\left[{.Math.e_1.Math.}^2\right]={.Math.}_{x=0}^{2^N-1}{.Math.}_{y=0}^{2^N-1}Pr\left(x,y\right){.Math.}_{W\left(x\right)\in R\left(x\right)}Pr\left(W\left(x\right)\right)\underset{W\left(y\right)\in R\left(y\right)}{\min }{\left(e_1\left(x,y\right)\right)}^2& \left[3\right]\end{array}$

where R(x) denotes the set of all possible representations for the digital input x, R(y) denotes the set of all possible representations for the digital input y, where Pr(x,y) is the transition probability from the digital input x to the digital input y, and where Pr(W(x)) is the probability distribution of representations of the digital input x.

[0058] For a selected basis length L satisfying N<L<2.sup.N−1, the DAC architecture may be optimized by determining the weights B.sub.OPT that minimize the expected glitch error power [|e.sub.1|.sup.2]. This optimization, which may be expressed as:

[00002]$\begin{array}{cc}{B}_{OPT}=\underset{B}{\arg \min }\left(𝔼\left[{.Math.e_1.Math.}^2\right]\right)& \left[4\right]\end{array}$

is a nonlinear, non-convex, discrete problem, where the dimension of the search space is L and each element has an integer value in the range 1 . . . 2.sup.N. Thus, the maximum size of the search space is 2.sup.NL, which grows exponentially with both N and L. Consequently, it may be impractical to do an exhaustive search (unless the values of L and N are small). According to some examples, the optimized basis vector B.sub.OPT for basis length L may be computed using a differential evolution (DE) optimization algorithm, for example, as described by Storn et al. in “Differential Evolution A Simple and Efficient Heuristic for Global Optimization over Continuous Spaces,” Journal of Global Optimization, vol. 11, no. 4, 1997. A computer simulation was performed wherein a DE optimization algorithm was used to determine the optimized basis vector B.sub.OPT of an 8-bit DAC for different basis lengths L=9, 10, 11, 12, and 13. The optimization assumed a white Gaussian noise input signal, with the root mean square (RMS) of the input signal being set to the optimal value that achieves maximum signal-to-quantization ratio (SQNR). Monte Carlo simulations were used to determine the optimal RMS of the input signal by sweeping the RMS and measuring the corresponding SQNR of the DAC. The DE optimization algorithm was repeated 100 times and the best basis vector B.sub.OPT (i.e., the one that achieved the lowest glitch error power) for each basis length L is shown in Table 1, where the weights in each vector B.sub.OPT are normalized by the minimum weight. In each case, it will be apparent that the sum of the normalized weights is 2.sup.8−1=255. The optimized basis vectors B.sub.OPT in Table 1 are configured to minimize glitch errors caused by rise/fall asymmetry.

TABLE-US-00001 TABLE 1 Basis Length L Optimized Basis Vector B.sub.OPT 9 [1, 2, 4, 8, 16, 31, 43, 69, 81] 10 [1, 2, 4, 8, 16, 21, 31, 39, 62, 71] 11 [1, 2, 4, 8, 13, 18, 26, 30, 38, 54, 61] 12 [1, 2, 4, 8, 11, 16, 20, 25, 27, 35, 48, 58] 13 [1, 2, 4, 7, 9, 15, 16, 19, 22, 26, 38, 42, 54]

[0059] FIG. 6 illustrates an 8-bit DAC architecture 600 having the optimized basis vector B.sub.OPT for the basis length L=9, as expressed in Table 1. Nine weighted current sources 602 having respective optimized weights B.sub.OPT=[1, 2, 4, 8, 16, 31, 43, 69, 81] are controlled by nine respective switches (denoted by S1, . . . , S9) to generate an analog output 606 that is representative of the 8-bit digital input 204. The nine switches are controlled by nine bits 608 generated by an 8-to-9 decoder 610 based on the 8-bit digital input 204.

[0060] FIG. 7 illustrates an 8-bit DAC architecture 700 having the optimized basis vector B.sub.OPT for the basis length L=12, as expressed in Table 1. Twelve weighted current sources 702 having respective optimized weights B.sub.OPT=[1, 2, 4, 8, 11, 16, 20, 25, 27, 35, 48, 58] are controlled by 12 respective switches (denoted by S1, . . . , S12) to generate an analog output 706 that is representative of the 8-bit digital input 204. The 12 switches are controlled by 12 bits 708 generated by an 8-to-12 decoder 710 based on the 8-bit digital input 204.

[0061] It should be noted that the values of the optimized weights B.sub.OPT may differ depending on the choice of application and design parameters. For example, a different input signal distribution (e.g., uniform) or a different number of repetitions of the DE algorithm may result in different optimized basis vectors B.sub.OPT than those provided in Table 1.

[0062] In general, an optimized DAC architecture, such as the 8-bit DAC architectures 600 and 700, comprises an N-to-L decoder which maps or converts the N-bit digital input x to an L-bit representation of the digital input W(x). The N-to-L decoder may also be referred to as a mapping. Since the optimized DAC architecture has an over-complete basis, there may exist multiple different representations W(x) for a given N-bit digital input x. For example, referring to FIG. 6, the same output current 606 may be generated when the nine signals 608 have respective values 000100000 or 000011111, since 16+8+4+2+1=31. The mapping of the decoder dictates which representation W(x) is to be used for each input x.

[0063] According to some examples, the mapping of the N-to-L decoder may be configured to minimize or reduce errors in the analog output of the DAC. For example, given the optimized basis vector B.sub.OPT and an input sequence x[j], for j=0 . . . M−1, where M is a positive integer, it may be of interest to determine the representations W(x[j]) that minimize the expected glitch error power caused by rise/fall asymmetry. The optimized representations W.sub.OPT(x[j]) may be determined by solving the expression:

[00003]$\begin{array}{cc}{W}_{OPT}\left(x\left[j\right]\right)=\underset{w\left(x\left[j\right]\right)}{\arg \min }{.Math.}_{m=1}^{M-1}{\left(e_1\left(x\left[m-1\right],x\left[m\right]\right)\right)}^2,& \left[5\right]\end{array}$$\mathrm{for}j=0..M-1.$

[0064] Equation 5 may be solved using different techniques of varying complexity. In one example, a dynamic programming algorithm, such as the Viterbi algorithm, may be used to determine the optimized representations W.sub.OPT (where the Viterbi algorithm is described, for example, by Proakis et al. in “Digital Communications”, Boston, McGraw-Hill, 2008). The complexity of this algorithm increases exponentially with L-N.

[0065] In another example, the optimized representations W.sub.OPT may be determined using a greedy “best next” algorithm which selects the best representation for x[j] based only the previous sample, expressed as:

[00004]$\begin{array}{cc}{W}_{OPT}\left(x\left[j\right]\right)=\underset{w\left(x\left[j\right]\right)}{\arg \min }{\left(e_1\left(x\left[j-1\right],x\left[j\right]\right)\right)}^2,& \left[6\right]\end{array}$$\mathrm{for}j=0..M-1.$

This approach, which uses sequential processing of samples, may be implemented through look-up tables (LUTs), where each LUT has a size of 2.sup.N+L. For a given LUT, the index/address within the LUT is determined by the representation W(x[j−1]) of the previous input x[j−1] and by the current input value x[j], and the contents of that index/address is the representation W(x[j]) of the current input x[j].

[0066] In yet another example, Equation 5 may be solved with a less sophisticated algorithm that uses only a single representation for each input value. In this case, the optimization problem may be solved iteratively such that, at each step, the representations for all inputs are fixed, and the optimized representation for x, W.sub.OPT(x), is determined as follows:

[00005]$\begin{array}{cc}{W}_{OPT}\left(x\right)=\underset{W\left(x\right)}{\arg \min }{.Math.}_{y=0}^{2^N-1}Pr\left(x,y\right){\left(.Math.W_{OPT}^T\left(y\right)-W^T\left(x\right).Math.B\right)}^2.& \left[7\right]\end{array}$

[0067] The application of Equation 7 may be repeated for each value of x to determine the best representations for all values of x. The whole process may also be reiterated until the solutions remain unchanged from one iteration to the next.

[0068] FIGS. 8 and 9 illustrate plots 800 and 900 of normalized MSE and signal-to-noise distortion ratio (SNDR), respectively, due to rise/fall asymmetry as a function of basis length for several optimized 8-bit DAC architectures in accordance with some examples of the proposed technology, relative to several segmented 8-bit DAC architectures. In each instance, the normalized MSE has been normalized by the MSE associated with a unary-weighted 8-bit DAC.

[0069] The results in FIGS. 8 and 9 were obtained using simulations. The optimized 8-bit DAC architectures used the optimized basis vectors B.sub.OPT as provided in Table 1 for basis lengths L=9, 10, 11, 12, and 13. For each optimized basis vector B.sub.OPT, the optimized representations W.sub.OPT were determined using three different algorithms: a Viterbi algorithm (VITERBI—diamonds), a greedy best next algorithm (GBN—closed circles), and a single representation algorithm (1 REP—open circles). The MSE and SNDR associated with the various optimized architectures were compared to the MSE and SNDR associated with three different segmented architectures. The segmented architecture of basis length L=9 corresponds to the DAC architecture 400, wherein the six LSB of the 8-bit digital input are provided to six binary-weighted current sources, and the two MSB of the 8-bit digital input are provided to three unary-weighted current sources. The segmented architecture of basis length L=12 comprises five binary-weighted current sources (for the five LSB of the 8-bit digital input) and seven unary-weighted current sources (for the three MSB of the 8-bit digital input). The segmented architecture of basis length L=19 comprises four binary-weighted current sources (for the four LSB of the 8-bit digital input) and 15 unary-weighted current sources (for the four MSB of the 8-bit digital input).

[0070] As is apparent from FIGS. 8 and 9, an optimized architecture (i.e., having the basis vector B.sub.OPT as provided in Table 1, for example) may achieve a lower MSE due to rise/fall asymmetry and a higher SNDR than a segmented architecture having the same number of switchable current sources, regardless of which technique is used to determine the optimized representations W.sub.OPT for the optimized architecture (i.e., Viterbi, GBN, 1 REP). For example, the performance of the segmented DAC with 12 switchable current sources is exceeded by that of the optimized DAC architecture comprising 12 switchable current sources.

[0071] It is also apparent from FIGS. 8 and 9 that an optimized architecture may achieve a similar or better performance than a segmented architecture having more switchable current sources. For example, the performance of the 10-switch optimized architecture (when the optimized representations W.sub.OPT have been determined using the Viterbi algorithm) exceeds the performance of the 19-switch segmented DAC. Even when the optimized representations W.sub.OPT have been determined using less complicated algorithms, the performance of the 19-switch segmented DAC may still be either matched or exceeded by an optimized DAC architecture that comprises fewer switchable current sources. Advantageously, a decrease in the number of switchable current sources may allow for a decrease in the overall chip size.

[0072] Although not explicitly shown, the simulations also demonstrated that the impact of rise/fall asymmetry on SFDR in the optimized DAC was comparable to the impact in a unary-weighted DAC (or a 19-switch segmented DAC).

[0073] The optimized representations W.sub.OPT were determined based on modeling of statistical error metrics. However, it is also contemplated that the optimized representations W.sub.OPT may be determined using real measurements of rise/fall asymmetry in a given DAC.

[0074] Static Errors Arising from Current Amplitude Mismatches

[0075] Mismatches between the amplitudes of the currents generated by the switchable current sources of the DAC may contribute to signal degradation. The DAC architecture may be configured to minimize the power of errors that arise from current amplitude mismatches between the switchable current sources of the DAC.

[0076] FIG. 10 illustrates a plot 1000 of current amplitude mismatches between switchable current sources in accordance with some examples. The current amplitude errors associated with the L current sources may be denoted by a vector Δ of size L, where the current amplitude error associated with the i.sup.th current source is denoted by Δ.sub.i, for i=1 . . . L. In the following example, the mismatch for the i.sup.th current source is statistically modeled as an uncorrelated Gaussian random variable with a standard deviation of √{square root over (B.sub.i)}σ.sub.δ, where σ.sub.δ denotes the standard deviation of the unit current source (corresponding to the LSB). For a digital input x, the current mismatch may cause an error e.sub.m(x) at the receiver expressed as:

e.sub.2(x)=Σ.sub.i=1.sup.L(W.sub.i(x)−Σ.sub.x=0.sup.2.sup.N.sup.−1Pr(x)W.sub.i(x))Δ.sub.i  [8]

where W.sub.i(x) denotes the i.sup.th element of the binary vector W(x), where W(x) satisfies Equation 1, and where Pr(x) is the probability distribution of the digital input x.

[0077] The MSE as a result of the current amplitude errors Δ for the digital input x may be expressed as:

[|e.sub.2|.sup.2]=σ.sub.δ.sup.2Σ.sub.i=1.sup.LΣ.sub.x=0.sup.2.sup.N.sup.−1Pr(x)W.sub.i(x)(1−Σ.sub.x=0.sup.2.sup.N.sup.−1Pr(x)W.sub.i(x))B.sub.i.  [9]

The representations W.sub.i(x) for i=1 . . . L used in Equation 9 may influence the performance of the DAC. Determining the optimized set of representations W.sub.OPT for all values of x is a discrete non-convex optimization problem that becomes more computationally expensive as L increases. An iterative approach may be used to determine the optimized representations W.sub.OPT(y). According to this approach, for a given basis vector B, all representations W are calculated for each input value x; W.sub.OPT(x) is initialized with a random representation for x=0 . . . 2.sup.N−1; and for each input value y, a global search is used to select the optimized representation W.sub.OPT(y) according to the expression:

[00006]$\begin{array}{cc}{W}_{OPT}\left(y\right)=\underset{W\left(y\right)}{\arg \min }{.Math.}_{i=1}^L{.Math.}_{x=0}^{2^N-1}Pr\left(x\right)W_{OPT,i}\left(x\right)\left(1-{.Math.}_{x=0}^{2^N-1}Pr\left(x\right)W_{OPT,i}\left(x\right)\right)B_i.& \left[10\right]\end{array}$

The search step may be repeated for a predetermined number of iterations or until W.sub.OPT(y) remains the same, whichever occurs first.

[0078] For a selected basis length L satisfying N<L<2.sup.N−1, the DAC architecture may be optimized by determining the weights B.sub.OPT that minimize the MSE in Equation 9. This optimization problem may be expressed as:

[00007]$\begin{array}{cc}{B}_{opt}=\underset{B}{\arg \min }\left(\underset{0\le x<2^N}{\underset{W\left(x,B\right)}{\arg \min }}{.Math.}_{i=1}^L{.Math.}_{x=0}^{2^N-1}Pr\left(x\right)W_i\left(x\right)\left(1-{.Math.}_{x=0}^{2^N-1}Pr\left(x\right)W_i\left(x\right)\right)B_i\right),& \left[11\right]\end{array}$

where the notation W(x,B) highlights that each binary vector W is a function of the basis vector B. According to some examples, the optimized basis vector B.sub.OPT for basis length L may be computed using simulated annealing.

[0079] A computer simulation was performed wherein a simulated annealing algorithm was used to determine the optimized basis vector B.sub.OPT of an 8-bit DAC for different basis lengths L=9, 10, 11, 12, 13, 14, and 15. The simulated annealing algorithm was run 100 times and the best basis vector B.sub.OPT (i.e., the one that achieved the lowest current amplitude mismatch error) for each basis length L is shown in Table 2, where the weights in each vector B.sub.OPT are normalized by the minimum weight. In each case, it will be apparent that the sum of the normalized weights is 2.sup.8−1=255. The optimized basis vectors B.sub.OPT in Table 2 are configured to minimize errors caused by current amplitude mismatch.

TABLE-US-00002 TABLE 2 Basis Length L Optimized Basis Vector B.sub.OPT 9 [1, 2, 4, 8, 16, 32, 35, 77, 80] 10 [1, 2, 4, 8, 16, 17, 32, 33, 70, 72] 11 [1, 2, 4, 8, 8, 16, 17, 32, 33, 66, 70] 12 [1, 2, 4, 7, 8, 15, 15, 23, 25, 30, 61, 64] 13 [1, 2, 4, 6, 8, 9, 12, 16, 17, 25, 32, 61, 66] 14 [1, 2, 4, 4, 9, 9, 13, 14, 15, 22, 25, 25, 53, 59] 15 [1, 2, 4, 4, 7, 8, 13, 13, 14, 15, 17, 24, 28, 54, 55]

[0080] It is noted that different simulation parameters may result in different values for the optimized weights B.sub.OPT than those provided in Table 2.

[0081] In Equation 10, the optimized representations W.sub.OPT(y) are calculated based on the minimization of the statistical error power (i.e., the expected error variance over many DAC samples). However, real measurements of the current amplitude error Δ.sub.i in a given DAC may be used to determine optimized representations Ŵ.sub.OPT(x) as follows:

[00008]$\begin{array}{cc}{\hat{W}}_{OPT}\left(x\right)=\underset{W\left(x\right)\in R\left(x\right)}{\arg \min }{.Math.{.Math.}_{i=1}^L{W}_i\left(x\right){\Delta }_i.Math.}^2& \left[12\right]\end{array}$

[0082] FIGS. 11 and 12 illustrate plots 1100 and 1200 of normalized MSE and SNDR, respectively, due to current amplitude mismatch as a function of basis length for several optimized 8-bit DAC architectures in accordance with some examples of the proposed technology, relative to several segmented 8-bit DAC architectures. In each instance, the normalized MSE has been normalized by the MSE associated with a unary-weighted 8-bit DAC.

[0083] The results in FIGS. 11 and 12 were obtained using simulations. The optimized 8-bit DAC architectures used the optimized basis vectors B.sub.OPT as provided in Table 2 for basis lengths L=9, 10, 11, 12, 13, 14, and 15. For each optimized basis vector B.sub.OPT, the optimized representations W.sub.OPT were determined using simulated annealing. Current amplitude mismatches were assumed to have an uncorrelated Gaussian distribution. The MSE and SNDR associated with the various optimized architectures were compared to the MSE and SNDR associated with three different segmented architectures, as described previously with respect to FIGS. 8 and 9.

[0084] As is apparent from FIGS. 11 and 12, an optimized architecture (i.e., having the basis vector B.sub.OPT as provided in Table 2, for example) may achieve a lower MSE and a higher SNDR than a segmented architecture having the same number of switchable current sources. For example, the performance of the 12-switch segmented DAC is exceeded by that of the 12-switch optimized DAC architecture.

[0085] It is also apparent from FIGS. 11 and 12 that an optimized architecture may achieve a similar or better performance than a segmented architecture having more switchable current sources. For example, the performance of the 12-switch optimized DAC architecture is similar to that of the 19-switch segmented DAC. As noted previously, the ability to achieve similar performance using fewer switchable current sources may be advantageous when chip area is limited.

[0086] Glitch Errors Arising from Timing Offsets

[0087] In addition to rise/fall asymmetry, glitch errors may also be caused by timing offsets between the switches of the DAC, that is, differences between the transition times (OFF-to-ON and/or ON-to-OFF) of the switches.

[0088] FIG. 13 illustrates a plot 1300 of OFF-to-ON timing offsets between switchable current sources in accordance with some examples. The timing offset (or skew) associated with the OFF-to-ON transition of L switchable current sources may be denoted by a vector t of size L, where the timing offset associated with the i.sup.th switch is denoted by τ.sub.i, for i=1 . . . L, where τ.sub.i is normalized by the sampling period T and satisfies −½≤τ.sub.i≤½. For a transition from a digital input x to a digital input y, the glitch error caused by timing offset at time t, where −T/2<t≤T/2, may be expressed as:

[00009]$\begin{array}{cc}{e}_3\left(t\right)={.Math.}_{i=1}^L{c}_i\left(x,y\right)B_i.Math.\left(\frac{t-{\tau }_i/2}{.Math.{\tau }_i.Math.}\right)\mathrm{sgn}\left({\tau }_i\right)& \left[13\right]\end{array}$

where c.sub.i(x,y) represents the difference between W.sub.i(y) and W.sub.i(x), such that c.sub.i(x,y)ϵ{+1, 0, −1} where sgn is the sign function, and where:

[00010]$\begin{array}{cc}.Math.\left(t\right)=\{\begin{array}{c}0,.Math.t.Math.>\frac{1}{2}\\ \frac{1}{2},.Math.t.Math.=\frac{1}{2}\\ 1,.Math.t.Math.<\frac{1}{2}\end{array}.& \left[14\right]\end{array}$

[0089] For the transition from x to y, the MSE of the glitch error metric e.sub.3(t) associated with timing offsets may be expressed as:

[00011]$\begin{array}{cc}C\left(x,y\right)=\frac{1}{T}𝔼\left[{\int }_{-\frac{T}{2}}^{\frac{T}{2}}{.Math.e_3\left(t\right).Math.}^2\mathrm{dt}\right],& \left[15\right]\end{array}$

For an over-complete basis, the total MSE due to timing offsets may be expressed as:

[00012]$\begin{array}{cc}𝔼\left[{.Math.e_3.Math.}^2\right]={.Math.}_{x=0}^{2^N-1}{.Math.}_{y=0}^{2^N-1}Pr\left(x,y\right){.Math.}_{w\left(x\right)\in R\left(x\right)}\mathrm{Pr}\left(W\left(x\right)\right)\underset{W\left(y\right)\in R\left(y\right)}{\min }C\left(x,y\right)& \left[16\right]\end{array}$

where R(x) and R(y) denote the set of all possible representations for the inputs x and y, respectively, where Pr(x,y) denotes the transition probability from input x to input y, and where Pr(W(x)) denotes the probability distribution of representations of input x.

[0090] For a selected basis length L satisfying N<L<2.sup.N−1, the DAC architecture may be optimized by determining the weights B.sub.OPT that minimize the total MSE. This optimization problem, expressed as:

[00013]$\begin{array}{cc}{B}_{\mathrm{OPT}}=\underset{B}{\mathrm{argmin}}\left(𝔼\left[{.Math.e_3.Math.}^2\right]\right),& \left[17\right]\end{array}$

may be simplified by assuming a uniform distribution for Pr(W(x)). According to some examples, the optimized basis vector B.sub.OPT for basis length L may be computed using simulated annealing.

[0091] A computer simulation was performed wherein a simulated annealing algorithm was used to determine the optimized basis vector B.sub.OPT of an 8-bit DAC for different basis lengths L=9, 10, 11, 12, 13, and 14. The simulated annealing algorithm was run 100 times and the best basis vector B.sub.OPT (i.e., the one that achieved the lowest glitch error power) for each basis length L is shown in Table 3, where the weights in each vector B.sub.OPT are normalized by the minimum weight. In each case, it will be apparent that the sum of the normalized weights is 2.sup.8−1=255. The optimized basis vectors B.sub.OPT in Table 3 are configured to minimize glitch errors caused by timing offset.

TABLE-US-00003 TABLE 3 Basis Length L Optimized Basis Vector B.sub.OPT 9 [1, 2, 4, 8, 16, 31, 43, 69, 81] 10 [1, 2, 4, 8, 16, 21, 31, 39, 62, 71] 11 [1, 2, 4, 8, 13, 18, 26, 30, 38, 54, 61] 12 [1, 2, 4, 8, 11, 16, 20, 25, 27, 35, 48, 58] 13 [1, 2, 4, 8, 14, 16, 18, 21, 25, 27, 30, 33, 56] 14 [1, 2, 4, 8, 12, 13, 14, 15, 18, 21, 26, 31, 35, 55]

[0092] It is noted that different simulation parameters may result in different values for the optimized weights B.sub.OPT than those provided in Table 3.

[0093] Given the optimized basis vector B.sub.OPT and an input sequence x[j], for j=1 . . . M−1, it is of interest to determine the representations of x[j] that minimize the expected glitch error power caused by timing offsets. The optimized representations W.sub.OPT (x[j]) may be determined by solving the expression:

[00014]$\begin{array}{cc}{W}_{OPT}\left(x\left[j\right]\right)=\underset{W\left(x\left[j\right]\right)}{\mathrm{argmin}}{.Math.}_{m=1}^{M-1}\left(C\left(x\left[m-1\right],x\left[m\right]\right)\right),\mathrm{for}j=0.Math.M-1& \left[18\right]\end{array}$

[0094] As described with respect to Equation 5, various algorithms may be used to solve Equation 18, including for example, the Viterbi algorithm, the greedy best next algorithm, and the single representation algorithm.

[0095] FIGS. 14 and 15 illustrate plots 1400 and 1500 of normalized MSE and SNDR, respectively, due to timing offsets as a function of basis length for several optimized 8-bit DAC architectures in accordance with some examples of the proposed technology, relative to several segmented 8-bit DAC architectures. In each instance, the normalized MSE has been normalized by the MSE associated with a unary-weighted 8-bit DAC.

[0096] The results in FIGS. 14 and 15 were obtained using simulations. The optimized 8-bit DAC architectures used the optimized basis vectors B.sub.OPT as provided in Table 3 for basis lengths L=9, 10, 11, 12, 13, and 14. For each optimized basis vector B.sub.OPT, the optimized representations W.sub.OPT were determined using three different algorithms: a Viterbi algorithm (VITERBI—diamonds), a greedy best next algorithm (GBN—closed circles), and a single representation algorithm (1 REP—open circles). The MSE and SNDR associated with the various optimized architectures were compared to the MSE and SNDR associated with three different segmented architectures, as described previously with respect to FIGS. 8 and 9.

[0097] As is apparent from FIGS. 14 and 15, an optimized architecture (i.e., having the basis vector B.sub.OPT as provided in Table 3, for example) may achieve a lower MSE due to timing offsets and a higher SNDR than a segmented architecture having the same number of switchable current sources, regardless of which technique is used to determine the optimized representations W.sub.OPT for the optimized architecture (i.e., Viterbi, GBN, 1 REP). For example, the performance of the 12-switch segmented DAC is exceeded by that of the 12-switch optimized DAC architecture.

[0098] It is also apparent from FIGS. 14 and 15 that an optimized architecture may achieve a similar or better performance than a segmented architecture having more switchable current sources. For example, the performance of the 13-switch optimized architecture (when the optimized representations W.sub.OPT have been determined using the Viterbi algorithm) exceeds the performance of the 19-switch segmented DAC. Even when the optimized representations W.sub.OPT have been determined using less complicated algorithms, the performance of the 19-switch segmented DAC may still be either matched or exceeded by an optimized DAC architecture that comprises fewer switchable current sources.

[0099] The optimized representations W.sub.OPT were determined based on modeling of statistical error metrics. However, it is also contemplated that the optimized representations W.sub.OPT may be determined using real measurements of timing skew in a given DAC.

[0100] In general, the simulation results plotted in FIGS. 8, 9, 11, 12, 14, and 15 demonstrate that an optimized DAC architecture may achieve similar (or even better) performance than a segmented DAC architecture having more switchable current sources. Expressed differently, an optimized DAC architecture may achieve better performance than a segmented DAC architecture having the same number of switchable current sources.

[0101] In the preceding examples, optimized DAC architectures were determined by minimizing statistical error metrics for glitch errors caused by rise/fall asymmetry or timing skew and current amplitude mismatch errors. It is contemplated that optimized DAC architectures may also be designed based on minimization of additional or alternative error metrics. For example, a statistical error metric may be derived that represents a combination of multiple sources of errors, such as the combined contributions of rise/fall asymmetry and timing skew to glitch errors, and the DAC architecture may be optimized to simultaneously limit both glitch error contributions. In another example, rather than optimizing DAC architectures based on modeling of statistical error metrics, the optimization may be performed on a per-chip or per-device basis using real measurements of errors such as rise/fall asymmetry, current amplitude mismatch, and timing skew.

[0102] While the optimized weights may include some unary weights and/or some binary weights, the optimized weights do not (exclusively) consist of unary weights or binary weights. Nor do the optimized weights (exclusively) consist of a combination of unary weights and binary weights (i.e., a hybrid or segmented architecture). In general, it may be shown that a weight ratio of at least one pair of the weighted current sources in an optimized architecture is a positive real number different from an integer power of two. That is, the pair of weights of at least one pair of weighted current sources has a ratio that differs from 2.sup.K, where K is any whole number (i.e., including zero). It will be apparent that this characteristic necessarily excludes unary-weighting (as illustrated in FIG. 1), binary weighting (as illustrated in FIG. 2), and combined unary/binary weighting (as illustrated in FIG. 3). In contrast, each optimized basis vector B.sub.OPT provided in Tables 1, 2, and 3 exhibits this characteristic.

[0103] FIG. 16 illustrates an example method 1600 for digital-to-analog conversion. The method 1600 may be performed by circuitry of an electronic apparatus, such as the optical transmitter 100. For example, aspects of the method 1600 may be implemented within any of the DACs 130, 131, 138, 139.

[0104] At 1602, L signals representing an N-bit digital input are generated based on a mapping, where N and L are positive integers, and where N<L<.sub.2.sup.N−1. For example, the L signals may be generated by circuitry comprising an N-to-L decoder which maps or converts the N-bit digital input to an L-bit representation of the digital input, where the L signals are the L bits output by the N-to-L decoder. For example, the 8-to-9 decoder 610 generates L=9 signals 608 based on the 8-bit digital input 204. In another example, the 8-to-12 decoder 710 generates L=12 signals 708 based on the 8-bit digital input 204. According to some examples, the mapping is programmable, such that the manner in which the L output bits represent the N input bits may be selected or modified through programming. The mapping may be stored in circuitry of the DAC.

[0105] At 1604, current flow from L weighted current sources is controlled using the L respective signals generated at 1602, thereby generating an analog output that uniquely represents the N-bit digital input, wherein a weight ratio of a least one pair of the weighted current sources is a positive real number different from an integer power of two. According to some examples, the weighted current sources have weights configured to minimize at least one error metric associated with the analog output. For example, the nine signals 608 control current flow from the nine respective weighted current sources 602 to generate the analog output 606 that uniquely represents the 8-bit digital input 204. In this particular example (illustrated in FIG. 6), the nine weighted current sources have respective weights [1, 2, 4, 8, 16, 31, 43, 69, 81] configured to minimize the MSE caused by rise/fall asymmetry between currents flowing from the weighted current sources. In another example, the weights may be configured to minimize errors caused by amplitude mismatches between currents flowing from the weighted current sources. For example, where the 8-bit DAC architecture of basis length L=9 is optimized to minimize the MSE caused by current amplitude mismatches, the current weights (basis vector B.sub.OPT) may be set as [1, 2, 4, 8, 16, 32, 35, 77, 80], as provided in Table 2. In yet another example, the weights may be configured to minimize glitch errors caused by timing offsets of OFF-to-ON and ON-to-OFF transitions between currents flowing from the weighted current sources. For example, where the 8-bit DAC architecture of basis length L=9 is optimized to minimize the MSE caused by timing offsets, the current weights (basis vector B.sub.OPT) may be set as [1, 2, 4, 8, 16, 31, 43, 69, 81], as provided in Table 3.

[0106] According to some examples, the mapping is configured to minimize the error metric associated with the analog output.

[0107] As noted above, the optimized DAC is configured such that the number of switchable current sources L satisfies N<L<2.sup.N−1. In other words, the optimized DAC has more switches/current sources than a binary-weighted DAC (for which L=N) and has fewer switches/current sources than a unary-weighted (thermometer-coded) DAC (for which L=2.sup.N−1). Various segmented DACs may also satisfy N<L<2.sup.N−1. However, as has been demonstrated herein, segmented DACs do not employ current weights that are configured to minimize errors associated with the analog output. Accordingly, segmented DACs are not able to achieve the advantages of the proposed optimized DAC architectures, in terms of superior performance and/or reduced footprint.

[0108] The technology described thus far may provide for efficient DAC architectures based on the minimization of at least one error metric associated with the analog output of the DAC. According to some examples, the need for low-distortion, low-complexity DACs may alternatively or additionally be addressed by digital pre-compensation of DAC distortion, which will now be described in detail.

[0109] DAC distortions, such as those caused by rise/fall asymmetry, current amplitude mismatches, and timing offsets may be pre-compensated for by digital signal processing performed within the DSP.

[0110] FIG. 17 illustrates a schematic 1700 showing digital pre-compensation of DAC distortion in accordance with some examples of the proposed technology. Within a DSP, such as the DSP 126 in FIG. 1, processing of digital signals is typically performed at a higher resolution than the resolution of the DACs. For example, the DSP 126 may process digital signals at a 12-bit resolution, followed by 8-bit quantization such that the DACs 130, 131, 138, 139 ultimately receive 8-bit digital input signals. Distortion pre-compensation may be implemented with more accuracy at a higher resolution. Consequently, the pre-compensation illustrated in the example schematic 1700 is applied to a digital signal 1702 having a resolution that is greater than N bits. A distortion model 1708 may be used to generate a predicted error signal 1710 from the digital signal 1702. As will be described in more detail with respect to FIGS. 19, 21, 23, and 25, the distortion model 1708 is characterized by parameters configured to model circuit component mismatches in the DAC, including one or more of rise/fall asymmetry, current amplitude mismatches, and timing offsets. According to some examples, the DAC distortion model 1708 may be implemented with the same N-bit resolution as the DAC. Thus, an N-bit quantizer 1704 may be applied to the digital signal 1702, thereby resulting in an N-bit digital signal 1706 being provided to the DAC distortion model 1708. According to some examples, the predicted error signal 1710 generated by the DAC distortion model 1708 may be subtracted from the digital signal 1702 using a difference operation 1712, thereby resulting in a signal 1714. Where the signal 1714 has a resolution greater than N, an N-bit quantizer 1716 may be applied to the signal 1714, thereby generating an N-bit pre-compensated digital signal 1718 that is based on the predicted error signal 1710. It is this N-bit pre-compensated signal 1718 that is provided to the DAC for conversion to an analog signal. For example, where N=8, the pre-compensated digital signal 1718 may be used as the 8-bit digital input 204 described with respect to any one of FIGS. 2, 3, 4, 6, and 7.

[0111] FIG. 18 illustrates a schematic 1800 showing aspects of a signal path between a transmitter device and a receiver device in accordance with some examples of the proposed technology. At the transmitter device, a pre-compensation process 1804 may be performed on a digital signal 1802, thereby generating a pre-compensated digital signal 1806 that is provided to a DAC 1808. The pre-compensation process 1804 may involve the application of the DAC distortion model 1708 and the difference operation 1712. For example, the pre-compensated digital signal 1806 may correspond to the signal 1718. Using the pre-compensated digital signal 1806, the DAC 1808 generates an analog signal 1810 that is conveyed by the transmitter device over a communication channel 1812 to the receiver device. For example, referring to the optical transmitter 100, the analog drive signals 132, 133, 140, 141 may be conveyed (via the optical signal 122, transmitted over an optical communication channel) to an optical receiver device. At the receiver device, a Wiener filter 1816 or some other adaptive filter may be applied to a signal 1814 received over the channel 1812, thereby resulting in a filtered signal 1818. The pre-compensation process 1804 may be configured to reduce or compensate for predicted errors in the filtered signal 1818 as a result of circuit component mismatches in the DAC 1808.

[0112] The performance achieved by the pre-compensation process 1804 may depend on the design of the DAC distortion model 1708, including the parameters used to characterize the distortion model, and the values selected for those parameters. The parameters may be configured to model circuit component mismatches in the DAC comprising one or more of rise/fall asymmetry, current amplitude mismatches, and timing offsets. The following description provides examples of various distortion models designed to model these three types of circuit component mismatches, separately, and in combination.

[0113] Pre-Compensation of Rise/Fall Asymmetry

[0114] In the absence of the digital pre-compensation process 1804, the predicted error in the filtered signal 1818 at a given time index m as a result of rise/fall asymmetry in the DAC 1808 may be expressed as

e.sub.R1[m]≅(|c.sup.T[m]|*g.sub.01[m])B  [19]

wherein

c[m]=W(x[m])−W(x[m−1])  [20]

wherein

g.sub.01[m]=τ.sub.ON/OFF*f.sub.C[m]  [21]

and wherein

f.sub.C[m]=f.sub.W[m]*f.sub.CH[m]*f.sub.DAC[m]  [22]

where x[m] denotes the digital signal 1802 at time index m, where W(x[m]) denotes a binary vector of size L which is a function of x[m], where B denotes a basis vector of size L, where TON/OFF denotes the static time offset between the OFF-to-ON transient and the ON-to-OFF transient of the switchable current sources of the DAC 1808, where f.sub.W[m] denotes the impulse response of the receiver's Wiener filter 1816, where f.sub.CH[m] denotes the linear impulse response of the channel 1812, where f.sub.DAC[m] denotes the linear impulse response of the DAC 1808, and where f.sub.C[m] denotes a combined linear impulse response. Since W.sub.i(x[m]), W.sub.i(x[m−1]) ϵ{0, 1}, it follows that c.sub.i[m]ϵ{0, +1, −1}, for i=1 . . . L.

[0115] The digital pre-compensation process 1804 may apply a pre-compensation integer term p[m] to the digital signal 1802, where the term p[m] is selected to minimize the error variance of the filtered signal 1818 as a result of rise/fall asymmetry. While it possible to calculate p[m] using the Viterbi algorithm, an approximation may be used to simplify the calculation of p[m]. Specifically, it may be assumed that the pre-compensation term at each time index is small relative to the digital signal 1802 at that time index, such that p[m]<<x[m] and p[m−1]<<x[m−1]. Under this assumption, the problem may be simplified to

[00015]$\begin{array}{cc}{p}_{\mathrm{OPT}}\left[m\right]\approx \underset{p\left[m\right]}{\mathrm{argmin}}\left({.Math.e_{R1}\left[m\right]+p\left[m\right].Math.}^2\right)& \left[23\right]\end{array}$

such that the optimal pre-compensation term p.sub.OPT[m] may be calculated as

P.sub.OPT[m]=round(−e.sub.R1[m])  [24]

where “round” denotes rounding to the nearest integer.

[0116] FIG. 19 illustrates a schematic showing a first distortion model 1900 representing rise/fall asymmetry in a DAC in accordance with some examples of the proposed technology.

[0117] The first distortion model 1900 is an example of the model 1708. Thus, the signal 1902 is an example of the N-bit digital signal 1706. In the event that the first distortion model 1900 represents distortions in a non-binary DAC (such as a unary DAC or an optimized DAC), an N-to-L decoder 1904 may be applied to the N-bit digital signal 1902, thereby generating L bits 1906 used to control the L weighted current sources of the DAC.

[0118] Each one of the L bits 1906 is processed separately. The LSB, denoted as “Bit 1”, is considered as an example. At any given point in time, the Bit-1 signal 1906 has a value of either zero or one. In order to model rise/fall asymmetry in the DAC, a detector 1908 is configured to detect transitions between zero and one, over time, in the Bit-1 signal 1906. In other words, the detector 1908 is configured to detect two different two-bit sequences within the Bit-1 signal 1906: bit sequence (0, 1) and bit sequence (1, 0). For two sequential bits in the Bit-1 signal 1906 at time indices m and m−1, the detector 1908 is configured to output a value of “1” if those bits are the sequence (0, 1) or (1, 0), and to output a value of “0” of those bits are the sequence (0, 0) or (1, 1). Thus, the detector 1908 generates, over time, a binary signal 1910 which represents transitions (0-to-1 and 1-to-0) in the Bit-1 signal 1906. Because rise/fall asymmetry errors are only relevant for transitions between different values in the Bit-1 signal 1906, there is no need for the model 1900 to detect the sequences (0, 0) and (1, 1).

[0119] The signal 1910 may be convolved with filter coefficients g.sub.01 of a G-tap finite impulse response (FIR) filter, as shown at 1912, thereby resulting in a signal 1914, where G is a positive integer. A multiplication operation 1916 is used to multiply the signal 1914 by the basis vector B.sub.1 for the Bit-1 signal 1906, thereby resulting in a signal 1918. A total of L signals 1918 are generated, one for each of the L bits 1906, where the basis vector B.sub.i is used for the Bit-1 signal, for i=1 . . . L, and where the filter coefficients g.sub.01 of the same G-tap filter are used for each of the L bits 1906. A summation operation 1920 is applied to the L signals 1918, thereby resulting in a signal 1922 that represents a sum of the L signals 1918. According to some examples, the summation operation 1920 may also add a bias term (not shown) to correct for tones in the DAC output. This bias term will be described in more detail with respect to FIG. 25.

[0120] By appropriate selection of the filter coefficients g.sub.01 (i.e., the function g.sub.01 in Equation 21), the distortion model 1900 may be configured such that the signal 1922 represents the error e.sub.R1[m] due to rise/fall asymmetry. The signal 1922 is an example of the predicted error signal 1710 generated by the DAC distortion model 1708. As described with respect to FIG. 17, digital pre-compensation is achieved by subtracting the predicted error signal 1710 from the digital signal 1702 (or, equivalently, by adding the pre-compensation term p.sub.OPT[m] as expressed in Equation 24).

[0121] In order to learn the filter coefficients g.sub.01, thereby training the model 1900 such that it may be used for an arbitrary digital input signal, a reference digital signal may be used. The reference signal may be selected such that all the current cells of the DAC 1808 are exercised, and such that an adequate number of 0-to-1 transitions and 1-to-0 transitions are observed, for example, 100 of each type. In response to inputting the reference signal to the DAC 1808, an error e.sub.W[m] may be measured at the output of the Wiener filter 1816. Given the measured error e.sub.W[m], it is possible to estimate the filter coefficients g.sub.01 using the relationship in Equation 19 (with e.sub.W[m] in place of e.sub.R1[m]).

[0122] While the detector 1908 is configured to detect the two-bit sequences (0, 1) and (1,0), alternative examples are contemplated wherein bit sequences comprising more than two bits are detected using one or more detectors. Such examples will be described further with respect to FIG. 25.

[0123] The detector 1908 is configured to detect both 0-to-1 and 1-to-0 transitions, thereby resulting in a single binary signal 1910 that is convolved with a single set of filter coefficients g.sub.01. However, other examples are contemplated wherein separate detectors are configured to detect 0-to-1 and 1-to-0 transitions, respectively, thereby resulting in separate, parallel binary signals that are convolved with separate filter coefficients g.sub.01 and g.sub.10, respectively. This alternative design would enable modeling of different settling transients for an OFF-to-ON transition and an ON-to-OFF transition in a given switchable current source.

[0124] FIG. 20 illustrates a plot 2000 of SNDR due to rise/fall asymmetry as a function of the standard deviation of the rise/fall asymmetry normalized by the sampling period T for several DAC architectures with and without pre-compensation in accordance with some examples of the proposed technology.

[0125] The results in FIG. 20 were obtained using simulations. The optimized DAC architecture used the optimized basis vector B.sub.OPT as provided in Table 1 for basis length L=13, and the optimized representations W.sub.OPT were determined using a Viterbi algorithm, a greedy best next algorithm, and a single representation algorithm.

[0126] As is apparent from FIG. 20, for each DAC architecture, digital pre-compensation of distortion due to rise/fall asymmetry may achieve an improvement in SNDR. This performance enhancement is achieved when the rise/fall asymmetry error exceeds the resolution of the DAC. As expected, when the error amplitude is smaller than the resolution of the DAC, no performance enhancement is observed. A higher-resolution DAC may benefit more from digital pre-compensation than a lower-resolution DAC. The best performance is achieved by using digital pre-compensation with either the 8-bit unary-weighted DAC or the 8-bit optimized DAC exploiting the Viterbi algorithm.

[0127] Pre-Compensation of Current Amplitude Mismatches

[0128] In another example, the pre-compensation process 1804 may be configured to reduce or compensate for predicted errors in the filtered signal 1818 as a result of current amplitude mismatches. In the absence of the digital pre-compensation 1804, the error in the filtered signal 1818 at a given time index m as a result of current amplitude mismatches in the DAC 1808 may be expressed as

e.sub.R2[m]≅f.sub.C[m]*Σ.sub.i=1.sup.LW.sub.i(x[m])Δ.sub.i  [25]

where Δ denotes the current amplitude mismatch errors of the L switchable current sources.

[0129] FIG. 21 illustrates a schematic 2100 showing a second distortion model representing current amplitude mismatches in a DAC in accordance with some examples of the proposed technology.

[0130] The second distortion model 2100 is an example of the model 1708. Thus, the signal 2102 is an example of the N-bit digital signal 1706. In the event that the second distortion model 2100 represents distortions in a non-binary DAC (such as a unary DAC or an optimized DAC), an N-to-L decoder 2104 may be applied to the N-bit digital signal 2102, thereby generating L bits 2106 used to control the L weighted current sources of the DAC.

[0131] Each one of the L bits 2106 is processed separately. The LSB, Bit 1, is considered as an example. In order to model current amplitude mismatches in the DAC, a multiplication operation 2108 is used to multiply the Bit-1 signal 2106 by the current amplitude mismatch error Δ.sub.1 for the Bit-1 signal 2106, thereby resulting in a signal 2110 which represents the current error for the switchable current source handling Bit 1. A total of L signals 2110 are generated, one for each of the L bits 2106, where the current error Δ.sub.i is used for the Bit-1 signal, for i=1 . . . L. A summation operation 2112 is applied to the L signals 2110, thereby resulting in a signal 2114 that represents a sum of the L signals 2110. According to some examples, the summation operation 2112 may also add a bias term (not shown) to correct for tones in the DAC output. This bias term will be described in more detail with respect to FIG. 25. The signal 2114 may be convolved with the combined impulse response f.sub.C[m], as shown at 2116, thereby resulting in a signal 2118.

[0132] By appropriate selection of the current amplitude mismatch errors Δ, the model 2100 may be configured such that the signal 2118 represents the error e.sub.R2[m] due to current amplitude mismatches. The signal 2118 is an example of the predicted error signal 1710 generated by the DAC distortion model 1708.

[0133] As described with respect to the model 1900, the model 2100 may be trained using a reference signal. In this case, with knowledge of the combined linear impulse response f.sub.C[m], the values of current amplitude mismatch errors Δ may be estimated using a least-squares minimization expressed as:

[00016]$\begin{array}{cc}\underset{\Delta }{\mathrm{minimize}}{.Math.}_{m=0}^{M-1}{.Math.f_C\left[m\right]*{.Math.}_{i=1}^L{W}_i\left(x\left[m\right]\right){\Delta }_i-e_W\left[m\right].Math.}^2& \left[26\right]\end{array}$

where e.sub.W[m] denotes the measured error after the Wiener filter 1816 for the reference signal input to the DAC 1808, and where M denotes the length of the reference signal.

[0134] For an arbitrary input digital signal 1802, denoted x, the digital pre-compensation process 1804 may apply a pre-compensation integer term p(x) to the digital signal 1802, where the term p(x) is selected to minimize the error variance of the filtered signal 1818 as a result of current amplitude mismatches. The optimal pre-compensation term p.sub.OPT(x) may be calculated as

[00017]$\begin{array}{cc}{p}_{\mathrm{OPT}}\left(x\right)=\underset{p\left(x\right)}{\mathrm{argmin}}\left({.Math.p\left(x\right)-𝔼\left[p\left(x\right)\right]+W^T\left(x+p\left(x\right)\right)\Delta -𝔼\left[W^T\left(x+p\left(x\right)\right)\Delta \right].Math.}^2\right)& \left[27\right]\end{array}$

where −x≤p(x)≤2.sup.N−1−x. The DC effect of the pre-compensation terms may be neglected with minimal performance impact, such that the optimal pre-compensation term may be approximated by the expression

[00018]$\begin{array}{cc}{P}_{\mathrm{OPT}}\left(x\right)=\underset{p\left(x\right)}{\mathrm{argmin}}\left({.Math.p\left(x\right)+W^T\left(x+p\left(x\right)\right)\Delta .Math.}^2\right).& \left[28\right]\end{array}$

Thus, given the current amplitude mismatch errors Δ estimated using Equation 25, the optimal pre-compensation terms p.sub.OPT(x) may be calculated independently for each value of x.

[0135] As described with respect to FIG. 17, digital pre-compensation is achieved by subtracting the predicted error signal 1710 from the digital signal 1702 (or, equivalently, by adding the pre-compensation term p.sub.OPT(x)). The pre-compensation terms p.sub.OPT(x) may be stored in a LUT of size 2.sup.N.

[0136] FIG. 22 illustrates a plot 2200 of SNDR due to current amplitude mismatches as a function of the standard deviation of the current amplitude mismatches for several optimized DAC architectures with and without pre-compensation in accordance with some examples of the proposed technology.

[0137] The results in FIG. 22 were obtained using simulations (statistical selection) and DAC-specific measurements (optimal mapping). The optimized DAC architecture used the optimized basis vector B.sub.OPT as provided in Table 2 for basis length L=12.

[0138] As is apparent from FIG. 22, digital pre-compensation of distortion due to current amplitude mismatches may achieve an improvement in SNDR. This performance enhancement is achieved when the current amplitude mismatch standard deviation exceeds half an LSB. The improvement achieved by the digital pre-compensation may be increased if the pre-compensation term is applied to a higher-resolution version of the digital input signal, prior to N-bit quantization.

[0139] Pre-Compensation of Timing Offsets

[0140] In yet another example, the pre-compensation process 1804 may be configured to reduce or compensate for predicted errors in the filtered signal 1818 as a result of timing offsets. In the absence of the digital pre-compensation 1804, the predicted error in the filtered signal 1818 at a given time index m as a result of timing offsets in the DAC 1808 may be expressed as

e.sub.R3[m]=Σ.sub.i=1.sup.L((c.sub.i[m]*g.sub.i,01[m])B.sub.i)  [29]

wherein

g.sub.01[m]=τ.sub.i[m]*f.sub.C[m]  [30]

where τ.sub.i denotes the timing offset associated with the i.sup.th switch, where i=1 . . . L, and f.sub.C[m] denotes the combined linear impulse response expressed in Equation 22.

[0141] FIG. 23 illustrates a schematic 2300 showing a third distortion model representing timing offsets in a DAC in accordance with some examples of the proposed technology.

[0142] The third distortion model 2300 is an example of the model 1708. Thus, the signal 2302 is an example of the N-bit digital signal 1706. In the event that the third distortion model 2300 represents distortions in a non-binary DAC (such as a unary DAC or an optimized DAC), an N-to-L decoder 2304 may be applied to the N-bit digital signal 2302, thereby generating L bits 2306 used to control the L weighted current sources of the DAC.

[0143] Each one of the L bits 2306 is processed separately. The LSB, Bit 1, is considered as an example. At any given point in time, the Bit-1 signal 2306 has a value of either zero or one. In order to model timing offsets in the DAC, a detector 2308 is configured to detect transitions between zero and one, over time, in the Bit-1 signal 2306. Thus, similarly to the detector 1908, the detector 2308 generates, over time, a binary signal 2310 which represents transitions (0-to-1 and 1-to-0) in the Bit-1 signal 2306. Because rise/fall asymmetry errors are only relevant for transitions between different values in the Bit-1 signal 2306, there is no need for the model 2300 to detect the sequences (0, 0) and (1, 1).

[0144] The signal 2306 may be convolved with filter coefficients g.sub.1,01 of a G-tap FIR filter, as shown at 2312, thereby resulting in a signal 2314, where G is a positive integer. A multiplication operation 2316 is used to multiply the signal 2314 by the basis vector B.sub.1 for the Bit-1 signal 2306, thereby resulting in a signal 2318. A total of L signals 2318 are generated, one for each of the L bits 2306, where filter coefficients g.sub.i,01 of a distinct G-tap filter are used for the Bit-1 signal, and where the basis vector B.sub.i is used for the Bit-1 signal, for i=1 . . . L. A summation operation 2320 is applied to the L signals 2318, thereby resulting in a signal 2322 that represents a sum of the L signals 2318. According to some examples, the summation operation 2320 may also add a bias term (not shown) to correct for tones in the DAC output. This bias term will be described in more detail with respect to FIG. 25.

[0145] By appropriate selection of the filter coefficients g.sub.i,01, the model 2300 may be configured such that the signal 2322 represents the error e.sub.R3[m] due to timing offsets. Thus, as expressed in Equation 30, the filter coefficients g.sub.i,01 may be understood as corresponding to the product of f.sub.C[m] and τ.sub.i. The signal 2322 is an example of the predicted error signal 1710 generated by the DAC distortion model 1708.

[0146] As described previously with respect to the models 1900 and 2100, the model 2300 may be trained using a reference signal. In this case, the filter coefficients g.sub.i,01[m] may be estimated using a least-squares minimization expressed as:

[00019]$\begin{array}{cc}\underset{g_{1,01},.Math.g_{L,01}}{\mathrm{minimize}}{.Math.}_{m=1}^{M-1}{.Math.{.Math.}_{i=1}^L\left(\left(c_i\left[m\right]*g_{i,01}\left[m\right]\right)B_i\right)-e_W\left[m\right].Math.}^2& \left[31\right]\end{array}$

where e.sub.W[m] denotes the measured error after the Wiener filter 1816 for the reference signal input to the DAC 1808, and where M denotes the length of the reference signal.

[0147] The estimates of the functions g.sub.i,01[m] for i=1 . . . L may then be used to obtain estimates of e.sub.R3[m] using Equation 29. As previously described with respect to Equations 23 and 24, the optimal pre-compensation term p.sub.OPT[m] may be approximated as the negated predicted error e.sub.R3[m].

[0148] While the detector 2308 is configured to detect the two-bit sequences (0, 1) and (1,0), alternative examples are contemplated wherein bit sequences comprising more than two bits are detected using one or more detectors. Such examples will be described further with respect to FIG. 25.

[0149] The detector 2308 is configured to detect both 0-to-1 and 1-to-0 transitions in the Bit-1 signal 2306, thereby resulting in a single binary signal 2310 that is convolved with a single set of filter coefficients g.sub.i,01. However, other examples are contemplated wherein separate detectors are configured to detect 0-to-1 and 1-to-0 transitions, respectively, thereby resulting in separate, parallel binary signals that are convolved with separate filter coefficients g.sub.i,01 and g.sub.1,10, respectively. This alternative design would enable modeling of different settling transients for an OFF-to-ON transition and an ON-to-OFF transition in a given switchable current source.

[0150] FIG. 24 illustrates a plot 2400 of SNDR due to timing offsets as a function of the standard deviation of the timing offsets normalized by the sampling period T for several optimized DAC architectures with and without pre-compensation in accordance with some examples of the proposed technology.

[0151] The results in FIG. 24 were obtained using simulations. The optimized DAC architectures used the optimized basis vectors B.sub.OPT as provided in Table 3 for basis lengths L=9 and L=12, and the optimized representations W.sub.OPT were determined using a single representation algorithm.

[0152] As is apparent from FIG. 24, digital pre-compensation of distortion due to timing offsets may achieve an improvement in SNDR. This performance enhancement is achieved when the timing offset standard deviation exceeds the resolution of the DAC.

[0153] Pre-Compensation of Rise/Fall Asymmetry, Current Amplitude Mismatches, and Timing Offsets

[0154] The DAC distortion models 1900, 2100, and 2300 separately model rise/fall asymmetry, current amplitude mismatches, and timing offsets, respectively. It is also possible to design a model that represents a combination of DAC distortions.

[0155] In the absence of the digital pre-compensation process 1804, the error in the filtered signal 1818 at a given time index m as a result of rise/fall asymmetry, current amplitude mismatches, and timing offsets in the DAC 1808 may be expressed as

[00020]$\begin{array}{cc}{e}_R\left[m\right]={.Math.}_{i=1}^L\left(c_{i,01}\left[m\right]*g_{i,01}\left[m\right]+c_{i,10}\left[m\right]*g_{i,10}\left[m\right]+c_{i,11}\left[m\right]*g_{i,11}\left[m\right]\right)B_i& \left[32\right]\end{array}$$\mathrm{wherein}$$\begin{array}{cc}{c}_{i,kl}\left[m\right]=\{\begin{array}{c}1,\mathrm{if}{W}_i\left(x\left[m-1\right]\right)=k\mathrm{AND}{W}_i\left(x\left[m\right]=l\right)\\ 0,\mathrm{otherwise}.\end{array}& \left[33\right]\end{array}$

[0156] The functions g.sub.i,01[m] and g.sub.i,10[m] represent rise/fall asymmetry and timing offsets, which are only in effect when there is a 0-to-1 transition or a 1-to-0 transition. The function g.sub.i,11[m] represents current amplitude mismatches, which are only in effect when there is a 1-to-1 transition.

[0157] The predicted error e.sub.R[m] in Equation 32 only considers bit sequences of length J=2. However, for a higher speed DAC with limited bandwidth, it may be advantageous to bit sequences comprising more than two bits. For example, where the model considers bit sequences of length J=3, the error in the filtered signal 1818 may be expressed as

[00021]$\begin{array}{cc}{e}_R\left[m\right]={.Math.}_{i=1}^L\left({.Math.}_{j=0}^1{.Math.}_{k=0}^1{.Math.}_{\begin{array}{c}l=0\\ l\ne j=k=0\end{array}}^1{c}_{i,\mathrm{jkl}}\left[m\right]*g_{i,\mathrm{jkl}}\left[m\right]\right)B_i& \left[34\right]\end{array}$$\mathrm{wherein}$$\begin{array}{cc}{c}_{i,\mathrm{jkl}}\left[m\right]=\{\begin{array}{c}1,\mathrm{if}{W}_i\left(x\left[m-1\right]\right)=j\mathrm{AND}{W}_i\left(x\left[m\right]\right)=k\\ \mathrm{AND}{W}_i\left(x\left[m+1\right]=l\right)\\ 0,\mathrm{otherwise}.\end{array}& \left[35\right]\end{array}$

[0158] The functions g.sub.i,000[m] and g.sub.i,111[m] represent current amplitude mismatches, which are only in effect when the bit sequence is (0, 0, 0) or (1, 1, 1), while the remaining six functions represent rise/fall asymmetry and timing offsets, which are only in effect when the bit sequence is (0, 0, 1), (1, 1, 0), (0, 1, 0), (1, 0, 1), (0, 1, 1), or (1, 0, 0).

[0159] The DAC output may comprise dominant tones at f.sub.S/2 and f.sub.S/4, where f.sub.S denotes the sampling frequency. In order to correct for these tones, a bias term may be added to each modulo-4 phase of the result in Equation 34, such that the predicted error is expressed as

[00022]$\begin{array}{cc}{e}_R\left[m\right]={.Math.}_{i=1}^L\left({.Math.}_{j=0}^1{.Math.}_{k=0}^1{.Math.}_{\begin{array}{c}l=0\\ l\ne j=k=0\end{array}}^1{c}_{i,\mathrm{jkl}}\left[m\right]*g_{i,\mathrm{jkl}}\left[m\right]\right)B_i+b_{m\mathrm{mod}4}& \left[36\right]\end{array}$

[0160] FIG. 25 illustrates a schematic 2500 showing a fourth distortion model representing rise/fall asymmetry, current amplitude mismatches, and timing offsets in a DAC in accordance with some examples of the proposed technology.

[0161] The fourth distortion model 2500 is an example of the model 1708. Thus, the signal 2502 is an example of the N-bit digital signal 1706. In the event that the fourth distortion model 2500 represents distortions in a non-binary DAC (such as a unary DAC or an optimized DAC), an N-to-L decoder 2504 may be applied to the N-bit digital signal 2502, thereby generating L bits 2506 used to control the L weighted current sources of the DAC.

[0162] Each one of the L bits 2506 is processed separately. The LSB, Bit 1, is considered as an example. At any given point in time, the Bit-1 signal 2506 has a value of either zero or one. As previously described with respect to the models 1900 and 2300, rise/fall asymmetry and timing offsets may be modeled using a detector configured to detect transitions between zero and one, over time, in the Bit-1 signal (i.e., two-bit sequences (0, 1) and (1, 0)). However, more accurate modeling of the DAC distortions may be achieved by using detectors configured to detect sequences of more than two bits. For example, the model 2500 uses four detectors 2508, 2510, 2512, and 2514 to detect three-bit sequences in the Bit-1 signal 2506. Specifically, the detector 2508 is configured to generate a binary signal 2516 representing the presence of the three-bit sequences (0, 0, 1) and (1, 1, 0); the detector 2510 is configured to generate a binary signal 2518 representing the presence of the three-bit sequences (0, 1, 0) and (1, 0, 1); the detector 2512 is configured to generate a binary signal 2520 representing the presence of the three-bit sequences (0, 1, 1) and (1, 0, 0); and the detector 2514 is configured to generate a binary signal 2522 representing the presence of the three-bit sequences (0, 0, 0) and (1, 1, 1).

[0163] The signals 2516, 2518, 2520, and 2522 may be convolved with respective filter coefficients g.sub.1,001, g.sub.1,010, g.sub.1,011, and g.sub.1,000 of four G-tap FIR filters, as shown at 2524, 2526, 2528, and 2530, respectively, where G is a positive integer, thereby resulting in respective signals 2532, 2534, 2536, and 2538. A summation operation 2540 may be applied to the signals 2532, 2534, 2536, and 2538, thereby resulting in a signal 2542. A multiplication operation 2544 is used to multiply the signal 2542 by the basis vector B.sub.1 for the Bit-1 signal 2506, thereby resulting in a signal 2546. A total of L signals 2546 are generated, one for each of the L bits 2506, where the filter coefficients g.sub.1,001, g.sub.1,010, g.sub.1,011, and g.sub.1,000 of a distinct set of G-tap filters are used for the Bit-1 signal, and where the basis vector B.sub.i is used for the Bit-1 signal, for i=1 . . . L. A summation operation 2548 is applied to the L signals 2546 and to a bias term 2550, thereby resulting in a signal 2552 that represents a sum of the L signals 2546 and the bias term 2550.

[0164] By appropriate selection of the filter coefficients g.sub.1,001, g.sub.1,010, g.sub.1,011, and g.sub.1,000, the model 2500 may be configured such that the signal 2552 represents the error e.sub.R[m] due to on/off asymmetry, current amplitude mismatches, and timing offsets. The signal 2552 is an example of the predicted error signal 1710 generated by the DAC distortion model 1708.

[0165] The model 2500 may be trained using a reference signal. As described previously, the reference signal may be selected such that all the current cells of the DAC are exercised, and such that an adequate number of each type of three-bit sequence is observed, for example, 100 of each type. In the case of the model 2500, the filter coefficients g.sub.1,001[m], g.sub.1,010[m], g.sub.1,011[m], and g.sub.1,000[m], and the bias term b.sub.m mod 4 may be estimated using the 12-norm (or Euclidean norm) minimization expressed as:

[00023]$\begin{array}{cc}\underset{g,b}{\mathrm{minimize}}{.Math.}_{m=1}^{M-1}{.Math.{.Math.}_{i=1}^L\left({.Math.}_{j=0}^1{.Math.}_{k=0}^1{.Math.}_{\begin{array}{c}l=0\\ l\ne j=k=0\end{array}}^1{c}_{i,\mathrm{jkl}}\left[m\right]*g_{i,\mathrm{jkl}}\left[m\right]\right)B_i+b_{m\mathrm{mod}4}-e_W\left[m\right].Math.}^2& \left[37\right]\end{array}$

where e.sub.W[m] denotes the measured error after the Wiener filter 1816 for the reference signal input to the DAC 1808, and where M denotes the length of the reference signal.

[0166] The estimates of the functions g.sub.1,001[m], g.sub.1,010[m], g.sub.1,011[m], and g.sub.1,000[m] for i=1 . . . L and the estimate of the bias term b.sub.m mod 4 may then be used to obtain estimates of e.sub.R[m] using Equation 36. As previously described, the optimal pre-compensation term p.sub.OPT[m] may be approximated as the negated predicted error e.sub.R[m].

[0167] While the detectors 2508, 2510, 2512, and 2514 are configured to detect three-bit sequences, alternative examples are contemplated wherein bit sequences comprising more than three bits (or fewer, i.e., two bits) are detected using a plurality of detectors.

[0168] Each of the detectors 2508, 2510, 2512, and 2514 is configured to detect two different three-bit sequences. For example, the detector 2508 is configured to detect both the sequence (0, 0, 1) and the sequence (1, 1, 0) in the Bit-1 signal 2306, thereby resulting in a single binary signal 2516 that is convolved with a single set of filter coefficients g.sub.1,001. However, other examples are contemplated wherein separate detectors are configured to detect the sequence (0, 0, 1) and the sequence (1, 1, 0), respectively, thereby resulting in separate, parallel binary signals that are convolved with separate filter coefficients g.sub.1,001 and g.sub.1,100, respectively. This alternative design would enable modeling of different settling transients for an OFF-to-ON transition and an ON-to-OFF transition in a given switchable current source.

[0169] FIG. 26 illustrates a plot 2600 of SNDR due to rise/fall asymmetry, current amplitude mismatches, and timing offsets as a function of the standard deviation of the timing offsets normalized by the sampling period T for several DAC architectures with and without pre-compensation in accordance with some examples of the proposed technology.

[0170] The results in FIG. 26 were obtained using simulations with τ.sub.ON/OFF/T=0.01 and σ.sub.δ=0.05. The binary results were obtained using the 8-bit binary DAC architecture 300, while the segmented results were obtained using the 8-bit segmented DAC architecture 400.

[0171] As is apparent from FIG. 26, digital pre-compensation using the model 2500 may achieve an improvement in SNDR.

[0172] FIG. 27 illustrates an example method 2700 for digital pre-compensation of distortion in a DAC in accordance with some examples of the proposed technology. The method 2700 may be performed by circuitry of an electronic apparatus, such as the optical transmitter 100. For example, aspects of the method 2700 may be implemented within the DSP 126.

[0173] At 2702, a predicted error signal is generated by applying a distortion model to a digital signal, where the distortion model is characterized by parameters configured to model circuit component mismatches in a DAC. For example, the predicted error signal 1922 is generated by applying the distortion model 1900 to the digital signal 1902; the predicted error signal 2118 is generated by applying the distortion model 2100 to the digital signal 2102; the predicted error signal 2322 is generated by applying the distortion model 2300 to the digital signal 2302; and the predicted error signal 2552 is generated by applying the distortion model 2500 to the digital signal 2502. The parameters may comprise, for example, coefficients of the plurality of FIR filters. For example, the filter coefficients g.sub.01 (FIG. 19), g.sub.i,01 (FIG. 23), and g.sub.i,001, g.sub.i,010, g.sub.i,011, g.sub.i,000 (FIG. 25) are examples of parameters configured to model circuit component mismatches in a DAC. The current amplitude mismatches A (FIG. 21) are also examples of such parameters.

[0174] There are various types of DAC component mismatches from which signal-dependent errors/distortions may originate. For example, where the DAC comprises a plurality of weighted current sources, the circuit component mismatches may comprise one or more of rise/fall asymmetry between currents flowing from the weighted current sources; amplitude mismatches between currents flowing from the weighted current sources; and timing offsets of OFF-to-ON and ON-to-OFF transitions between currents flowing from the weighted current sources.

[0175] According to some examples, the distortion model comprises a plurality of detectors, where each detector is configured to detect sequences of J bits in the digital signal, wherein J≥2, and wherein each bit is selected from 0 and 1. Examples of the detectors include the detectors 1908 and 2308, which are configured to detect two-bit sequences, and the detectors 2508, 2510, 2512, and 2514 which are configured to detect three-bit sequences.

[0176] According to some examples, the distortion model is further characterized by a bias term configured to correct for predicted tones in the analog signal, such as the bias term 2550.

[0177] At 2704, a pre-compensated digital signal is generated using the digital signal and the predicted error signal generated at 2702. According to some examples, the pre-compensated digital signal is generated based on a difference between the digital signal and the predicted error signal. According to some examples, the pre-compensated digital signal comprises N bits per sample and the digital signal comprises more than N bits per sample, where N is a positive integer. According to some examples, the distortion model is applied to the digital signal at a resolution of N bits per sample. For example, as described with respect to FIG. 17, the pre-compensated digital signal 1718 is generated using the digital signal 1702 and the predicted error signal 1710. The pre-compensated digital signal 1718 is generated based on the difference between the digital signal 1702 and the predicted error signal 1710 (using the difference operation 1712). In this example, the N-bit quantizer 1716 ensures that the pre-compensated digital signal 1718 comprises N bits per sample, while the digital signal 1702 comprises more than N bits per sample. The N-bit quantizer 1704 ensures that the distortion model 1708 is applied at a resolution of N bits per sample.

[0178] At 2706, the pre-compensated digital signal generated at 2704 is provided to the DAC for conversion into an analog signal.

[0179] According to some examples, the method 2700 may be implemented in combination with the method 1600. For example, the pre-compensated digital signal generated at step 2704 in the method 2700 may comprise the same digital signal used at step 1602 in the method 1600. In other words, the DAC to which the pre-compensated digital signal is provided at 2706 may comprise a plurality of weighted current sources, wherein a weight ratio of at least one pair of the weighted current sources is a positive real number different from an integer power of two.

[0180] The scope of the claims should not be limited by the details set forth in the examples, but should be given the broadest interpretation consistent with the description as a whole.