OPERATIONAL AMPLIFIER, DRIVE CIRCUIT, INTERFACE CHIP, AND ELECTRONIC DEVICE

Abstract

An operational amplifier, a drive circuit, an interface chip (1201, 1301, 1401, 1501), and an electronic device (1600) relate to the field of power electronics technologies. The operational amplifier includes a first load (R1), a second load (R2), a first switching transistor group (301-1), a second switching transistor group (301-2), and a tail current source (203). The first switching transistor group (301-1) has a first end connected to a first output end (outp) of the operational amplifier and connected to a power supply (VDD) of the operational amplifier by using the first load (R1), and has a second end grounded by using the tail current source (203). The second switching transistor group (301-2) has a first end connected to a second output end (outn) of the operational amplifier.

Claims

1. An operational amplifier, wherein the operational amplifier comprises: a first load, a second load, a first switching transistor group, a second switching transistor group, and a tail current source; a first end of the first switching transistor group is connected to a first output end of the operational amplifier, and is connected to a power supply of the operational amplifier by using the first load, and a second end of the first switching transistor group is grounded by using the tail current source; a first end of the second switching transistor group is connected to a second output end of the operational amplifier, and is connected to the power supply by using the second load, and a second end of the second switching transistor group is grounded by using the tail current source; the first switching transistor group and the second switching transistor group comprise a same quantity of at least two input adjustment units, and an input end of each of the input adjustment units is connected to an input signal; and the input signal connected to each of the input adjustment units is adjustable.

2. The operational amplifier according to claim 1, wherein the input adjustment unit comprises a first selector switch and a first switching transistor; the first selector switch is connected to a control end of the first switching transistor; and the first selector switch is configured to select an input signal to be connected to the control end of the first switching transistor.

3. The operational amplifier according to claim 1, wherein the input signal comprises the following two signals: a first input signal and a second input signal; in the first switching transistor group, a first quantity of input adjustment units is connected to the first input signal, and a second quantity of input adjustment units is connected to the second input signal; in the second switching transistor group, the second quantity of input adjustment units is connected to the first input signal, and the first quantity of input adjustment units is connected to the second input signal; and the first quantity is not equal to the second quantity.

4. The operational amplifier according to claim 3, wherein the first selector switch selects a to-be-connected input signal based on an adjustment signal, and the first selector switch selects to connect to the first input signal when the adjustment signal is a first level or selects to connect to the second input signal when the adjustment signal is a second level.

5. The operational amplifier according to claim 3, wherein the first quantity is greater than the second quantity, to enable an output gain of the operational amplifier to be of a first polarity, and when the output gain is of the first polarity, the operational amplifier is configured to amplify the input signal; or the first quantity is less than the second quantity, to enable an output gain of the operational amplifier to be of a second polarity, and when the output gain is of the second polarity, the operational amplifier is configured to scale down the input signal.

6. The operational amplifier according to claim 2, wherein the input signal comprises the following two signals: a first input signal and a second input signal; in the first switching transistor group, a first quantity of input adjustment units is connected to the first input signal, and a second quantity of input adjustment units is connected to the second input signal; a third quantity of input adjustment units in the second switching transistor group is connected to the first input signal, and the third quantity is equal to a sum of the first quantity and the second quantity.

7. The operational amplifier according to claim 6, wherein the first selector switch selects a to-be-connected input signal based on an adjustment signal; and the first selector switch selects to connect to the first input signal when the adjustment signal is a first level; or the input signal selector switch selects to connect to the second input signal when the adjustment signal is a second level.

8. The operational amplifier according to claim 6, wherein the first selector switch selects a to-be-connected input signal based on an adjustment signal; and the first selector switch of the first switching transistor group selects to connect to the first input signal when the adjustment signal is a first level or selects to connect to the second input signal when the adjustment signal is a second level; and the first selector switch of the second switching transistor group selects to connect to the first input signal when the adjustment signal is a second level or selects to connect to the second input signal when the adjustment signal is a first level.

9. The operational amplifier according to claim 1, wherein each of the input signals comprises at least the following two signals: a common-mode signal and a reference signal.

10. The operational amplifier according to claim 9, wherein the operational amplifier further comprises a voltage divider circuit, an input end of the voltage divider circuit is connected to the power supply of the operational amplifier, and an output end of the voltage divider circuit is configured to output the reference signal; and the voltage divider circuit is configured to convert a voltage provided by the power supply into the reference signal.

11. A low voltage differential signal drive circuit, wherein the low voltage differential signal drive circuit comprises the operational amplifier according to claim 1, and further comprises a low voltage differential signal generation circuit; an input end of the low voltage differential signal generation circuit is connected to the power supply, and a feedback signal end of the low voltage differential signal generation circuit is connected to the first output end of the operational amplifier or the second output end of the operational amplifier; the low voltage differential signal generation circuit is configured to output a common-mode signal, and the common-mode signal is a first input signal of the operational amplifier; and an output end of the low voltage differential signal generation circuit is configured to output a low voltage differential signal.

12. The low voltage differential signal drive circuit according to claim 11, wherein a reference signal is a second input signal of the operational amplifier; the operational amplifier further comprises a voltage divider circuit, an input end of the voltage divider circuit is connected to the power supply, and an output end of the voltage divider circuit is configured to output the reference signal; and the voltage divider circuit is configured to convert a voltage provided by the power supply into the reference signal.

13. A gain adjustment method for an operational amplifier, wherein the operational amplifier comprises a first switching transistor group and a second switching transistor group, the first switching transistor group and the second switching transistor group comprise a same quantity of at least two input adjustment units, an input end of each of the input adjustment units is configured to connect to an input signal, and the method comprises: determining a target gain; and determining an adjustment signal based on the target gain, and sending the adjustment signal to the first switching transistor group and the second switching transistor group, wherein the adjustment signal is for adjusting the input signal connected to the input adjustment unit.

14. An interface chip, wherein the interface chip comprises the operational amplifier according to claim 1, and the interface chip comprises a power port, a first output port, a second output port, a grounding port, a control port, and a first input port; the operational amplifier is connected to the power supply by using the power port, the operational amplifier is grounded by using the grounding port, a first output end of the operational amplifier is connected to the first output port, and a second output end of the operational amplifier is connected to the second output port; the first input port is connected to a common-mode signal, and the common-mode signal is a first input signal of the operational amplifier; and the first switching transistor group and the second switching transistor group obtain an adjustment signal through the control port.

15. The interface chip according to claim 14, wherein the interface chip further comprises a reference input port; and the reference input port is configured to connect to a reference signal, and the reference signal is a second input signal.

Description

BRIEF DESCRIPTION OF DRAWINGS

[0046] FIG. 1 is a schematic diagram of a low voltage differential signal drive circuit according to the conventional technology;

[0047] FIG. 2 is a schematic diagram of a common-mode feedback circuit according to the conventional technology;

[0048] FIG. 3 is a schematic diagram of an operational amplifier according to an embodiment of this application;

[0049] FIG. 4 is a schematic diagram of an input adjustment unit according to an embodiment of this application;

[0050] FIG. 5 is a schematic diagram of an input switching transistor group of an operational amplifier according to an embodiment of this application;

[0051] FIG. 6 is a schematic diagram of an input switching transistor group of another operational amplifier according to an embodiment of this application;

[0052] FIG. 7A is a schematic adjustment diagram of a conventional gain adjustment method;

[0053] FIG. 7B is a schematic adjustment diagram of an operational amplifier according to an embodiment of this application;

[0054] FIG. 8 is a schematic diagram of another operational amplifier according to an embodiment of this application;

[0055] FIG. 9 is a schematic diagram of another operational amplifier according to an embodiment of this application;

[0056] FIG. 10 is a schematic diagram of a low voltage differential signal drive circuit according to an embodiment of this application;

[0057] FIG. 11 is a flowchart of a gain adjustment method for an operational amplifier according to an embodiment of this application;

[0058] FIG. 12 is a schematic diagram of an interface chip according to an embodiment of this application;

[0059] FIG. 13 is a schematic diagram of another interface chip according to an embodiment of this application;

[0060] FIG. 14 is a schematic diagram of still another interface chip according to an embodiment of this application;

[0061] FIG. 15 is a schematic diagram of yet another interface chip according to an embodiment of this application; and

[0062] FIG. 16 is a schematic diagram of an electronic device according to an embodiment of this application.

DESCRIPTION OF EMBODIMENTS

[0063] To make a person skilled in the art better understand technical solutions provided in embodiments of this application, the following first describes an application scenario of the technical solutions provided in this application.

[0064] An operational amplifier and a low voltage differential signal drive circuit that are provided in this application are applied to a data transmission system. A data type is not specifically limited in this application, and may be, for example, audio data or video data. The data transmission system may be a display system, a monitoring system, a vehicle communication system, an industrial control system, or the like.

[0065] Refer to FIG. 1. A low voltage differential signal drive circuit includes a main drive circuit 101 and a common-mode feedback circuit 102. The common-mode feedback circuit 102 is a feedback network. The common-mode feedback circuit 102 has a first input end to which a common-mode level Vcm is input and a second input end to which a reference level Vref is input. The common-mode feedback circuit 102 is configured to adjust the common-mode level Vcm with a change of the reference voltage Vref, to satisfy a multi-scenario and multi-protocol requirement.

[0066] With development of processes, a transconductance (Transconductance) of a switching transistor becomes larger, a gain of an operational amplifier becomes higher, and a requirement for stability of a closed-loop feedback loop using an operational amplifier also becomes higher. For the drive circuit of a current-mode low voltage differential signal architecture shown in FIG. 1, a gain, a zero, and an output pole of the drive circuit are complex, and the gain, the zero, and the output pole change with a change of an input common mode and an output amplitude. Therefore, an operational amplifier with a fixed gain cannot provide stable common-mode feedback in all cases. Therefore, the gain of the operational amplifier is required to be adjustable. Currently, main indicators for measuring performance of the operational amplifier with an adjustable gain include: a gain adjustment range, a gain adjustment step, influence on a zero and a pole, power consumption, and an area.

[0067] Refer to a common-mode feedback circuit shown in FIG. 2. Adc represents a gain of the circuit, W/L represents a size-to-width ratio of an input switching transistor, μ represents a carrier migration rate, Cox represents a gate oxygen capacitance, and I.sub.bias represents a tail current, Wp represents a position of an output pole, C.sub.L represents a parasitic capacitance of the switching transistor and a load capacitance of an output end, and Vdd represents a supply voltage. Therefore, the foregoing parameters satisfy the following formulas:

Adc=R.sub.L√{square root over (W/L.Math.μ.Math.C.sub.ox.Math.I.sub.bias)}  (1)

Vdc=V.sub.dd−R.sub.L/2.Math.I.sub.bias  (2)

Wp=1/(C.sub.L.Math.R.sub.L)  (3)

[0068] Refer to the foregoing formula (1). When Adc is adjusted in a current gain adjustment solution, one or more of R.sub.L, W/L, or I.sub.bias may be adjusted. However, with reference to formula (3), when R.sub.L is adjusted, the position of the output pole changes. When W/L or I.sub.bias is adjusted, a relationship between W/L or I.sub.bias and the adjusted item Adc is a square root calculation, that is, an adjustment range is non-linear. The adjustment range of Adc is limited, adjustment efficiency is low, C.sub.L is affected, and the output pole of the circuit is changed. Therefore, it is difficult to guarantee normal operating of the operational amplifier.

[0069] To resolve the foregoing problem, this application provides an operational amplifier, a drive circuit, an interface chip, an electronic device, and a gain adjustment method. A gain of an operational amplifier is linearly adjusted through a method for adjusting a state of an input switching transistor group, and then controlling proportions of two or more input signals, so that the gain can be linearly adjusted. Moreover, a direct-current operating point and an output pole of the circuit are not changed, and stability and adjustment effect are improved.

[0070] To make a person skilled in the art understand the solutions in this application more clearly, the following describes the technical solutions in embodiments of this application with reference to the accompanying drawings in embodiments of this application.

[0071] Terms such as “first” and “second” in the following description of this application are merely used for description purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating a quantity of indicated technical features.

[0072] In this application, unless otherwise explicitly specified and limited, the term “connection” should be understood in a broad sense. For example, the “connection” may be a fixed connection, a detachable connection, or an integrated connection; and may be a direct connection or an indirect connection through an intermediate medium.

[0073] FIG. 3 is a schematic diagram of an operational amplifier according to an embodiment of this application.

[0074] As shown in the figure, the operational amplifier includes a first load R1, a second load R2, an input switching transistor group 301, and a tail current source 203.

[0075] When the operational amplifier uses a symmetric design structure, parameter values of the first load R1 and the second load R2 are the same. In the following description, parameter values of R1 and R2 are both represented by R.sub.L.

[0076] The input switching transistor group 301 includes a first switching transistor group 301-1 and a second switching transistor group 301-2.

[0077] A first end of the first switching transistor group 301-1 is connected to a first output end (represented by outp in the figure) of the operational amplifier, and is connected to a power supply VDD of the operational amplifier by using the first load R1, and a second end of the first switching transistor group 301-1 is grounded by using the tail current source 203.

[0078] A first end of the second switching transistor group 301-2 is connected to a second output end (represented by outn in the figure) of the operational amplifier, and is connected to the power supply VDD by using the second load R1, and a second end of the second switching transistor group 301-2 is grounded by using the tail current source 203.

[0079] The first switching transistor group 301-1 and the second switching transistor group 301-2 include a same quantity of at least two input adjustment units, and an input end of each input adjustment unit is connected to only one input signal.

[0080] The input signal connected to each input adjustment unit in the first switching transistor group 301-1 and the second switching transistor group 301-2 is adjustable. To be specific, each input adjustment unit may be connected to different input signals.

[0081] The following specifically describes a principle of a manner in which the operational amplifier implements gain adjustment.

[0082] An example in which the first switching transistor group 301-1 and the second switching transistor group 301-2 each include eight input adjustment units and the operational amplifier supports connection of two input signals is used for description.

[0083] IN and IP respectively represent two input signals, A.sub.dc_tot represents a total gain of the input switching transistor group 301, A.sub.dc_p is an equivalent gain of the input IP, and A.sub.dc_n is an equivalent gain of the input IN.

[0084] When the first switching transistor group 301-1 has one input adjustment unit connected to IN and seven input adjustment units connected to IP, and the second switching transistor group 301-2 has seven input adjustment units connected to IN and one input adjustment unit connected to IP, the gains are as follows:

[00001]$\begin{array}{cc}{A}_{\mathrm{dc\_p}}=\frac{7-1}{7+1}.Math.A_{d{c}_{-}tot}=0.75A_{d{c}_{-}tot}& \left(4-1\right)\end{array}$$\begin{array}{cc}{A}_{d{c}_{-}n}=\frac{7-1}{7+1}.Math.A_{d{c}_{-}tot}=0.75A_{d{c}_{-}tot}& \left(4-2\right)\end{array}$

[0085] After the input signals connected to the switching transistor groups are adjusted to adjust the gains, using an example in which the gains are reduced, when the first switching transistor group 301-1 has two input adjustment units connected to IN and six input adjustment units connected to IP, and the second switching transistor group 301-2 has six input adjustment units connected to IN and two input adjustment units connected to IP, the gains are as follows:

[00002]$\begin{array}{cc}{A}_{\mathrm{dc\_p}}=\frac{6-2}{6+2}.Math.A_{d{c}_{-}tot}=0.5A_{d{c}_{-}tot}& \left(5-1\right)\end{array}$$\begin{array}{cc}{A}_{d{c}_{-}n}=\frac{6-2}{6+2}.Math.A_{d{c}_{-}tot}=0.5A_{d{c}_{-}tot}& \left(5-2\right)\end{array}$

[0086] After the input signals connected to the switching transistor groups continue to be adjusted to adjust the gains, when the first switching transistor group 301-1 has three input adjustment units connected to IN and five input adjustment units connected to IP, and the second switching transistor group 301-2 has five input adjustment units connected to IN and three input adjustment units connected to IP, the gains are as follows:

[00003]$\begin{array}{cc}{A}_{\mathrm{dc\_p}}=\frac{5-3}{5+3}.Math.A_{d{c}_{-}tot}=0.25A_{d{c}_{-}tot}& \left(6-1\right)\end{array}$$\begin{array}{cc}{A}_{d{c}_{-}n}=\frac{5-3}{5+3}.Math.A_{d{c}_{-}tot}=0.25A_{d{c}_{-}tot}& \left(6-2\right)\end{array}$

[0087] Refer to the foregoing (4-1) to (6-2) together. The range in the foregoing adjustment process is 0.25 A.sub.dc_tot, linear adjustment can be implemented, and only the type of the input signal connected to the input adjustment unit is changed in the adjustment process. The total quantity of input adjustment units does not change in the adjustment process, and the size, the load, and the tail current of the switching transistor group are not changed.

[0088] In this embodiment of this application, input adjustment units of the first switching transistor group 301-1 and the second switching transistor group 301-2 include switching transistors. Types of switching transistors are not specifically limited in this embodiment of this application. In some embodiments, the switching transistor may be an IGBT, a MOSFET, a SiC MOSFET, or the like.

[0089] In conclusion, the operational amplifier provided in this application is used to linearly adjust a gain, and a size, a load, and a tail current of the switching transistor group are not changed in the adjustment process. Therefore, a direct-current operating point and an output pole of the operational amplifier are not changed. In addition, because the size of the switching transistor group is not increased in the adjustment process, that is, an area of the switching transistor group and power consumption are not increased, gain adjustment efficiency is further improved.

[0090] The following first describes an implementation of the input adjustment unit.

[0091] FIG. 4 is a schematic diagram of an input adjustment unit according to an embodiment of this application.

[0092] As shown in the figure, the input adjustment unit 401 includes a first selector switch S and a switching transistor Q.

[0093] The first selector switch S is connected to a control end c of the switching transistor Q, a first end a of the switching transistor Q is connected to a first end of a switching transistor group in which the switching transistor Q is located, and a second end b of the switching transistor Q is connected to a second end of the switching transistor group in which the switching transistor Q is located.

[0094] The first selector switch S is configured to select an input signal to be connected to the control end.

[0095] For example, the switching transistor Q is an N-channel metal oxide semiconductor (N-channel metal oxide semiconductor) field effect transistor. For the switching transistor Q, the first end is a drain (Drain), the second end is a source (Source), and the control end is a gate (Gate).

[0096] In some embodiments, the first selector switch S selects a to-be-connected input signal based on an adjustment signal SEL. Using an example in which the input signal includes the following two signals: a first input signal and a second input signal, the first input signal is represented by IN, and the second input signal is represented by IP. In this case, the adjustment signal SEL may be a level signal. The first selector switch S selects to connect to the first input signal IN when the adjustment signal SEL is a first level or selects to connect to the second input signal IP when the adjustment signal is a second level. In a possible implementation, the first level is a high level, and the second level is a low level. In another possible implementation, the first level is a low level, and the second level is a high level.

[0097] Based on the principle of the input adjustment unit shown in FIG. 4, a person skilled in the art may replace the selector switch S in another possible implementation, to select one of the two inputs based on the adjustment signal and output the selected input to the switching transistor.

[0098] The following describes an operating principle of the operational amplifier with reference to a specific implementation.

[0099] First, an implementation of adjusting a gain in a symmetric adjustment manner is described.

[0100] FIG. 5 is a schematic diagram of an input switching transistor group of an operational amplifier according to an embodiment of this application.

[0101] As shown in the figure, a first switching transistor group 301-1 and a second switching transistor group 301-2 each include (M+N) input adjustment units 401.

[0102] Still using an example in which the input signal includes the following two signals: a first input signal and a second input signal, the first input signal is represented by IN, and the second input signal is represented by IP.

[0103] When the symmetric adjustment manner is used, in the first switching transistor group 301-1, a first quantity of input adjustment units is connected to the first input signal, and a second quantity of input adjustment units is connected to the second input signal.

[0104] In the second switching transistor group 301-2, the second quantity of input adjustment units is connected to the first input signal, and the first quantity of input adjustment units is connected to the second input signal; and

[0105] the first quantity is not equal to the second quantity. As shown in the figure, the first quantity is M, the second quantity is N, and both M and N are integers greater than or equal to 0.

[0106] A.sub.dc_tot represents a total gain of the input switching transistor group 301, A.sub.dc_p is an equivalent gain of the input IP, and A.sub.dc_n is an equivalent gain of the input IN, R.sub.L represents a load resistance, I.sub.bias represents a tail current, W/L represents a ratio of a total width of the input switching transistor group to a channel length, μ represents a carrier migration rate, and Cox represents a gate oxygen capacitance. Therefore, a gain of the operational amplifier can be linearly adjusted by symmetrically adjusting proportions of the input IP and the input IN in the first switching transistor group 301-1 and the second switching transistor group 301-2, and an adjustment step Adc step satisfies the following formula:

A.sub.dc_step=2.Math.A.sub.dc_tot/(M+N)  (7)

[0107] The gains of the two inputs are as follows:

[00004]$\begin{array}{cc}{A}_{\mathrm{dc\_p}}=\frac{N-M}{M+N}.Math.A_{d{c}_{-}tot}& \left(8-1\right)\end{array}$$\begin{array}{cc}{A}_{d{c}_{-}n}=\frac{N-M}{M+N}.Math.A_{d{c}_{-}tot}& \left(8-2\right)\end{array}$

[0108] A.sub.dc_tot satisfies the following formula:

A.sub.dc_tot=R.sub.L√{square root over (W/L.Math.μ.Math.C.sub.ox.Math.I.sub.bias)}  (9)

[0109] In the symmetric adjustment manner, polarity reversal of the operational amplifier may be implemented by adjusting the proportions of the input IP and the input IN. To be specific, when N>M, the input signal IP dominates in 301-1 and the input signal IN dominates in 301-2. In this case, an output gain of the operational amplifier is of a first polarity. Alternatively, when N<M, the input signal IN dominates in 301-1 and the input signal IP dominates in 301-2. In this case, an output gain of the operational amplifier is of a second polarity.

[0110] In some embodiments, positiveness and negativeness of the gain respectively correspond to the first polarity and the second polarity. When the gain is positive, that is, when the gain is of the first polarity, it indicates that the operational amplifier is configured to amplify the input signal. When the gain is negative, that is, when the gain is of the second polarity, it indicates that the operational amplifier is configured to scale down the input signal. It should be understood that a polarity of the gain when being negative may alternatively be referred to as the first polarity, and a polarity of the gain when being positive may be referred to as the second polarity.

[0111] In the adjustment process, N is required to be not equal to M. Otherwise, the input of the operational amplifier is 0.

[0112] In conclusion, the operational amplifier provided in this application is used to linearly adjust a gain in the symmetric adjustment manner, and a size, a load, and a tail current of the switching transistor group are not changed in the adjustment process. Therefore, a direct-current operating point and an output pole of the operational amplifier are not changed. Because a size of the switching transistor group is not increased in the adjustment process, that is, an area of the switching transistor group and power consumption are not increased, gain adjustment efficiency is further improved.

[0113] The following describes an implementation in which an operational amplifier uses asymmetric adjustment.

[0114] FIG. 6 is a schematic diagram of an input switching transistor group of another operational amplifier according to an embodiment of this application.

[0115] As shown in the figure, a first switching transistor group 301-1 and a second switching transistor group 301-2 each include (M+N) input adjustment units 401.

[0116] Still using an example in which the input signal includes the following two signals: a first input signal and a second input signal, the first input signal is represented by IN, and the second input signal is represented by IP.

[0117] When the asymmetric adjustment manner is used, in the first switching transistor group 301-1, a first quantity of input adjustment units is connected to the first input signal, and a second quantity of input adjustment units is connected to the second input signal.

[0118] A third quantity of input adjustment units in the second switching transistor group 301-2 is connected to the first input signal.

[0119] As shown in the figure, the first quantity is M, the second quantity is N, M is an integer greater than or equal to 0, N is an integer greater than 0, and the third quantity is equal to a sum of the first quantity and the second quantity.

[0120] A.sub.dc_tot represents a total gain of the input switching transistor group 301, A.sub.dc_p is an equivalent gain of the input IP, and Aden is an equivalent gain of the input IN, R.sub.L represents a load resistance, I.sub.bias represents a tail current, W/L represents a ratio of a total width of the input switching transistor group to a channel length, μ represents a carrier migration rate, and Cox represents a gate oxygen capacitance. Therefore, a gain of the operational amplifier is linearly adjusted by symmetrically adjusting proportions of the input IP and the input IN in the first switching transistor group 301-1 and the second switching transistor group 301-2, and an adjustment step Adc step satisfies the following formula:

A.sub.dc_step=A.sub.dc_tot/(M+N)  (10)

[0121] By comparing formula (10) with formula (7), it can be found that in the asymmetric adjustment manner, the adjustment step is smaller and the adjustment precision is higher when the quantity of input adjustment units is the same than those in the symmetric adjustment manner.

[0122] The gains of the two inputs are as follows:

[00005]$\begin{array}{cc}{A}_{\mathrm{dc\_p}}=\frac{N}{M+N}.Math.A_{d{c}_{-}tot}& \left(11-1\right)\end{array}$$\begin{array}{cc}{A}_{d{c}_{-}n}=\frac{N}{M+N}.Math.A_{d{c}_{-}tot}& \left(11-2\right)\end{array}$

[0123] Ade tot satisfies formula (9), and N is required to be a positive integer in the foregoing adjustment process.

[0124] For asymmetric adjustment, when polarity reversal is not performed, the first selector switch selects to connect to the first input signal when the adjustment signal is a first level or selects to connect to the second input signal when the adjustment signal is a second level.

[0125] When polarity reversal is performed, the first selector switch of the first switching transistor group 301-1 selects to connect to the first input signal when the adjustment signal is a first level or selects to connect to the second input signal when the adjustment signal is a second level; and the first selector switch of the second switching transistor group 301-1 selects to connect to the first input signal when the adjustment signal is a second level or selects to connect to the second input signal when the adjustment signal is a first level. In this case, gains of the two inputs are as follows:

[00006]$\begin{array}{cc}{A}_{\mathrm{dc\_p}}=\frac{M}{M+N}.Math.A_{d{c}_{-}tot}& \left(12-1\right)\end{array}$$\begin{array}{cc}{A}_{d{c}_{-}n}=\frac{M}{M+N}.Math.A_{d{c}_{-}tot}& \left(12-2\right)\end{array}$

[0126] In conclusion, the operational amplifier provided in this application is used to linearly adjust a gain in the asymmetric adjustment manner, and a size, a load, and a tail current of the switching transistor group are not changed in the adjustment process. Therefore, a direct-current operating point and an output pole of the operational amplifier are not changed. Because a size of the switching transistor group is not increased in the adjustment process, that is, an area of the switching transistor group and power consumption are not increased, gain adjustment efficiency is further improved.

[0127] The following describes technical effects of the solutions of this application in detail with reference to accompanying drawings.

[0128] Refer to FIG. 7A and FIG. 7B together. FIG. 7A is a schematic adjustment diagram of a conventional gain adjustment method, and FIG. 7B is a schematic adjustment diagram of an operational amplifier according to an embodiment of this application.

[0129] It can be learned from formula (1) that a gain A.sub.dc_tot in the conventional method is directly proportional to (W*I.sub.bias).sup.1/2. In the description of this application, one switching transistor in the conventional technology is equivalent to a plurality of switching transistors, to better represent a change of W of the switching transistor in an adjustment process.

[0130] In the conventional method, when a gain is halved through adjustment, in a possible implementation, a solution A is used, a width-to-length ratio of an input transistor needs to be reduced from 4 to 1, an adjustment step of this manner is non-linear, an exponential change relationship is present, a size of the input transistor is greatly changed, and adjustment efficiency is low; or in another possible implementation, a solution B is used, a width-to-length ratio of an input transistor is reduced from 4 to 2, and a tail current is reduced by half. In this case, it can be learned from formula (2) that a direct-current operating point changes, and consequently normal operating of the operational amplifier is affected.

[0131] However, when the solution of this application is applied, in a possible implementation, a symmetric adjustment manner shown in C is used. Using an example in which in an initial state, four input adjustment units in a first switching transistor group 301-1 are connected to IP and four input adjustment units in a second switching transistor group 301-2 are connected to IN, when the gain needs to be halved through adjustment, an input signal of one input adjustment unit in the first switching transistor group 301-1 is switched from IP to IN, and an input signal of one input adjustment unit in the second switching transistor group 301-2 is symmetrically switched from IN to IP, to complete adjustment.

[0132] In another possible implementation, an asymmetric adjustment manner shown in D is used, input signals of a second switching transistor group 301-2 are kept unchanged, and input signals of two input adjustment units in a first switching transistor group 301-1 are switched from IP to IN, to complete adjustment.

[0133] The above two methods achieve gain halving, but do not change the size of the input transistor, the load, the tail current, positions of the operating point, the zero point and the pole of the operational amplifier, the adjustment solutions are simple, the area of the input transistor and the overhead of power consumption are not increased, and the gain adjustment efficiency is high.

[0134] In addition, the foregoing adjustment implements gain adjustment. Alternatively, a similar manner may be used, a load may be adjusted to control proportions of two or more input signals, to perform linear adjustment on parameters such as an equivalent transconductance, an equivalent current, and an equivalent impedance. Detailed descriptions are made below with reference to accompanying drawings.

[0135] FIG. 8A is a schematic diagram of another operational amplifier according to an embodiment of this application.

[0136] As shown in the figure, for the operational amplifier, a first load is a first load group 302-1 and a second load is a second load group 302-2.

[0137] The first load group 302-1 and the second load group 302-2 include a same quantity of at least two load adjustment units 402.

[0138] The first load group 302-1 and the second load group 302-2 are configured to adjust quantities of respective load adjustment units connected to input signals.

[0139] In this embodiment, two input signals are respectively represented by X and T.

[0140] In this case, parameters such as an equivalent transconductance, an equivalent current, and an equivalent impedance of the operational amplifier can be linearly adjusted by adjusting the input signals connected to the load adjustment units. A specific implementation and an adjustment principle of the load adjustment unit are similar to those described in the foregoing embodiments, and details are not described herein again in this application.

[0141] In a typical application scenario, the operational amplifier provided in this embodiment of this application is applied to feedback adjustment on a common-mode signal. In this case, the input signal includes a common-mode signal and a reference signal.

[0142] In some embodiments, the common-mode signal is generated by a low voltage differential signal generation circuit, and the reference signal may be input by an external circuit, or may be obtained through voltage division of a power supply. An example in which the first input signal is the reference signal is used below for description.

[0143] FIG. 9 is a schematic diagram of another operational amplifier according to an embodiment of this application.

[0144] In this case, the operational amplifier further includes a voltage divider circuit 303, an input end of the voltage divider circuit is connected to a power supply VDD of the operational amplifier, and an output end of the voltage divider circuit 303 is configured to output a reference signal Vref.

[0145] The voltage divider circuit 303 is configured to convert a voltage provided by the power supply VDD into the reference signal Vref.

[0146] Based on the operational amplifier provided in the foregoing embodiments, an embodiment of this application further provides a low voltage differential signal drive circuit which is specifically described below with reference to an accompanying drawing.

[0147] FIG. 10 is a schematic diagram of a low voltage differential signal drive circuit according to an embodiment of this application.

[0148] As shown in the figure, the low voltage differential signal drive circuit includes the operational amplifier provided in the foregoing embodiments, and further includes a low voltage differential signal generation circuit 101.

[0149] An input end of the low voltage differential signal generation circuit 101 is connected to a power supply VDD, and a feedback signal end of the low voltage differential signal generation circuit is connected to a first output end outp of the operational amplifier or a second output end outn of the operational amplifier, and is connected to, for example, the first output end outp in the figure.

[0150] A common-mode signal Vcm output by the low voltage differential signal generation circuit 101 is a first input signal of the operational amplifier, and is, for example, the input signal IP in the foregoing embodiments.

[0151] Output ends outp1 and outn1 of the low voltage differential signal generation circuit 101 are configured to output low voltage differential signals.

[0152] A reference signal Vref is a second input signal of the operational amplifier, and is, for example, the input signal IN in the foregoing embodiments. The reference signal may be input by an external circuit, or may be obtained through voltage division of the power supply VDD.

[0153] In FIG. 10, an example in which the reference signal is obtained through voltage division of the power supply VDD is used. In this case, the operational amplifier further includes a voltage divider circuit 303, an input end of the voltage divider circuit 303 is connected to the power supply VDD, and an output end of the voltage divider circuit is configured to output the reference signal Vref.

[0154] The voltage divider circuit 303 is configured to convert a voltage provided by the power supply VDD into the reference signal Vref.

[0155] For a principle of the low voltage differential signal generation circuit 101, refer to the description corresponding to FIG. 1. The principle is a mature technology in the art, and details are not described herein again in this embodiment of this application. For an implementation and an operating principle of the operational amplifier, refer to the related description in the foregoing embodiments, and details are not described herein again.

[0156] In conclusion, the low voltage differential signal generation circuit adjusts, by using the operational amplifier, a common-mode level Vcm with a change of a reference voltage Vref, to satisfy a multi-scenario and multi-protocol requirement. The operational amplifier adjusts types of the input signals connected to the input adjustment units in the first switching transistor group and the second switching transistor group, to adjust proportions of the input signals of the operational amplifier, and further adjust a gain of the operational amplifier. An input end of each input adjustment unit is connected to only one input signal, and a quantity of adjustment units does not change in an adjustment process. Therefore, a gain can be linearly adjusted, and a size, a load, a tail current, a direct-current operating point, and an output pole of a switching transistor group are not changed in an adjustment process. In addition, because the size of the switching transistor group is not increased in the adjustment process, that is, an area of the switching transistor group and power consumption are not increased, gain adjustment efficiency is further improved.

[0157] Based on the operational amplifier provided in the foregoing embodiments, an embodiment of this application further provides a gain adjustment method for an operational amplifier. The method is specifically described below with reference to an accompanying drawing.

[0158] FIG. 11 is a flowchart of a gain adjustment method for an operational amplifier according to an embodiment of this application.

[0159] The method is applied to the operational amplifier provided in the foregoing embodiments. For a specific implementation of the operational amplifier, refer to the related description in the foregoing embodiments. Details are not described herein again.

[0160] The method includes the following steps:

[0161] S1101: Determine a target gain of an operational amplifier.

[0162] S1102: Adjust, based on the target gain, a type of an input signal connected to each input adjustment unit.

[0163] In a possible implementation, when the symmetric adjustment manner is used, in a first switching transistor group, a first quantity of input adjustment units is connected to a first input signal, and a second quantity of input adjustment units is connected to a second input signal; and in the second switching transistor group, the second quantity of input adjustment units is connected to the first input signal, and the first quantity of input adjustment units is connected to the second input signal; and

[0164] the first quantity is not equal to the second quantity. The first quantity is M, the second quantity is N, and both M and N are integers greater than or equal to 0. After current values of M and N are determined based on the target gain, corresponding adjustment is performed on the input adjustment units in the first switching transistor group and the second switching transistor group through a corresponding adjustment signal, to linearly adjust a gain of the operational amplifier.

[0165] In another possible implementation, when the asymmetric adjustment manner is used, in a first switching transistor group, a first quantity of input adjustment units is connected to a first input signal, and a second quantity of input adjustment units is connected to a second input signal; and A third quantity of input adjustment units in the second switching transistor group 301-2 is connected to the first input signal.

[0166] The first quantity is M, the second quantity is N, M is an integer greater than or equal to 0, N is an integer greater than 0, and the third quantity is equal to a sum of the first quantity and the second quantity. After current values of M and N are determined based on the target gain, corresponding adjustment is performed on the input adjustment units in the first switching transistor group and the second switching transistor group through a corresponding adjustment signal, to linearly adjust a gain of the operational amplifier.

[0167] In conclusion, the method provided in this embodiment of this application is used to linearly adjust the gain of the operational amplifier according to a method for adjusting a state of an input switching transistor, and then controlling proportions of two or more input signals, so that the gain can be linearly adjusted. Moreover, a direct-current operating point and an output pole of the circuit are not changed, and stability and adjustment effect are improved.

[0168] Based on the operational amplifier provided in the foregoing embodiments, an embodiment of this application further provides an interface chip integrated with the operational amplifier provided in the foregoing embodiments. The interface chip is specifically described below with reference to an accompanying drawing.

[0169] FIG. 12 is a schematic diagram of an interface chip according to an embodiment of this application.

[0170] The interface chip 1201 shown in the figure includes the operational amplifier provided in the foregoing embodiments. Package pin ports of the interface chip include: a power port VDD, a first output port OUT1, a second output port OUT2, a grounding port GND, a control port Vc, and a first input port INPUT.

[0171] The operational amplifier is connected to the power supply by using the power port, the operational amplifier is grounded by using the grounding port, a first output end of the operational amplifier is connected to the first output port, and a second output end of the operational amplifier is connected to the second output port. In practical application, the first output port OUT1 or the second output port OUT2 is configured to output a feedback signal V_fb. In this embodiment of this application, an example in which OUT1 outputs the feedback signal V_fb is used.

[0172] The first input port is connected to a common-mode signal Vcm, and the common-mode signal is a first input signal.

[0173] The first switching transistor group and the second switching transistor group obtain an adjustment signal SEL through the control port Vc. Each input adjustment unit adjusts, based on the adjustment signal SEL, a type of an input signal connected to the input adjustment unit.

[0174] In this case, the operational amplifier is integrated into the interface chip 1201, and is used as a peripheral circuit of a low voltage differential signal generation circuit 101. The low voltage differential signal generation circuit 101 adjusts, by using the interface chip 1201, a common-mode level Vcm with a change of a reference voltage Vref, to satisfy a multi-scenario and multi-protocol requirement.

[0175] The interface chip 1201 is further integrated with a voltage divider circuit, an input end of the voltage divider circuit is connected to the power port, an output end of the voltage divider circuit is configured to output the reference signal, and the reference signal is the second input signal. The voltage divider circuit is configured to convert a voltage provided by the power supply into the reference signal to serve as an input signal generated inside the interface chip 1201.

[0176] FIG. 13 is a schematic diagram of another interface chip according to an embodiment of this application.

[0177] Different from 1201, the interface chip 1301 shown in FIG. 13 further includes a reference input port VF.

[0178] The reference input port VF is configured to connect to a reference signal Vref, and the reference signal is a second input signal. To be specific, the reference signal Vref is not generated inside the interface chip 1301, but is input through an external circuit.

[0179] In conclusion, the interface chip provided in this embodiment of this application is used to linearly adjust a gain, and a size, a load, and a tail current of the switching transistor group are not changed in the adjustment process. Therefore, a direct-current operating point and an output pole of the operational amplifier are not changed. Because a size of the switching transistor group is not increased in the adjustment process, that is, an area of the switching transistor group and power consumption are not increased, gain adjustment efficiency is further improved.

[0180] Based on the operational amplifier provided in the foregoing embodiments, an embodiment of this application further provides an interface chip integrated with the low voltage differential signal drive circuit provided in the foregoing embodiments. The interface chip is specifically described below with reference to an accompanying drawing.

[0181] FIG. 14 is a schematic diagram of still another interface chip according to an embodiment of this application.

[0182] The interface chip 1401 shown in the figure includes the operational amplifier and the low voltage differential signal generation circuit that are provided in the foregoing embodiments. Package pin ports of the interface chip include: a power port VDD, a first control port VC1, a second control port VC2, a third control port Vc, a grounding port GND, and output ports OUT1 and OUT2.

[0183] The low voltage differential signal generation circuit and the operational amplifier are connected to the power supply by using the power port, and are grounded by using the grounding port.

[0184] For specific implementations and operating principles of the low voltage differential signal generation circuit and the operational amplifier, refer to the foregoing description, and details are not described herein again.

[0185] The low voltage differential signal generation circuit obtains a control signal from the first control port VC1 and the second control port VC2, generates a low voltage differential signal based on the control signal, and outputs the low voltage differential signal through the output port.

[0186] The first switching transistor group and the second switching transistor group obtain an adjustment signal SEL through the third control port Vc, and adjust, based on the adjustment signal, quantities of respective input adjustment units connected to input signals.

[0187] The interface chip 1401 is further integrated with a voltage divider circuit, an input end of the voltage divider circuit is connected to the power port, an output end of the voltage divider circuit is configured to output the reference signal, and the reference signal is the second input signal. The voltage divider circuit is configured to convert a voltage provided by the power supply into the reference signal to serve as an input signal generated inside the interface chip 1401.

[0188] In some embodiments, only one of the foregoing output ports OUT1 and OUT2 may alternatively be disposed.

[0189] FIG. 15 is a schematic diagram of yet another interface chip according to an embodiment of this application.

[0190] Different from 1401, the interface chip 1501 shown in FIG. 15 further includes a reference input port VF.

[0191] The reference input port VF is configured to connect to a reference signal Vref, and the reference signal is a second input signal. To be specific, the reference signal Vref is not generated inside the interface chip 1301, but is input through an external circuit.

[0192] In conclusion, through the interface chip provided in this embodiment of this application, the low voltage differential signal generation circuit and the operational amplifier are integrated together, a gain can be linearly adjusted, and a size, a load, and a tail current of the switching transistor group are not changed in the adjustment process. Therefore, a direct-current operating point and an output pole of the operational amplifier are not changed. Because a size of the switching transistor group is not increased in the adjustment process, that is, an area of the switching transistor group and power consumption are not increased, gain adjustment efficiency is further improved.

[0193] Based on the operational amplifier and the low voltage differential signal drive circuit that are provided in the foregoing embodiments, an embodiment of this application further provides an electronic device which is specifically described below with reference to an accompanying drawing.

[0194] FIG. 16 is a schematic diagram of an electronic device according to an embodiment of this application.

[0195] The electronic device 1600 shown in the figure includes the operational amplifier and the low voltage differential signal drive circuit 101 that are provided in the foregoing embodiments. For a specific implementation and an operating principle of the operational amplifier, refer to related descriptions in the foregoing embodiments. Details are not described herein again in this embodiment of this application.

[0196] The electronic device 1600 further includes a controller (not shown in the figure), and the controller may be an ASIC, a PLC, a DSP, or a combination thereof. The PLD may be a CPLD, an FPGA, a GAL, or any combination thereof. This is not specifically limited in this embodiment of this application.

[0197] The controller is configured to send a control signal to two pairs of switching transistors Pren1 and Prep1 and Pren2 and Prep2 of the low voltage differential signal drive circuit 101, so that the low voltage differential signal drive circuit 101 generates and outputs a low voltage differential signal. The controller is further configured to send an adjustment signal to the first selector switch based on the target gain, so that the first switching transistor group 301-1 and the second switching transistor group 301-2 adjust quantities of respective input adjustment units connected to input signals.

[0198] A type of the electronic device is not specifically limited in this embodiment of this application. For example, the electronic device may be a display device, a monitoring device, a vehicle communication device, an industrial control device, or the like.

[0199] In conclusion, the operational amplifier of the electronic device adjusts the input signals connected to the input adjustment units in the first switching transistor group and the second switching transistor group, to adjust proportions of the input signals of the operational amplifier, and further adjust a gain of the operational amplifier. An input end of each input adjustment unit is connected to only one input signal, and a quantity of adjustment units does not change in an adjustment process. Therefore, a gain can be linearly adjusted, and a size, a load, a tail current, a direct-current operating point, and an output pole of a switching transistor group are not changed in an adjustment process. In addition, because the size of the switching transistor group is not increased in the adjustment process, that is, an area of the switching transistor group and power consumption are not increased, gain adjustment efficiency is further improved.

[0200] Based on the foregoing electronic device, an embodiment of this application further provides a gain adjustment method for an operational amplifier. The method is specifically described below.

[0201] FIG. 17 is a flowchart of a gain adjustment method for an operational amplifier according to an embodiment of this application.

[0202] The method may be implemented by a controller of an electronic device, and specifically includes the following steps:

[0203] S1701: Determine a target parameter value.

[0204] S1702: Determine an adjustment signal based on the target parameter value, and send the adjustment signal to the first switching transistor group and the second switching transistor group, where the adjustment signal is for indicating the first switching transistor group and the second switching transistor group to adjust quantities of respective input adjustment units connected to input signals.

[0205] The target parameter value may be a gain of the operational amplifier.

[0206] It should be understood that in this application, “at least one (item)” refers to one or more, and “a plurality of” refers to two or more. “and/or” is used to describe an association relationship between associated objects, and indicates that three relationships may exist. For example, “A and/or B” may indicate that only A exists, only B exists, and both A and B exist, where A and B may be singular or plural. The character “I” generally indicates that the associated objects are in an OR relationship. “At least one of the following” or a similar expression thereof refers to any combination of these items, including any combination of a single item or a plural item. For example, at least one ( ) of a, b, or c may represent: a, b, c, “a and b”, “a and c”, “b and c”, or “a and b and c”, where a and b, c can be a single or multiple.

[0207] The foregoing embodiments are merely used to describe the technical solutions of this application, but not to limit the technical solutions. Although this application is described in detail with reference to the foregoing embodiments, a person of ordinary skill in the art should understand that he or she may still make modifications to the technical solutions recorded in the foregoing embodiments, or make equivalent replacements to some technical features thereof. However, these modifications or replacements do not deviate from the spirit and scope of the technical solutions in embodiments of this application.