CHIP ARRANGEMENT AND METHOD FOR FORMING A SINTERED CONTACT CONNECTION

Abstract

A method for forming a contact connection between a chip-and a conductor material formed on a non-conductive substrate, the chip being arranged on the substrate or on another conductor material track, a sinter paste consisting of at least 40% silver or copper being applied to respective chip contact surfaces of the chip and the conductor material track, a contact conductor being immersed in the sinter paste on the chip contact surface and in the sinter paste on the conductor material track, and the contact connection being formed by sintering the sinter paste by means of laser energy.

Claims

1. A method for forming a contact connection between a chip and a conductor material track, the conductor material track being formed on a non-conductive substrate, the chip being arranged on the substrate or on another conductor material track, wherein a sinter paste consisting of at least 40% silver or copper is applied to respective chip contact surfaces of the chip and the conductor material track, a contact conductor being immersed in the sinter paste on the chip contact surface and in the sinter paste on the conductor material track, and the contact connection being formed by sintering the sinter paste by means of laser energy.

2. The method according to claim 1, wherein a sinter paste comprising silver or copper nanoparticles is used as the sinter paste.

3. The method according to claim 1, wherein a sinter paste comprising an alcohol solution, a glycol solution or epoxy resin is used as the sinter paste.

4. The method according to claim 1, wherein the sinter paste is applied with a layer thickness of 80 μm to 700 μm.

5. The method according to claim 1, wherein a stranded wire or a wire or a flat wire is used as a contact conductor.

6. The method according to claim 1, wherein laser energy of 10 mJ to 40 mJ is applied for sintering the sinter paste by means of laser energy.

7. The method according to claim 1, wherein a laser is operated with a pulse duration in the range of 1 ms to 4 ms for sintering the sinter paste by means of laser energy.

8. The method according to claim 1, wherein the solvent contained in the sinter paste is at least partially vaporized by heating in an oven.

9. The method according to claim 1, wherein the sinter paste is sintered prior to complete vaporization of the solvent.

10. A chip arrangement comprising a chip, a non-conductive substrate having a conductor material track formed thereon, and a contact conductor, the chip having been arranged on the substrate or on a conductor material track, wherein a sinter paste consisting of at least 40% silver or copper has been applied to respective chip contact surfaces of the chip and the conductor material track, the contact conductor having been immersed in the sinter paste on the chip contact surface and in the sinter paste on the conductor material track, a solvent contained in the sinter paste having been vaporized by heating, a contact connection having been formed by sintering the sinter paste by means of laser energy.

11. The chip arrangement according to claim 10, wherein the substrate is made of silicon or glass or a thermoplastic material.

12. The chip arrangement according to claim 10, wherein the sinter paste comprises silver or copper nanoparticles.

13. The chip arrangement according to claim 10, wherein the contact conductor is a stranded wire or a wire or a flat wire.

14. The chip arrangement according to claim 10, wherein the contact conductor has a width between 10 μm and 350 μm.

15. The chip arrangement according to claim 10, wherein the sinter paste covers, preferably fully encloses, the section of the contact conductor immersed in the sinter paste.

16. The method according to claim 1, wherein the chip is a power transistor.

17. The method according to claim 1, wherein a flat litz wire, is used as a contact conductor.

18. The method according to claim 1, wherein laser energy of 15 mJ to 30 mJ is applied for sintering the sinter paste.

19. The chip arrangement according to claim 10, wherein the substrate is made of polyethylene naphthalate.

20. The chip arrangement according to claim 10, wherein the sinter paste fully encloses the section of the contact conductor immersed in the sinter paste.

Description

[0043] Embodiments of the disclosure are schematically illustrated in the drawings and will be explained as examples below.

[0044] In the drawing:

[0045] FIG. 1 shows a schematic sectional view of a first embodiment of a chip arrangement during a method step;

[0046] FIG. 2 shows a schematic sectional view of the chip arrangement of FIG. 1 after completion of a contact connection;

[0047] FIG. 3 shows a schematic sectional view of a second embodiment of a chip arrangement; and

[0048] FIG. 4 shows a schematic sectional view of a third embodiment of a chip arrangement.

[0049] FIG. 1 shows a chip arrangement 10 in a schematic sectional view during the production of a contact connection 11. Chip arrangement 10 comprises a non-conductive substrate 12, on whose surface 13 a plurality of different conductor material tracks 14 and 15 are formed. Conductor material tracks 14 and 15 are separated from each other via an isolating gap 16 and are thus electrically isolated from each other. A contact metallization 17 made of silver or a silver alloy is formed on or applied to each of conductor material tracks 14 and 15. Alternatively, contact metallization 17 can also be made of nickel, copper, gold, palladium, aluminum or another alloy of one of said metals. A chip 18, which is made of a semiconductor material, is formed on conductor material track 15. A contact metallization 23 made of silver or a silver alloy is applied to a rear side 19 of chip 18 facing away from conductor material track 15, and contact bumps 21 are applied to a front side 20 of chip 18 facing toward conductor material track 15. Contact bumps 21 connect chip 18 to conductor material track 15. Accordingly, a rear chip contact surface 25 and a front chip contact surface 26 are formed on chip 18. Chip contact surface 26 of chip 18 is contacted, that is electrically connected, with a conductor surface 27 of conductor material track 15. A defined amount of sinter paste 29 has been applied to each of a conductor surface 28 of conductor material track 14 and to chip contact surface 25 of chip 18. A contact conductor 30 is realized as a flat litz wire 31 made of copper and is immersed in sinter paste 29 with each of its ends 32 and 33, sinter paste 29 substantially surrounding ends 32 and 33.

[0050] As can be taken from FIG. 2, sinter paste 29 was sintered after the solvent contained therein had largely vaporized. Sintering took place in that laser energy was introduced to sinter paste 29 and to each of ends 32 and 33. In this way, a first contact 34 of contact connection 11 was formed with sinter paste 29 and end 32 on conductor surface 28 and a second contact 35 of contact connection 11 was formed with sinter paste 29 and end 33 on chip contact surface 25. The metallic particles (not visible) of sinter paste 29 penetrated ends 32 and 33 and were sintered or partially melted together by the sintering, a particularly tight connection having been formed with filaments (not visible) of flat litz wire 31 and conductor surface 28 and chip contact surface 25, respectively. Thus, the sintered sinter paste 29 is solidified in contact areas 36 and 37.

[0051] FIG. 3 shows a second embodiment of a chip arrangement 38, which differs from the chip arrangement shown in FIG. 2 in that it comprises a flat litz wire 39 that was severed only after sintering of sinter paste 29. An end 40 of flat litz wire 39 thus protrudes from a contact area 41, a section 42 of flat litz wire 39 serving to form a contact 43 with chip 18.

[0052] FIG. 4 shows a third embodiment of a chip arrangement 44, which differs from the chip arrangement shown in FIG. 2 in that it comprises conductor material tracks 45 and 46, between which a chip 47 is arranged. Chip 47 forms two front chip contact surfaces 48 and 49 on a front side 50 of chip 47, a rear side 51 of chip 47 being arranged directly on a substrate 52. Each of chip contact surfaces 48 and 49 is connected to conductor surfaces 57 and 58 of conductor material tracks 45 and 46, respectively, via contact conductors 53 and 54, which are realized as flat litz wires 55 and 56, respectively.