CHIP STATE MONITORING CIRCUIT BASED ON SELF-BALANCING DIFFERENTIAL SIGNAL INTEGRATION AND AMPLIFICATION CIRCUIT

Abstract

A chip state monitoring circuit based on a self-balancing differential signal integration and amplification circuit is provided. The chip state monitoring circuit is built in a chip, and can sense a state signal of the chip and transmit the state signal to a chip configuration circuit after performing amplification and analog-to-digital conversion, such that the chip configuration circuit can monitor a state and provide a timely feedback or response, thereby improving reliability and a service life of the chip. The chip state monitoring circuit uses a brand new self-balancing differential signal integration and amplification circuit. With a built-in positive coefficient integration network and negative coefficient balancing network, the self-balancing differential signal integration and amplification circuit can perform amplification by required times to enter a self-balancing stable state, thereby achieving fixed-multiple amplification without timed reading. The control method is simple and flexible.

Claims

1. A chip state monitoring circuit based on a self-balancing differential signal integration and amplification circuit, comprising a state sensing circuit, a self-balancing differential signal integration and amplification circuit, and an analog-to-digital converter, wherein the state sensing circuit, a self-balancing differential signal integration and amplification circuit, and an analog-to-digital converter are sequentially connected; the analog-to-digital converter is connected to a chip configuration circuit inside a chip, and the state sensing circuit is disposed at a to-be-detected point inside the chip to sense a differential-form state signal of the chip; the self-balancing differential signal integration and amplification circuit comprises a fully differential operational amplifier, a positive coefficient integration network, and a negative coefficient balancing network, wherein both the positive coefficient integration network and the negative coefficient balancing network are connected between an input terminal and an output terminal of the fully differential operational amplifier; the fully differential operational amplifier achieves a signal amplification function for the differential-form state signal under an action of the positive coefficient integration network, and performs reverse adjustment on signal amplification under an action of the negative coefficient balancing network; a reverse adjustment function achieved by the negative coefficient balancing network is gradually enhanced until the self-balancing differential signal integration and amplification circuit achieves self balancing, to stabilize an output signal of the self-balancing differential signal integration and amplification circuit to a state signal amplified by K times; and the state signal amplified by the K times is output to the chip configuration circuit after undergoing analog-to-digital conversion by the analog-to-digital converter.

2. The chip state monitoring circuit according to claim 1, wherein the self-balancing differential signal integration and amplification circuit further comprises a sampling network for sampling a charge of a state signal; before the self-balancing differential signal integration and amplification circuit achieves self balancing, a first part of the charge sampled by the sampling network is transferred to the positive coefficient integration network to achieve the signal amplification function, and a second part of the charge sampled by the sampling network is transferred to the negative coefficient balancing network to achieve the reverse adjustment function of the signal amplification, and the output signal of the self-balancing differential signal integration and amplification circuit gradually increases; and as an output signal of the fully differential operational amplifier increases, the second part of the charge transferred by the sampling network to the negative coefficient balancing network gradually increases, thereby gradually enhancing the reverse adjustment function achieved by the negative coefficient balancing network; and after the self-balancing differential signal integration and amplification circuit achieves self balancing, the charge sampled by the sampling network is completely transferred to the negative coefficient balancing network, and the output signal of the self-balancing differential signal integration and amplification circuit is stabilized to the state signal amplified by the K times.

3. The chip state monitoring circuit according to claim 2, wherein the positive coefficient integration network is built based on an integration capacitor C.sub.fp, the negative coefficient balancing network is built based on a balancing capacitor C.sub.fn, the sampling network is built based on a sampling capacitor C.sub.s, and an amplification factor K achieved for the state signal by the self-balancing differential signal integration and amplification circuit in a stable state is determined by capacitance values of the sampling capacitor C.sub.s and the balancing capacitor C.sub.fn.

4. The chip state monitoring circuit according to claim 3, wherein the amplification factor achieved for the state signal by the self-balancing differential signal integration and amplification circuit in the stable state is calculated according to a following formula: $K=2\times \frac{C_s}{C_{\mathrm{fn}}},$ wherein C.sub.s represents the capacitance value of the sampling capacitor C.sub.s, and C.sub.fn represents the capacitance value of the balancing capacitor C.sub.fn.

5. The chip state monitoring circuit according to claim 2, wherein in each sampling cycle, the self-balancing differential signal integration and amplification circuit successively undergoes a sampling stage, an integration stage, and a holding stage; in each sampling cycle before the self-balancing differential signal integration and amplification circuit achieves self balancing: in the sampling stage, the sampling network samples the charge of the state signal; in the integration stage, the charge sampled by the sampling network is transferred to the positive coefficient integration network and the negative coefficient balancing network, to increase the output signal of the self-balancing differential signal integration and amplification circuit; and in the holding stage, the output signal of the fully differential operational amplifier remains unchanged; and in each sampling cycle after the self-balancing differential signal integration and amplification circuit achieves self balancing after a plurality of sampling cycles: in the sampling stage, the sampling network samples the charge of the state signal; in the integration stage, the charge sampled by the sampling network is completely transferred to the negative coefficient balancing network, to keep the output signal of the self-balancing differential signal integration and amplification circuit unchanged; and in the holding stage, the output signal of the fully differential operational amplifier remains unchanged.

6. The chip state monitoring circuit according to claim 5, wherein in the integration stage of each sampling cycle before the self-balancing differential signal integration and amplification circuit achieves self balancing, the fully differential operational amplifier starts working, a charge sampled by a sampling capacitor is transferred to the positive coefficient integration network and the negative coefficient balancing network, and the charge transferred to the negative coefficient balancing network increases as the output signal of the fully differential operational amplifier increases, to gradually enhance the reverse adjustment function achieved by the negative coefficient balancing network.

7. The chip state monitoring circuit according to claim 5, wherein the self-balancing differential signal integration and amplification circuit further comprises a common-mode signal generation circuit connected to a common-mode signal terminal Com of the fully differential operational amplifier; a first circuit structure is connected between a positive input terminal Ip and a negative output terminal On of the fully differential operational amplifier, a second circuit structure is connected between a negative input terminal In and a positive output terminal Op of the fully differential operational amplifier, and the first circuit structure is symmetrical with the second circuit structure; and each circuit structure comprises the sampling network, the positive coefficient integration network, and the negative coefficient balancing network; and in each sampling cycle of the self-balancing differential signal integration and amplification circuit, in the sampling stage, the sampling network in the first circuit structure is connected to a positive differential input terminal V.sub.inp of the self-balancing differential signal integration and amplification circuit for sampling, and the sampling network in the second circuit structure is connected to a negative differential input terminal V.sub.inn of the self-balancing differential signal integration and amplification circuit for sampling; in the integration stage, the sampling network in the first circuit structure is connected to the negative differential input terminal V.sub.inn of the self-balancing differential signal integration and amplification circuit, and the sampling network in the second circuit structure is connected to the positive differential input terminal V.sub.inp of the self-balancing differential signal integration and amplification circuit; and a changing voltage difference on the sampling capacitor in each of the two sampling networks enables the sampled charge to be transferred to an integration capacitor C.sub.fp in the positive coefficient integration network and a balancing capacitor C.sub.fn in the negative coefficient balancing network in the corresponding circuit structure of the sampling network.

8. The chip state monitoring circuit according to claim 7, wherein the first circuit structure comprises: an upper plate of the sampling capacitor C.sub.s in the sampling network is connected to the positive differential input terminal V.sub.inp of the self-balancing differential signal integration and amplification circuit through a switch S.sub.6, the upper plate of the sampling capacitor C.sub.s is further connected to the negative differential input terminal V.sub.inn of the self-balancing differential signal integration and amplification circuit through a switch S.sub.7, a lower plate of the sampling capacitor C.sub.s is connected to a lower plate of the balancing capacitor C.sub.fn in the negative coefficient balancing network, an upper plate of the balancing capacitor C.sub.fn is connected to the negative output terminal On of the fully differential operational amplifier through a switch S.sub.1, the upper plate of the balancing capacitor C.sub.fn is further connected to the common-mode signal terminal Com of the fully differential operational amplifier through a switch S.sub.2, the lower plate of the sampling capacitor C.sub.s is further connected to a lower plate of the integration capacitor C.sub.fp in the positive coefficient integration network through a switch S.sub.3, an upper plate of the integration capacitor C.sub.fp is connected to the negative output terminal On of the fully differential operational amplifier through a switch S.sub.4, the lower plate of the integration capacitor C.sub.fp is further connected to the positive input terminal Ip of the fully differential operational amplifier, and the positive input terminal Ip and the negative output terminal On of the fully differential operational amplifier are also bridged through a switch S.sub.5, wherein the switch S.sub.1 is controlled by a control signal ctrl1 the switch S.sub.2, the switch S.sub.5, and the switch S.sub.6 are all controlled by a control signal ctrl2 the switch S.sub.3 is controlled by a control signal ctrl3 and the switch S.sub.4 and the switch S.sub.7 are controlled by a control signal ctrl4.

9. The chip state monitoring circuit according to claim 8, wherein a working process of the first circuit structure in each sampling cycle is as follows: in the sampling stage, the control signal ctrl2 controls the switch S.sub.2, the switch S.sub.5, and the switch S.sub.6 to be closed, the control signal ctrl3 controls the switch S.sub.3 to be closed, the control signal ctrl1 controls the switch to be opened, and the control signal ctrl4 controls the switch S.sub.4 and the switch S.sub.7 to be opened; the upper plate of the sampling capacitor C.sub.s in the first circuit structure is connected to the positive differential input terminal inn V.sub.inp, the positive input terminal Ip and the negative output terminal On of the fully differential operational amplifier are short circuited, a value obtained after the short circuit is connected to the lower plate of the sampling capacitor C.sub.s and the lower plate of the balancing capacitor C.sub.fn, and the upper plate of the balancing capacitor C.sub.fn is connected to an output terminal of the common-mode signal generation circuit; and a charge in the integration capacitor C.sub.fn remains unchanged; in the integration stage, the control signal ctrl2 controls the switch S.sub.2, the switch S.sub.5, and the switch S.sub.6 to be opened, the control signal ctrl3 controls the switch S.sub.3 to be closed, the control signal ctrl1 controls the switch S.sub.1 to be closed, and the control signal ctrl4 controls the switch S.sub.4 and the switch S.sub.7 to be closed; the fully differential operational amplifier starts working; the upper plate of the sampling capacitor C.sub.s in the first circuit structure is connected to the negative differential input terminal V.sub.inn, and the lower plate of the sampling capacitor C.sub.s, the lower plate of the balancing capacitor C.sub.fn, and the lower plate of the integration capacitor C.sub.fp are connected and are connected to the positive input terminal Ip of the fully differential operational amplifier; the upper plate of the balancing capacitor C.sub.fn and the upper plate of the integration capacitor C.sub.fp are connected and are connected to the negative output terminal On of the fully differential operational amplifier; and a changing voltage difference on the sampling capacitor C.sub.s enables the sampled charge to be transferred to the balancing capacitor C.sub.fn and the integration capacitor C.sub.fp; and in the holding stage, the control signal ctrl2 controls the switch S.sub.2 the switch S.sub.5, and the switch S.sub.6 to be opened, the control signal ctrl3 controls the switch S.sub.3 to be opened, the control signal ctrl1 controls the switch S.sub.1 to be opened, and the control signal ctrl4 controls the switch S.sub.4 and the switch S.sub.7 to be closed; two terminals of the integration capacitor C.sub.fp are respectively connected to the positive input terminal Ip and the negative output terminal On of the fully differential operational amplifier; and the fully differential operational amplifier maintains the output signal unchanged.

10. The chip state monitoring circuit according to claim 9, wherein in the working process of the first circuit structure in each sampling cycle, a change of the sampled charge is as follows: in the sampling stage, a charge sampled by the sampling capacitor C.sub.s is calculated according to a formula Q.sub.s.sup.s=(V.sub.com=V.sub.inp)*C.sub.s, a charge in the balancing capacitor C.sub.fn is calculated according to a formula Q.sub.fn.sup.s=(V.sub.com=V.sub.Ip)*C.sub.fn, and the charge in the integration capacitor C.sub.fp is the same as that in a previous sampling cycle; in the integration stage, the charge sampled by the sampling capacitor C.sub.s is calculated according to a formula Q.sub.s.sup.i=(V.sub.com=V.sub.inn)* C.sub.s, and the charge in the balancing capacitor C.sub.fn is calculated according to a formula Q.sub.fn.sup.i=(V.sub.Ip=V.sub.On)* C.sub.fn; during switching from the sampling stage to the integration stage, a charge transferred by the sampling capacitor C.sub.s to the positive coefficient integration network and the negative coefficient balancing network due to the changing voltage difference on the sampling capacitor C.sub.s is calculated according to a formula ΔQ.sub.s=Q.sub.s.sup.s−Q.sub.s.sup.i=(V.sub.inn−V.sub.inp)*C.sub.s; in the holding stage, the charge in the integration capacitor C.sub.fp remains unchanged until a next sampling cycle; in each sampling cycle before the self-balancing differential signal integration and amplification circuit achieves self balancing, after the switching to the integration stage, a charge transferred by the sampling capacitor C.sub.s to the balancing capacitor C.sub.fn of the negative coefficient balancing network is calculated according to a formula ΔQ.sub.fn=Q.sub.fn.sup.s−Q.sub.fn.sup.i=(V.sub.On−V.sub.Ip)*C.sub.fn, and a charge transferred to the integration capacitor C.sub.fp of the positive coefficient integration network is calculated according to a formula ΔQ.sub.fp=ΔQ.sub.s−ΔQ.sub.fn=(V.sub.inn−V.sub.inp)*C.sub.s−(V.sub.On−V.sub.Ip)*C.sub.fn; as the sampling cycle changes, output signals V.sub.On and on and V.sub.Op of the fully differential operational amplifier increase, the charge ΔC.sub.fn transferred by the sampling capacitor C.sub.s to the balancing capacitor C.sub.fn increases, and the reverse adjustment function achieved by the negative coefficient balancing network is gradually enhanced; and after a plurality of sampling cycles, when ΔQ.sub.s is equal to ΔQ.sub.fn, the self-balancing differential signal integration and amplification circuit achieves self balancing; and afterwards, in each sampling cycle after the self-balancing differential signal integration and amplification circuit achieves self balancing, after the switching to the integration stage, the charge ΔQ.sub.s transferred by the sampling capacitor C.sub.s to the positive coefficient integration network and the negative coefficient balancing network is completely transferred to the balancing capacitor C.sub.fn, rather than to the integration capacitor C.sub.fp, and the output signal of the self-balancing differential signal integration and amplification circuit is stabilized to the state signal amplified by the K times; wherein C.sub.s represents the capacitance value of the sampling capacitor C.sub.s, C.sub.fn represents the capacitance value of the balancing capacitor C.sub.fn, V.sub.com represents a voltage output by the common-mode signal generation circuit to the common-mode signal terminal Com of the fully differential operational amplifier, V.sub.inp represents a voltage at the positive differential input terminal V.sub.inp, V.sub.inn represents a voltage at the negative differential input terminal V.sub.inn, V.sub.Ip represents a voltage at the positive input terminal Ip of the fully differential operational amplifier, and V.sub.On represents a voltage at the negative output terminal On of the fully differential operational amplifier.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0013] FIG. 1 schematically shows a circuit connection of a chip state monitoring circuit in a chip according to an embodiment of the present disclosure;

[0014] FIG. 2 is a circuit diagram of a self-balancing differential signal integration and amplification circuit in a chip state monitoring circuit according to an embodiment of the present disclosure;

[0015] FIG. 3 is a sequence chart of controlling a corresponding switch by each control signal in FIG. 2; and

[0016] FIG. 4 shows a voltage change of an output signal of a self-balancing differential signal integration and amplification circuit, as well as changes of quantities of charges transferred by a sampling capacitor to two networks with respect to a sampling cycle according to the present disclosure.

DETAILED DESCRIPTION OF THE EMBODIMENTS

[0017] Specific implementations of the present disclosure will be further described with reference to the accompanying drawings.

[0018] The present disclosure provides a chip state monitoring circuit based on a self-balancing differential signal integration and amplification circuit. A chip may be a field programmable gate array (FPGA) chip or an application specific integrated circuit (ASIC) chip, such as an SRAM-type FPGA. The chip state monitoring circuit includes a state sensing circuit, a self-balancing differential signal integration and amplification circuit, and an analog-to-digital converter that are sequentially connected. The analog-to-digital converter is connected to a chip configuration circuit inside the chip. Referring to a schematic diagram of an internal structure of the chip shown in FIG. 1, the chip state monitoring circuit may be added to an existing chip architecture to monitor an operating state of the chip, thereby ensuring operational reliability of the chip. It should be noted that FIG. 1 only schematically illustrates a connection relationship between the chip state monitoring circuit and the chip configuration circuit when the chip state monitoring circuit is disposed inside the chip, and does not represent an actual position and an occupied chip region of the chip state monitoring circuit inside the chip.

[0019] The state sensing circuit is disposed at a to-be-detected point inside the chip to sense a differential-form state signal of the chip. The self-balancing differential signal integration and amplification circuit amplifies the sensed state signal, and the amplified state signal is output to the chip configuration circuit after undergoing analog-to-digital conversion by the analog-to-digital converter. The chip configuration circuit can provide a timely feedback or response after receiving the state signal. The state sensing circuit may be any type of sensor, and the sensed state signal may be any important operating parameter of the chip.

[0020] For example, in a typical application, the chip is the SRAM-type FPGA, and the state sensing circuit is a temperature sensor. In this case, the sensed state signal is a temperature signal. In an operating process of the chip, excessively accumulated heat can easily cause a thermal breakdown or an electrical breakdown. Because the SRAM type-FPGA cannot save its own data after a power failure, it is of very important application value to monitor the temperature signal in an operating process of the SRAM-type FPGA. Subsequently, the chip configuration circuit can adjust an operating frequency of a dormant frequency in a timely manner to effectively provide high-temperature protection for the SRAM-type FPGA, thereby improving reliability and a service life of the chip. This is also true for other important operating parameters in addition to a temperature.

[0021] In the chip state monitoring circuit, the sensed state signal is generally a differential-form alternating current (AC) small signal. Therefore, it is necessary to use a differential signal integration and amplification circuit to amplify the state signal. A conventional differential signal integration and amplification circuit amplifies a differential signal based on a fixed cycle, and performs integration until a maximum output swing of the circuit is reached, and the amplified signal needs to be read regularly. This makes it difficult to perform control and adjust an amplification factor. Moreover, the conventional differential signal integration and amplification circuit has a complex peripheral circuit, which occupies a lot of chip resources and chip area, and makes it difficult to apply the conventional differential signal integration and amplification circuit to a scenario with a high integration requirement, such as the chip. Therefore, the chip state monitoring circuit in the present disclosure cannot directly use an existing common differential signal integration and amplification circuit.

[0022] In order to meet an internal usage requirement of the chip, the present disclosure uses a brand new self-balancing differential signal integration and amplification circuit. The self-balancing differential signal integration and amplification circuit includes a fully differential operational amplifier, a positive coefficient integration network, and a negative coefficient balancing network. Both the positive coefficient integration network and the negative coefficient balancing network are connected between an input terminal and an output terminal of the fully differential operational amplifier. The fully differential operational amplifier amplifies the state signal under the action of the positive coefficient integration network, and performs reverse adjustment on signal amplification under the action of the negative coefficient balancing network. The self-balancing differential signal integration and amplification circuit achieves an amplification function of the state signal as a whole, but a reverse adjustment function achieved by the negative coefficient balancing network is gradually enhanced until achieving self balancing with the amplification factor, such that an output signal of the self-balancing differential signal integration and amplification circuit finally reaches a stable state and outputs a state signal amplified by K times.

[0023] The signal amplification function of the positive coefficient integration network and the reverse adjustment function of the negative coefficient balancing network change according to a following method: The self-balancing differential signal integration and amplification circuit further includes a sampling network. The sampling network samples a charge of the state signal, and the charge sampled by the sampling network is transferred to the positive coefficient integration network and the negative coefficient balancing network.

[0024] Before the self-balancing differential signal integration and amplification circuit achieves self balancing, one part of the charge sampled by the sampling network is transferred to the positive coefficient integration network to achieve the signal amplification function, and the other part of the charge sampled by the sampling network is transferred to the negative coefficient balancing network to achieve the reverse adjustment function of the signal amplification. An overall signal amplification effect is better than a reverse adjustment effect, so the output signal of the self-balancing differential signal integration and amplification circuit gradually increases. As an output signal of the fully differential operational amplifier increases, the charge transferred by the sampling network to the negative coefficient balancing network increases, such that the reverse adjustment function achieved by the negative coefficient balancing network is gradually enhanced.

[0025] After the self-balancing differential signal integration and amplification circuit achieves self balancing, the charge sampled by the sampling network is completely transferred to the negative coefficient balancing network, such that the output signal of the self-balancing differential signal integration and amplification circuit is stabilized to the state signal amplified by the K times.

[0026] Actually, the self-balancing differential signal integration and amplification circuit works based on a cycle and the output signal increases gradually. In each sampling cycle, the self-balancing differential signal integration and amplification circuit increases its output signal through a sampling stage, an integration stage, and a holding stage in sequence, and finally the output signal becomes stable after a plurality of sampling cycles. A working process of the self-balancing differential signal integration and amplification circuit is as follows:

[0027] In each sampling cycle before the self-balancing differential signal integration and amplification circuit achieves self balancing: (1) In the sampling stage, the sampling network samples the charge of the state signal. (2) In the integration stage, the fully differential operational amplifier starts working, and the sampling network transfers the sampled charge to the positive coefficient integration network and the negative coefficient balancing network according to the process described above, to increase the output signal of the self-balancing differential signal integration and amplification circuit. (3) In the holding stage, the output signal of the fully differential operational amplifier remains unchanged.

[0028] As the sampling cycle progresses, the charge transferred by the sampling network to the integration network and the charge transferred by the sampling network to the balancing network are not fixed in integration stages of different sampling cycles. The charge transferred by the sampling network to the negative coefficient balancing network increases as the output signal of the fully differential operational amplifier increases. Therefore, the reverse adjustment function achieved by the negative coefficient balancing network is gradually enhanced with the sampling cycle, until a balance between the reverse adjustment function achieved by the negative coefficient balancing network and the amplification function achieved by the positive coefficient integration network is finally achieved. In this way, after a plurality of sampling cycles, the self-balancing differential signal integration and amplification circuit achieves self balancing. In each sampling cycle after the self-balancing differential signal integration and amplification circuit achieves self balancing: (1) In the sampling stage, the sampling network also samples the charge of the state signal. (2) In the integration stage, the fully differential operational amplifier starts working, and the sampling network completely transfers the sampled charge to the negative coefficient balancing network to keep the output signal of the self-balancing differential signal integration and amplification circuit unchanged. (3) In the holding stage, the output signal of the fully differential operational amplifier remains unchanged.

[0029] The sampling network is built based on sampling capacitor C.sub.s, the positive coefficient integration network is built based on integration capacitor C.sub.fp, and the negative coefficient balancing network is built based on balancing capacitor C.sub.fn. FIG. 2 is a circuit diagram of the self-balancing differential signal integration and amplification circuit according to an embodiment. As shown in FIG. 2, the self-balancing differential signal integration and amplification circuit has a simple circuit structure and does not require a complex peripheral circuit. The self-balancing differential signal integration and amplification circuit further includes a common-mode signal generation circuit. The common-mode signal generation circuit is connected to common-mode signal terminal Com of the fully differential operational amplifier U1 to provide voltage V.sub.com. In an embodiment, the common-mode signal generation circuit is implemented by a voltage division circuit composed of resistor R.sub.1 and resistor R.sub.2.

[0030] A first circuit structure is connected between positive input terminal Ip and negative output terminal On of the fully differential operational amplifier U1, and a second circuit structure is connected between negative input terminal In and positive output terminal Op of the fully differential operational amplifier U1. The first circuit structure is symmetrical with the second circuit structure, and their working processes are the same. Each circuit structure includes the sampling network, the positive coefficient integration network, and the negative coefficient balancing network.

[0031] In each sampling cycle of the self-balancing differential signal integration and amplification circuit: (1) In the sampling stage, the sampling network in the first circuit structure is connected to positive differential input terminal V.sub.inp of the self-balancing differential signal integration and amplification circuit for sampling, and the sampling network in the second circuit structure is connected to negative differential input terminal V.sub.inn of the self-balancing differential signal integration and amplification circuit for sampling. (2) In the integration stage, the sampling network in the first circuit structure is connected to the negative differential input terminal V.sub.inn of the self-balancing differential signal integration and amplification circuit, and the sampling network in the second circuit structure is connected to the positive differential input terminal V.sub.inp of the self-balancing differential signal integration and amplification circuit. Therefore, a changing voltage difference on the sampling capacitor in each sampling network enables the sampled charge to be transferred to the positive coefficient integration network and the negative coefficient balancing network in a corresponding circuit structure of the sampling network.

[0032] Referring to FIG. 2, in the first circuit structure, an upper plate of the sampling capacitor C.sub.s in the sampling network is connected to the positive differential input terminal V.sub.inp of the self-balancing differential signal integration and amplification circuit through switch S.sub.6, and the upper plate of the sampling capacitor C.sub.s is further connected to the negative differential input terminal V.sub.inn of the self-balancing differential signal integration and amplification circuit through switch S.sub.7. A lower plate of the sampling capacitor C.sub.s is connected to a lower plate of the balancing capacitor C.sub.fn in the negative coefficient balancing network, and an upper plate of the balancing capacitor C.sub.fn is connected to the negative output terminal On of the fully differential operational amplifier through switch S.sub.1. The upper plate of the balancing capacitor C.sub.fn is further connected to the common-mode signal terminal Com of the fully differential operational amplifier through switch S.sub.2. The lower plate of the sampling capacitor C.sub.s is further connected to a lower plate of the integration capacitor C.sub.fp in the positive coefficient integration network through switch S.sub.3, and an upper plate of the integration capacitor C.sub.fp is connected to the negative output terminal On of the fully differential operational amplifier through switch S.sub.4. The lower plate of the integration capacitor C.sub.fp is further connected to the positive input terminal IP of the fully differential operational amplifier, and the positive input terminal IP and the negative output terminal On of the fully differential operational amplifier are bridged through switch S.sub.5.

[0033] The second circuit structure is symmetrical with the first circuit structure, and same reference numerals are used in FIG. 2. In the second circuit structure, the upper plate of the sampling capacitor C.sub.s in the sampling network is connected to the negative differential input terminal V.sub.inn through switch S.sub.6 and the upper plate of the sampling capacitor C.sub.s is further connected to the positive differential input terminal V.sub.inp through switch S.sub.7. The lower plate of the sampling capacitor C.sub.s is connected to the lower plate of the balancing capacitor C.sub.fn in the negative coefficient balancing network, and the upper plate of the balancing capacitor C.sub.fn is connected to the positive output terminal Op of the fully differential operational amplifier through switch S.sub.1. The upper plate of the balancing capacitor C.sub.fn is further connected to the common-mode signal terminal Com of the fully differential operational amplifier through switch S.sub.2. The lower plate of the sampling capacitor C.sub.s is further connected to the lower plate of the integration capacitor C.sub.fp in the positive coefficient integration network through switch S.sub.3, and the upper plate of the integration capacitor C.sub.fp is connected to the positive output terminal Op of the fully differential operational amplifier through switch S.sub.4. The lower plate of the integration capacitor C.sub.fp is further connected to the negative input terminal in of the fully differential operational amplifier, and the positive input terminal IP and the negative output terminal On of the fully differential operational amplifier are bridged through the switch S.sub.5.

[0034] In the two circuit structures, the switch S.sub.1 is controlled by control signal ctrl1, the switch S.sub.2, the switch S.sub.5, and the switch S.sub.6 are all controlled by control signal ctrl2, the switch S.sub.3 is controlled by control signal ctrl3, and the switch S.sub.4 and the switch S.sub.7 are controlled by control signal ctrl4.

[0035] Based on the circuit diagram shown in FIG. 2, referring to a sequence chart of controlling a corresponding switch by each control signal in FIG. 3, as well as a voltage change value shown in FIG. 4, the working process of the self-balancing differential signal integration and amplification circuit is as follows. Because the first circuit structure and the second circuit structure are symmetrical and have the same working process, the working process of the first circuit structure in each sampling cycle is described as follows:

[0036] (1) In the sampling stage, the control signal ctrl2 controls the switch S.sub.2, the switch S.sub.5, and the switch S.sub.6 to be closed, the control signal ctrl3 controls the switch S.sub.3 to be closed, the control signal ctrl1 controls the switch S.sub.1 to be opened, and the control signal ctrl4 controls the switch S.sub.4 and the switch S.sub.7 to be opened.

[0037] Because the switch S.sub.5 is closed, the positive input terminal IP and the negative output terminal On of the fully differential operational amplifier U1 are short circuited, and the negative input terminal In and the positive output terminal Op of the fully differential operational amplifier are short circuited. A value generated after the short circuit is connected to the lower plate of the sampling capacitor C.sub.s through path F.fwdarw.D.fwdarw.B, and is also connected to the lower plate of the balancing capacitor C.sub.fn.

[0038] Because the switch S.sub.6 is closed and the switch S.sub.7 is opened, the upper plate of the sampling capacitor C.sub.s in the first circuit structure is connected to the positive differential input terminal V.sub.inp. Therefore, a charge sampled by the sampling capacitor C.sub.s is calculated according to formula Q.sub.s.sup.s=(V.sub.com−V.sub.inp)*C.sub.s, where C.sub.s represents a capacitance value of the sampling capacitor C.sub.s.

[0039] The upper plate of the balancing capacitor C.sub.fn is connected to an output terminal of the common-mode signal generation circuit, and the voltage is V.sub.com. Therefore, a charge in the balancing capacitor C.sub.fn calculated according to formula Q.sub.fn.sup.s=(V.sub.com−V.sub.Ip)*C.sub.fn, where V.sub.Ip represents a voltage of the positive input terminal Ip of the fully differential operational amplifier, and C.sub.fn represents a capacitance value of the balancing capacitor C.sub.fn. Because the positive input terminal Ip and the negative output terminal On are short circuited V.sub.com=V.sub.Ip=V.sub.On. Therefore, Q.sub.fn.sup.s=(V.sub.com−V.sub.Ip)*C.sub.fn=0. V.sub.Ip represents the voltage of the positive input terminal Ip of the fully differential operational amplifier, and V.sub.onrepresents a voltage of the negative output terminal On of the fully differential operational amplifier.

[0040] Because the switch S.sub.1 and the switch S.sub.4 are opened, a charge in the integration capacitor C.sub.fp remains unchanged, which is equal to a charge in a previous sampling cycle.

[0041] (2) In the integration stage, the control signal ctrl2 controls the switch S.sub.2, the switch S.sub.5, and the switch S.sub.6 to be opened, the control signal ctrl3 controls the switch S.sub.3 to be closed, the control signal ctrl1 controls the switch S.sub.1 to be closed, and the control signal ctrl4 controls the switch S.sub.4 and the switch S.sub.7 to be closed.

[0042] Because the switch S.sub.5 is opened, the fully differential operational amplifier starts working, and the upper plate of the sampling capacitor C.sub.s in the first circuit structure switches to the negative differential input terminal V.sub.inn. In this case, the charge sampled by the sampling capacitor C.sub.s is calculated according to formula Q.sub.s.sup.i=(V.sub.com−V.sub.inn)* C.sub.s, where V.sub.inn represents a voltage of the negative differential input terminal V.sub.inn. During switching from the sampling stage to the integration stage, the changing voltage difference on the sampling capacitor C.sub.s enables the charge sampled by the sampling capacitor C.sub.s to be transferred to the balancing capacitor C.sub.fn and the integration capacitor C.sub.fp, with the transferred charge being ΔQ.sub.s=Q.sub.s.sup.s−Q.sub.s.sup.i=(V.sub.inn−V.sub.inp)*C.sub.s.

[0043] The lower plate of the sampling capacitor C.sub.s, the lower plate of the balancing capacitor C.sub.fn, and the lower plate of the integration capacitor C.sub.fp are connected and are connected to the positive input terminal Ip of the fully differential operational amplifier. The upper plate of the balancing capacitor C.sub.fn and the upper plate of the integration capacitor C.sub.fp are connected and are connected to the negative output terminal On of the fully differential operational amplifier.

[0044] Therefore, in this case, the charge in the balancing capacitor C.sub.fn is calculated according to formula Q.sub.fn.sup.i=(V.sub.Ip−V.sub.On)* C.sub.fn. Since the charge change in the balancing capacitor C.sub.fn is caused by the charge transfer by the sampling capacitor C.sub.s, it can be determined that the charge transferred by the sampling capacitor C.sub.s to the balancing capacitor C.sub.fn of the negative coefficient balancing network is calculated according to formula ΔQ.sub.fn=Q.sub.fn.sup.s−Q.sub.fn.sup.i=(V.sub.On−V.sub.Ip)*C.sub.fn.

[0045] Further, it can be determined that the charge transferred by the sampling capacitor C.sub.s to the integration capacitor C.sub.fp of the positive coefficient integration network is calculated according to ΔQ.sub.fp=ΔQ.sub.s−ΔQ.sub.fni=(V.sub.inn−V.sub.inp)*C.sub.s−(V.sub.On−V.sub.Ip)*C.sub.fn.

[0046] (3) In the holding stage, the control signal ctrl2 controls the switch S.sub.2, the switch S.sub.5, and the switch S.sub.6 to be opened, the control signal ctrl3 controls the switch S.sub.3 to be opened, the control signal ctrl1 controls the switch S.sub.1 to be opened, and the control signal ctrl4 controls the switch S.sub.4 and the switch S.sub.7 to be closed. Two terminals of the integration capacitor C.sub.fp are respectively connected to the input terminal and the output terminal of the fully differential operational amplifier. The fully differential operational amplifier keeps the output signal unchanged, and the charge of the integration capacitor remains C.sub.fp unchanged until a next sampling cycle.

[0047] Based on the working process described above, it can be determined that in each sampling cycle when ΔQ.sub.s and ΔQ.sub.fn are unequal, in other words, before the self-balancing differential signal integration and amplification circuit achieves self balancing, after the switching to the integration stage, the sampling capacitor C.sub.s transfers the charge to the positive coefficient integration network and the negative coefficient balancing network, and charges respectively transferred to the positive coefficient integration network and the negative coefficient balancing network are as described above. In addition, as the sampling cycle changes, output signals V.sub.On and V.sub.Op of the fully differential operational amplifier increase, such that the charge ΔQ.sub.fn transferred by the sampling capacitor C.sub.s to the balancing capacitor C.sub.fn in the sampling stage increases, and the reverse adjustment function achieved by the negative coefficient balancing network is enhanced.

[0048] After a plurality of sampling cycles, when ΔQ.sub.fn increases to be equal to ΔQ.sub.s, the self-balancing differential signal integration and amplification circuit achieves self balancing. Afterwards, in each sampling cycle, the charge ΔQ.sub.s transferred by the sampling capacitor C.sub.s to the positive coefficient integration network and the negative coefficient balancing network is completely transferred to the balancing capacitor C.sub.fn, rather than to the integration capacitor C.sub.fp, such that the output signal of the self-balancing differential signal integration and amplification circuit is stabilized to the state signal amplified by the K times. As shown in FIG. 4, if a voltage of the state signal obtained from the differential input terminal is set to V.sub.inp−V.sub.inn=ΔV, the output signal of the self-balancing differential signal integration and amplification circuit gradually increases with the sampling cycle until it is finally stabilized at V.sub.Op−V.sub.On=K×ΔV. Then, as the sampling cycle changes, the output signal of the self-balancing differential signal integration and amplification circuit no longer changes, achieving a stable output effect.

[0049] FIG. 4 shows changes of quantities of charges ΔQ.sub.s transferred by the sampling capacitor C.sub.s to the positive coefficient integration network and the negative coefficient balancing network with respect to the sampling cycle. It can be seen from FIG. 4 that as a quantity of sampling cycles increases, the charge ΔQ.sub.fp transferred by the sampling capacitor C.sub.s to the integration capacitor C.sub.fp gradually decreases, and the charge ΔQ.sub.fn transferred by the sampling capacitor C.sub.s to the balancing capacitor C.sub.fn gradually increases to be equal to ΔQ.sub.fn. In a subsequent sampling cycle, the charge ΔQ.sub.fn transferred to the balancing capacitor C.sub.fn of the negative coefficient balancing network is always ΔQ.sub.s, and the charge ΔQ.sub.fp transferred to the integration capacitor C.sub.fp is always 0.

[0050] The amplification factor K achieved for the state signal by the self-balancing differential signal integration and amplification circuit in the stable state is determined by the capacitance value of the sampling capacitor C.sub.s and the capacitance value of the balancing capacitor CC.sub.fn. Referring to FIG. 2, it is assumed that C.sub.s=M×C.sub.fn, where C.sub.s represents the capacitance value of the sampling capacitor C.sub.s, C.sub.fn represents the capacitance value of the balancing capacitor C.sub.fn, and M represents a positive coefficient. It can be inferred and determined that V.sub.on=V.sub.com−M*(V.sub.inp−V.sub.inn) and V.sub.op=V.sub.com+M*(V.sub.inp−V.sub.inn) .Therefore, the amplification factor

[00001]$K=\frac{V_{op}-V_{on}}{V_{\mathrm{inp}}-V_{\mathrm{inn}}}=2M=2\times \frac{C_s}{C_{fn}}$

achieved when the self-balancing differential signal integration and amplification circuit reaches the stable state can be obtained. Therefore, the amplification factor K can be accurately adjusted by adjusting a ratio of the sampling capacitance C.sub.s to the balancing capacitance C.sub.fn.

[0051] The above described are merely preferred implementations of the present disclosure, and the present disclosure is not limited to the above embodiments. It can be understood that other improvements and modifications directly derived or associated by those skilled in the art without departing from the spirit and concept of the present disclosure should be regarded as falling within the protection scope of the present disclosure.