FREQUENCY MULTIPLIER CIRCUIT

Abstract

According to a first aspect of the disclosure, an integrated frequency multiplier circuit is provided. The circuit comprises a substrate, a strip of graphene, first and second electrode, a dielectric layer, a frequency input electrode, and a frequency output electrode. The strip of graphene has a uniform width provided on the substrate, the strip having a width x and a length y extending from a first end to a second end. The first and second electrodes are provided in electrical contact with the strip of graphene at the first and second ends of the strip of graphene respectively. The dielectric layer is provided on the strip of graphene, wherein the dielectric layer is provided across the width x of the strip of graphene. The frequency input electrode is formed on the dielectric layer, wherein the frequency input electrode is provided across the width x of the strip of graphene. The frequency input electrode is provided over the strip of graphene at a location closer to the first end of the strip of graphene than the second end. The frequency output electrode is provided in electrical contact with the strip of graphene at a location along the length of the strip of graphene between the second electrode and the frequency input electrode, spaced apart from the second electrode.

Claims

1. An integrated frequency multiplier circuit comprising: a substrate; a strip of graphene having a uniform width provided on the substrate, the strip having a width x and a length y extending from a first end to a second end; first and second electrodes provided in electrical contact with the strip of graphene at the first and second ends respectively; a dielectric layer provided on the strip of graphene, the dielectric layer provided across the width x of the strip of graphene a frequency input electrode formed on the dielectric layer, the frequency input electrode provided across the width x of the strip of graphene, wherein the frequency input electrode is provided over the strip of graphene at a location closer to the first end of the strip of graphene than the second end; a frequency output electrode provided in electrical contact with the strip of graphene at a location along the length of the strip of graphene between the second electrode and the frequency input electrode and spaced apart from the second electrode.

2. The integrated frequency multiplier circuit according to claim 1 wherein the frequency output electrode is equally spaced from the first and second electrodes along the strip of graphene.

3. The integrated frequency multiplier circuit according to claim 1, wherein the graphene sheet has a sheet resistance in the range of 250 Ω/sq to 10 kΩ/sq.

4. The integrated frequency multiplier circuit according to claim 1, wherein the first and second electrical contacts are each provided on the substrate adjacent to the strip of graphene such that each of the first and second electrical contacts are in direct contact with a respective edge of the strip of graphene.

5. The integrated frequency multiplier circuit according to claim 1, wherein the substrate comprises a non-metallic surface on which the graphene strip is provided.

6. The integrated frequency multiplier circuit according to claim 1, wherein the dielectric layer comprises an inorganic oxide, nitride, carbide, fluoride or sulphide, preferably alumina or silica.

7. The integrated frequency multiplier circuit according to claim 1, wherein the length y of the strip of graphene is at least 5 mm and/or no greater than 20 mm; and/or the width x of the strip of graphene is at least 1 mm and/or no greater than 10 mm.

8. The integrated frequency multiplier circuit according to claim 1, wherein the location of the frequency output electrode on the strip of graphene and a sheet resistance of the graphene is provided such that a resistance of the strip of graphene between the frequency output electrode and the second electrode is at least 250 Ω and/or no greater than 50 kΩ.

9. The integrated frequency multiplier circuit according to claim 1, wherein an aspect ratio of the length y of the strip of graphene to the width w of the strip of graphene is at least 0.5; and/or the aspect ratio of the length y of the strip of graphene to the width w of the strip of graphene is no greater than 20.

10. The integrated frequency multiplier circuit according to claim 1, further comprising: a resistance dielectric layer provided on the strip of graphene, the resistance dielectric layer provided across the width x of the strip of graphene and between the frequency output electrode and the second end of the strip of graphene; and a variable resistance electrode provided on the resistance dielectric layer, the variable resistance dielectric layer provided across the width x of the strip of graphene.

11. The integrated frequency multiplier circuit according to claim 1 provided as part of an AC to DC current converter circuit, further comprising a capacitor connected between the frequency output electrode and the first electrode formed at the first end of the graphene strip.

12. The integrated frequency multiplier circuit according to claim 11, wherein the capacitor is formed on the substrate, and the AC to DC current converter circuit further comprises: a third electrode extending between the frequency output electrode and a first terminal of the capacitor; and a fourth electrode extending between the first electrode and a second terminal of the capacitor.

13. The integrated frequency multiplier circuit according to claim 12, further comprising: a capacitor dielectric layer provided between the first terminal of the capacitor and the second terminal of the capacitor.

14. The integrated frequency multiplier circuit according to claim 11, wherein the capacitor is a graphene capacitor.

15. The integrated frequency multiplier circuit according to claim 14, wherein the graphene capacitor comprises: a first set of graphene fingers provided on the substrate; and a second set of graphene fingers provided on the substrate, wherein the first and second sets of graphene fingers are provided on the substrate such that the first and second sets of graphene fingers are interdigitated.

16. A method of forming an integrated frequency multiplier circuit comprising: depositing a graphene layer on a substrate using a chemical vapour process; patterning the graphene layer to define a strip of graphene, the strip having a width x and a length y extending from a first end to a second end; forming first and second electrodes in electrical contact with the strip of graphene at the first and second ends respectively; forming a dielectric layer on the strip of graphene, the dielectric layer extending across the width of the strip of graphene and along a portion of the length of the strip towards the second end; forming a frequency input electrode on the dielectric layer, the frequency input electrode provided across the width x of the strip of graphene, wherein the frequency input electrode is closer to the first end of the strip of graphene than the second end; and forming a frequency output electrode in electrical contact with the strip of graphene at a location along the length of the strip of graphene between the second electrode and the frequency input electrode and spaced apart from the second electrode.

17. A method of forming an AC to DC current converter circuit comprising: depositing a graphene layer on a substrate using a chemical vapour process; patterning the graphene layer to define a strip of graphene, the strip having a width x and a length y extending from a first end to a second end; forming first and second electrodes in electrical contact with the strip of graphene at the first and second ends respectively; forming a dielectric layer on the strip of graphene, the dielectric layer extending across the width of the strip of graphene and along a portion of the length of the strip towards the second end; forming a frequency input electrode on the dielectric layer, the frequency input electrode provided across the width x of the strip of graphene, wherein the frequency input electrode is closer to the first end of the strip of graphene than the second end; forming a frequency output electrode in electrical contact with the strip of graphene at a location along the length of the strip of graphene between the second electrode and the frequency input electrode and spaced apart from the second electrode; and providing a capacitor in electrical contact between the frequency output electrode and the first electrode formed at the first end of the graphene strip.

18. A method of forming an AC to DC current converter circuit according to claim 17, wherein providing the capacitor comprises: and depositing a further graphene layer on a substrate using a chemical vapour process patterning the graphene layer to define a first set of graphene on the substrate and a second set of graphene fingers on the substrate, wherein the first and second sets of graphene fingers are interdigitated.

19. The integrated frequency multiplier circuit according to claim 1, wherein the substrate comprises silicon (Si), silicon carbide (SiC), silicon nitride (Si.sub.3N.sub.4), silicon dioxide (SiO.sub.2), sapphire (Al.sub.2O.sub.3), aluminium gallium oxide (AGO), hafnium dioxide (HfO.sub.2), zirconium dioxide (ZrO.sub.2), yttria-stabilised hafnia (YSH), yttria-stabilised zirconia (YSZ), magnesium aluminate (MgAl.sub.2O.sub.4), yttrium orthoaluminate (YAlO.sub.3), strontium titanate (SrTiO.sub.3), cerium oxide (Ce.sub.2O.sub.3), scandium oxide (Sc.sub.2O.sub.3), erbium oxide (Er.sub.2O.sub.3), magnesium difluoride (MgF.sub.2), calcium difluoride (CaF.sub.2), strontium difluoride (SrF.sub.2), barium difluoride (BaF.sub.2), scandium trifluoride (ScF.sub.3), germanium (Ge), hexagonal boron nitride (h-BN), cubic boron nitride (c-BN) and/or a III/V semiconductor.

20. The integrated frequency multiplier circuit according to claim 1, wherein the substrate comprises a III/V semiconductor selected from aluminium nitride (A1N) and gallium nitride (GaN).

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Embodiments of the disclosure will now be described, by way of example only, with reference to accompanying figures in which:

[0041] FIG. 1 shows a schematic diagram of a frequency multiplier circuit according to an embodiment of the disclosure;

[0042] FIG. 2 is a graph of a source-drain current response of a frequency multiplier circuit according to an embodiment of the disclosure;

[0043] FIG. 3 is a graph depicting the frequency multiplication of a 0.5 Hz input wave using a frequency multiplier circuit according to an embodiment of the disclosure;

[0044] FIG. 4 shows a schematic diagram of an AC to DC converter circuit according to an embodiment of the disclosure; and

[0045] FIG. 5 is a block diagram of a method of forming an integrated frequency multiplier circuit or an AC to DC converter according to this disclosure.

DETAILED DESCRIPTION

[0046] According to a first embodiment of the disclosure, an integrated frequency multiplier circuit 1 is provided. The integrated frequency multiplier circuit 1 comprises a substrate 10, a strip of graphene 20, a first electrode 30, a second electrode 32, a dielectric layer 40, a frequency input electrode 50, and a frequency output electrode 52. A schematic diagram showing a plan view of the integrated frequency multiplier circuit 1 is shown in FIG. 1.

[0047] As will be explained in further detail below, the integrated frequency multiplier circuit provides a transistor element and a resistor element which are interconnected in order to provide a frequency multiplication functionality. According to the first embodiment, the transistor element and the resistor element each comprise graphene.

[0048] The substrate 10 may comprise a non-metallic surface on which the other layers of the integrated frequency multiplier circuit 1 are provided. Preferably, the surface is an electrically insulative surface (for example, a substrate may be a silicon substrate having a silicon dioxide surface). The substrate 10 may also be a CMOS wafer which may be silicon based and have associated circuitry embedded within the substrate. A substrate 10 may also comprise one or more layers (for example, regions or channels of embedded waveguide materials such as silicon nitride suitable for EOMs). In another example, a substrate may comprise a non-metallic layer which provides a non-metallic growth surface, and a conductive layer (for example, silicon on insulator (SOI) substrates such as a silicon substrate having a silicon oxide layer). The conductive layer can serve as a contact for electronic devices.

[0049] Preferably, the non-metallic surface upon which the graphene layer structure is provided is silicon (Si), silicon carbide (SiC), silicon nitride (Si.sub.3N.sub.4), silicon dioxide (SiO.sub.2), sapphire (Al.sub.2O.sub.3), aluminium gallium oxide (AGO), hafnium dioxide (HfO.sub.2), zirconium dioxide (ZrO.sub.2), yttria-stabilised hafnia (YSH), yttria-stabilised zirconia (YSZ), magnesium aluminate (MgAl.sub.2O.sub.4), yttrium orthoaluminate (YAIO.sub.3), strontium titanate (SrTiO.sub.3), cerium oxide (Ce.sub.2O.sub.3), scandium oxide (Sc.sub.2O.sub.3), erbium oxide (Er.sub.2O.sub.3), magnesium difluoride (MgF.sub.2), calcium difluoride (CaF.sub.2), strontium difluoride (SrF.sub.2), barium difluoride (BaF.sub.2), scandium trifluoride (ScF.sub.3), germanium (Ge), hexagonal boron nitride (h-BN), cubic boron nitride (c-BN) and/or a III/V semiconductor such as aluminium nitride (AIN) and gallium nitride (GaN). In some embodiments, the substrate 10 may comprise sapphire or silicon, particularly for graphene prepared by the method of WO 2017/029470. Where the substrate 10 comprises sapphire, in some embodiments it is preferable that the sapphire is R-plane sapphire. As is known in the art, r-plane refers to the crystallographic orientation of the surface of the substrate (i.e. the surface upon which graphene is deposited). Such a substrate is particularly suited to providing high quality graphene which is well suited to the formation of the graphene strip 20 according to this disclosure. In part, this is due to effect of the substrate 10 on the resulting charge carrier density of the graphene deposited thereon. For example, graphene strips 20 according to this disclosure may preferably have a charge carrier density in the range of 5 × 10.sup.11 cm-.sup.2 to 1 × 10.sup.14 cm.sup.-2.

[0050] The strip of graphene 20 is formed on the substrate 10. The strip of graphene 20 has a uniform width provided on the substrate. As such, the strip of graphene 20 has a generally rectangular shape (including square shapes) formed on the substrate 10.

[0051] In the embodiment of FIG. 1, the strip of graphene has a width x and a length y extending from a first end 21 to a second end 22. In some embodiments, the length y of the strip of graphene 20 is at least: 5 mm, or 7 mm or 10 mm.

[0052] In some embodiments, the length y of the strip of graphene 20 may be no greater than: 20 mm, or 17 mm, or 15 mm. The length y of the strip of graphene 20 may be selected in order to provide a desired channel resistance for the transistor, and/or a desired resistance for the resistor.

[0053] In some embodiments, the width x of the strip of graphene is at least: 1 mm, 2 mm, 3 m, or 5 mm. In some embodiments, the width x of the strip of graphene 20 is no greater than: 10 mm, 9 mm, 8 mm, or 7 mm. The width x and length y of the strip of graphene 20 may be selected in combination in order to provide a desired channel resistance for the transistor, and/or a desired resistance for the resistor.

[0054] In some embodiments, the strip of graphene 20 may have a sheet resistance of at least 250 Ω, 500 Ω, or 1 kΩ/sq. In some embodiments, the strip of graphene 20 may have a sheet resistance of no greater than 10 kΩ/sq. The sheet resistance of the strip of graphene 20 may be controlled according to the carrier density of the strip of graphene. As such, the sheet resistance of the strip of graphene 20 may be selected in order to provide the resistor section of the integrated frequency response circuit with the desired resistance.

[0055] The strip of graphene 20 may be formed from a layer of graphene which is deposited as a continuous layer across substantially all of the substrate 10. As such, the strip of graphene 20 may be synthesised directly on the substrate 10 and therefore does not involve any physical transfer steps. The strip of graphene 20 may then be formed having the desired length y and width x using a patterning step. As such, direct synthesis of the graphene layer as a continuous layer is preferable as it allows the strip of graphene 20 to be subsequently patterned and etched in a reliable and economic manner.

[0056] Preferably the graphene layer is formed by Chemical Vapour Deposition (CVD) or MOCVD growth. It is particularly preferable that the graphene is formed by VPE or MOCVD. MOCVD is a term used to describe a system used for a particular method for the deposition of layers on a substrate. While the acronym stands for metal-organic chemical vapour deposition, MOCVD is a term in the art and would be understood to relate to the general process and the apparatus used therefor and would not necessarily be considered to be restricted to the use of metal-organic reactants or to the production of metal-organic materials but would simply require the use of a carbon containing precursor when forming graphene. Instead, the use of this term indicates to the person skilled in the art a general set of process and apparatus features. MOCVD is further distinct from CVD techniques by virtue of the system complexity and accuracy. While CVD techniques allow reactions to be performed with straight-forward stoichiometry and structures, MOCVD allows the production of difficult stoichiometries and structures. An MOCVD system is distinct from a CVD system by virtue of at least the gas distribution systems, heating and temperature control systems and chemical control systems. An MOCVD system typically costs at least 10 times as much as a typical CVD system. MOCVD is particularly preferred for achieving high quality graphene layer structures.

[0057] MOCVD can also be readily distinguished from atomic layer deposition (ALD) techniques. ALD relies on step-wise reactions of reagents with intervening flushing steps used to remove undesirable by products and/or excess reagents. It does not rely on decomposition or dissociation of the reagent in the gaseous phase. It is particularly unsuitable for the use of reagents with low vapour pressures such as silanes, which would take undue time to remove from the reaction chamber. MOCVD growth of graphene is discussed in WO 2017/029470 which is incorporated by reference and provides the preferred method.

[0058] The method of WO 2017/029470 provides a chamber which has a plurality of cooled inlets arranged so that, in use, the inlets are distributed across the substrate and have a constant separation from the substrate. The flow comprising a precursor compound may be provided as a horizontal laminar flow or may be provided substantially vertically. Inlets suitable for such reactors are well known and include Planetary and Showerhead® reactors available from Aixtron®. Other suitable growth chambers include Turbodisc K-series or Propel® MOCVD systems available from Veeco® Instruments Inc.

[0059] The graphene layer may be patterned to form the strip of graphene 20 by masking and etching steps. Lithography may be used to mask a region of the layer of graphene on the substrate 10 with a mask layer (not shown). The mask layer may comprise a photoresist, or a dielectric layer, or any other suitable mask layer for a lithographic technique known in the art.

[0060] A subsequent etching step may then be provided to remove the uncovered regions of graphene from the substrate 10. For example at least one uncovered region of the graphene layer may be etched away to form at least one covered region of graphene layer (i.e. the strip of graphene 20 plus the mask layer above). The mask layer may then be selectively removed from the strip of graphene 20 using a suitable lift of technique or selective etch (i.e. an etching process which does not etch the underlying strip of graphene 20).

[0061] Plasma etching is a typical process used in the manufacture of electronic devices and integrated circuits. Plasma etching involves the flow of a plasma of an appropriate gas mixture across the substrate, the plasma having been formed from application of an RF across two electrodes, typically under low pressure. In oxygen plasma etching, the RF radiation ionises the gas to form oxygen radicals which etch the layer structure. The byproducts, also known in the art as “ash”, are removed by a pump which are predominantly carbon monoxide and carbon dioxide when a graphene layer structure is etched by oxygen plasma etching. In a preferred embodiment, the plasma etching comprises oxygen plasma etching. In a preferred embodiment, oxygen plasma etching comprises using at least 5 W RF power, preferably at least 10 W and more preferably at least 20 W, and preferably less than 200 W, preferably less than 100 W. The flow rate of O2 may be at least 1 sccm, preferably at least 3 sccm and/or less than 50 sccm, preferably less than 30 sccm. Preferably, the chamber pressure is at least 0.1 mbar and/or at most 100 mbar, preferably at least 0.2 mbar and/or at most 10 mbar. Accordingly, the time required for plasma etching may be as little as 1 second and/or up to 5 minutes. Preferably, the time required is at least 10 seconds and/or less than 2 minutes.

[0062] The first and second electrodes 30, 32 are provided in electrical contact with the strip of graphene 20 at the first and second ends 21, 22 of the strip of graphene 20 respectively. As shown in FIG. 1, each of the first and second electrodes 30, 32 extend across the entire width x of the strip of graphene 20. As shown in FIG. 1, each of the first and second electrodes 30, 32 may have a generally rectangular shape, although other shapes may also be provided. In FIG. 1, each of first and second electrodes may extend away from the strip of graphene 20 in order to form electrical connections to other circuits or components.

[0063] Each of the first and second electrodes 30, 32 are provided in direct electrical contact with the first and second ends 21, 22 of the strip of graphene 20 in order to provide improved current injection into the strip of graphene 20. In the embodiments of FIG. 1, each of the first and second electrodes 30, 32 form Ohmic contacts with the strip of graphene 20. Preferably each of the first and second electrodes comprises one or more of titanium, aluminium, chromium and gold. Preferably, the first and second electrodes 30, 32 are titanium and/or gold electrodes. The first and second electrodes 30, 32 may be formed by any standard technique such as electron beam deposition, preferably using a mask.

[0064] In the embodiment of FIG. 1, the first and second electrical contacts 30, 32 are provided adjacent to the first and second ends 21, 22 of the strip of graphene. As such, the strip of graphene extending between the first and second contacts 30, 32 has a length y.

[0065] The frequency output electrode 52 is provided in electrical contact with the strip of graphene at a location along the length of the strip of graphene 20. The frequency output electrode may be located at a location along the length of the strip of graphene between the second electrode and the frequency input electrode, spaced apart from the second electrode. As shown in FIG. 1, the frequency output electrode 52 extends across the width x of the strip of graphene, although in some embodiments, the frequency output electrode may not extend fully across the strip of graphene 20. The frequency output electrode 52 effectively divides the strip of graphene (having length y) into two regions. A first region 60 of the strip of graphene has a length z.sub.1 and extends between the first end 21 and the frequency output electrode 52. In effect, the first region 60 provides a region of the strip of graphene in which the transistor is formed.

[0066] The second region 62 of the strip of graphene 20 having length z.sub.2 extends between the second end 22 of the strip of graphene 20 and the frequency output electrode 52. The second region 62 of the strip of graphene 20 defines a resistor extending between the second electrode 32 and the frequency output electrode 52.

[0067] The frequency output electrode 52 is located in FIG. 1 in order to define the lengths z.sub.1 and z.sub.2 of the first and second regions 60, 62 respectively. In FIG. 1, the lengths z.sub.1 and z.sub.2 (and consequently the areas of the respective first and second regions 60, 62) are about the same.

[0068] Similar to the first and second electrodes, the frequency output electrode 52 may be formed by any standard technique such as electron beam deposition, preferably using a mask. The frequency output electrode 52 may comprise any suitable contact material configured to form an Ohmic contact to the strip of graphene 20. For example, titanium and/or gold electrodes may be used.

[0069] In some embodiments, the length z.sub.1 of the first region 60 may be less than the length of the second region z.sub.2 62. As such, the length of the resistor (and the associated resistance of the resistor) may be greater than the resistance of the graphene strip in the first region 60 used to form the transistor. For example, the length z.sub.1 of the first region 60 may be greater than 60% of the length z.sub.2 of the second region 62 up to no greater than 100% of the length z.sub.2 of the second region 62.

[0070] It will be appreciated that the length of the frequency output electrode 52 in the y direction of the graphene strip is non-zero as shown in FIG. 1. The area of the frequency output electrode 52 may be selected in order to provide the desired electrical contact conductivity to the graphene strip 20. The overall length y of the graphene strip may be selected in order to provide for the desired lengths z.sub.1, z.sub.2 of the first and second regions 60, 62 and the length of the frequency output electrode 52.

[0071] The second region 62 of the graphene strip defines a resistance for the integrated frequency multiplier circuit. The size of the resistance may be selected based on the dimensions for the second region (length z.sub.2 and width x) and the sheet resistance of the graphene. In some embodiments, the second region 62 may define a resistance R between the second electrode 32 and the frequency output electrode of at least: 250 Ω, 500 Ω, or 1 kΩ. In some embodiments, the resistance R may be no greater than 50 kΩ.

[0072] As noted above, the first region 60 of the graphene strip provides a transistor functionality for the integrated frequency multiplier circuit 1. As shown in FIG. 1, the dielectric layer 40 is provided on the strip of graphene 20 in the first region 60. The dielectric layer 40 is provided across the width x of the strip of graphene. The dielectric layer 40 is provided in order to define a gate insulating layer for the transistor part of the integrated frequency multiplier circuit 1.

[0073] The dielectric layer 40 may comprise an inorganic oxide, nitride, carbide, fluoride or sulphide. In some preferred embodiments, the dielectric layer may comprise alumina or silica. The dielectric layer 40 may have a thickness (in a direction normal to the substrate 10) of at least 1 nm. The dielectric layer may have a thickness of no greater than 1000 nm. Preferably, the dielectric layer 40 is a continuous layer which is substantially free of pores, point defects and the like.

[0074] The dielectric layer 40, may be formed using any suitable process known in the art. For example, where the dielectric layer comprises alumina, the dielectric layer may be formed by a thermal evaporation technique, for example e-beam evaporation, or preferably formed by an Atomic Layer Deposition (ALD) technique. Forming the dielectric layer by thermal evaporation provides for the formation of the dielectric layer on the strip of graphene 20 without damaging the graphene sheet.

[0075] ALD is technique known in the art and comprises the reaction of at least two precursors in a sequential, self-limiting manner. Repeated cycles to the separate precursors allow the growth of a thin film of the dielectric layer in a conformal manner (i.e. uniform thickness across graphene strip 20) due to the layer by layer growth mechanism. Alumina is a particularly preferred dielectric material and can be formed by sequential exposure to trimethylaluminium (TMA) and an oxygen source, preferably one or more of water (H2O), O2, and ozone (O3), preferably water.

[0076] The frequency input electrode 50 is formed on the dielectric layer 40, wherein the frequency input electrode 50 is provided across the width x of the strip of graphene 20. As such, the frequency input electrode 50 is provided over the first region 60 of the strip of graphene. The frequency input electrode 50 is provided over the strip of graphene 20 at a location closer to the first end 21 of the strip of graphene 20 than the second end 22 (i.e. on the first region of the graphene strip 20).

[0077] The frequency input electrode 50 can be formed by any standard technique such as electron beam deposition, preferably using a mask on the dielectric layer. For example, the frequency input electrode may comprise gold or titanium contacts. In some embodiments, the frequency input electrode 50 may comprise a plurality of layers. For example, in some embodiments, the frequency input electrode 50 may comprise a bi-layer combination of Ti and Au, Al and Ni, or any two of Pt, Pd, Ag and Au.

[0078] An electrical bias can be applied to the frequency input electrode 50 in order to modulate the charge carriers within the graphene strip 20 below the frequency input electrode. As such, the frequency input electrode 50 in combination with the dielectric layer 40 defines a “top gate” structure of a Field Effect Transistor (FET), wherein the graphene strip 20 provides the “channel” layer of the FET.

[0079] One known property of graphene is that the mobility of the holes and the mobility of the electrons are approximately the same. Accordingly, a graphene FET-type device has an ambi-polar behaviour in which majority hole conduction can occur in the channel region when the device is under negative bias, and majority electron conduction can occur when the device is under positive bias. As bias is reduced towards 0 V (or a value shifted from 0 V in practice), charge carrier conduction is reduced towards a minimum point known as the Dirac point. Application of positive or negative bias about the Dirac point of a graphene FET causes an increase in current. This behaviour may be applied in order to provide frequency multiplication in the integrated frequency multiplier circuit of FIG. 1.

[0080] FIG. 2 shows a graph of the current (I.sub.SD) flowing between the first and second electrodes 30, 32 of an integrated frequency multiplier circuit 1 according to this disclosure for a range of different voltages applied to the frequency input electrode 50. In the graph of FIG. 2, a voltage of 0.5 V is applied between the first and second electrodes 30, 32 (V.sub.SD) for each measurement. As shown in FIG. 2, the Dirac point occurs at a frequency input voltage (V.sub.GS) relative to the voltage applied to the first electrode 30, of about -0.5 V. Variation in the frequency input voltage V.sub.GS about the Dirac point causes the current (I.sub.SD) to increase in magnitude. As shown in FIG. 2, the current increases in an approximately linear manner on either side of the Dirac point over a range of +/- 1 V. Such a V.sub.GS - I.sub.SD behaviour can be used to perform frequency multiplication, for example as shown in FIG. 3.

[0081] FIG. 3 shows a current output of the integrated frequency multiplier circuit 1 from the frequency output electrode 52 in response to a 0.5 Hz AC input signal (V.sub.GS) applied to the frequency input electrode 50. The input signal has a peak to peak amplitude of about 2 V, biased at about -0.5 V (i.e. biased to the Dirac point). As shown in FIG. 3, the integrated frequency multiplication circuit increases outputs a waveform which oscillates with a fundamental frequency of about 1 Hz (i.e. a frequency doubling).

[0082] In some embodiments, the second region 62 of the strip of graphene 20 having length z.sub.2 may be provided as a variable resistance. As such, in some embodiments, a resistance dielectric layer (not shown in FIGS. 1 or 4) may be provided on the strip of graphene 20, wherein the resistance dielectric layer is provided across the width x of the strip of graphene 20. The resistance dielectric layer may extend along at least some of the length y of the second region 62 of the strip of graphene. As such, the resistance dielectric layer is formed between the frequency output electrode 52 and the second end 22 of the strip of graphene 20. A variable resistance electrode (not shown in FIGS. 1 or 4) may be provided on the resistance dielectric layer, wherein the variable resistance dielectric layer is provided across the width x of the strip of graphene.

[0083] The variable resistance electrode may be provided to modulate the resistance of the graphene sheet underneath the variable resistance electrode by application of a suitable voltage to variable resistance electrode. Consequently, the resistance of the at least some of the graphene in the second region 62 of graphene sheet 20 may be controlled through application of an appropriate voltage to the variable resistance electrode. For example, a DC bias (e.g. a voltage of about no more than +/- 10 V) may be applied to the variable resistance electrode in order to modify the charge carrier density (and therefore the resistance) in the second region 62. Such voltage control may be utilised to improve the operation of the frequency multiplier circuit under different temperatures. In some embodiments, the voltage control may be utilised to control the frequency response of the integrated frequency multiplier circuit.

[0084] In some embodiments, the resistance dielectric layer and the variable resistance electrode may be formed using similar materials and processes as the dielectric layer 40 and the frequency input electrode 50 as described in further detail herein.

[0085] In some embodiments, the frequency multiplication functionality of the circuit 1 can be used to provide an AC to DC converter 2. FIG. 4 shows a schematic diagram of such a circuit, which incorporates the integrated frequency multiplier circuit 1 of the first embodiment. Components in FIG. 4 which are equivalent to the components of FIG. 1 are denoted with the same reference numerals.

[0086] The AC to DC converter circuit of FIG. 4 incorporates a capacitor 70. The capacitor 70 is connected between the frequency output electrode 52 and the first electrode 30. By including an energy storage element, rectified current waveforms (for example as shown in FIG. 3) may be smoothed out to provide a DC current.

[0087] In the embodiment of FIG. 4, the capacitor 70 may comprise a graphene capacitor formed on the substrate 10. The graphene capacitor may be formed from a first set of graphene fingers 72 and a second set of graphene fingers 74 which are interdigitated. As shown in FIG. 4, the first set of graphene fingers 72 are connect to the frequency output electrode 52 and extend towards the first electrode 30. The second set of graphene fingers 74 are connected to the first electrode 30 and extend towards the first set of graphene fingers 72. The first and second sets of graphene fingers 72, 74 extend in a generally parallel manner to each other.

[0088] As shown in FIG. 4, the first and second sets of graphene fingers are formed on the substrate 10. Each first finger 72 is spaced apart from adjacent second fingers 74 by a first spacing d. The first spacing d may be selected, in combination with the number of first and second fingers 72, 74 to define the capacitance of the capacitor.

[0089] In the embodiment of FIG. 4, the first set of graphene fingers 72 comprise three fingers and the second set of graphene fingers 74 comprises two fingers. In other embodiments, each of the first and second sets of graphene fingers 72, 74 may comprise at least 3, 5, 7, 10 or 15 fingers. As such, it will be appreciated that capacitance of the capacitor 70 may be selected based on the number of graphene fingers included, along with the spacing d.

[0090] The capacitor 70 may be connected to the frequency output electrode 52 by a third electrode extending between the frequency output electrode 52 and a first terminal of the capacitor. The capacitor may also be connected to the first electrode 30 by a fourth electrode extending between the first electrode and a second terminal of the capacitor 70. As shown in FIG. 4, the third and fourth electrodes may be provided by extending the frequency output electrode 52 and the first electrode 30 respectively in a direction transverse to the length y of the strip of graphene 20. The first and second sets of fingers 72, 74 then extend in a direction generally aligned with the length of the strip of graphene 20. As such, the capacitor 70 is provided generally adjacent to the first region 60 of the strip of graphene 20. Of course, in other embodiments, the strip of graphene may be arranged in different locations on the substrate 10.

[0091] In some embodiments, the capacitor 70 may be provided using a capacitor dielectric layer (not shown in FIG. 4). Such a capacitor 70 may comprise third and fourth electrodes connected to the frequency output electrode 52 and the first electrode 30 respectively, wherein the third and fourth electrodes are formed on the substrate such that they at least partially overlap, separated by the capacitor dielectric layer. As such, the capacitor may be formed on the substrate as a stack of layers: electrode, dielectric, electrode.

[0092] Next, a method 100 of forming the AC to DC current converter circuit of FIG. 4 will be explained. It will be appreciated that the following method may also be used to form the integrated frequency multiplier circuit 1 of FIG. 1. FIG. 5 shows a block diagram of the method 100.

[0093] In step 101, a graphene layer is deposited on a substrate using a chemical vapour process. For example, the method of WO 2017/029470 may be used to form the graphene layer as discussed above.

[0094] In step 102, the graphene layer is patterned. The patterning process may comprise the formation of a mask layer following by etching of the graphene as described above. The graphene layer is patterned to define a strip of graphene 20, the strip having a width x and a length y extending from a first end to a second end. When forming the AC to DC converter 2, the graphene layer may also be patterned to define the first and second sets of fingers 72, 74 as described above. As such, all the graphene layers for the frequency multiplier circuit 1/AC to DC converter 2 may be formed from the same graphene layer.

[0095] In step 103, the dielectric layer 40 is formed on the strip of graphene 20. The dielectric layer 40 may be formed, for example using a CVD or MOCVD process as discussed above. The dielectric layer 40 is formed on the strip of graphene wherein the dielectric layer extends across the width of the strip of graphene and along a portion of the length of the strip towards the second end. A lithographic technique may be used to form the dielectric layer 40 with the desired shape on the strip of graphene 40.

[0096] In step 104, the contacts for the circuit are formed. Step 104 comprises forming the first and second electrodes 30, 32 in electrical contact with the strip of graphene 20 at the first and second ends respectively 21, 22.

[0097] Step 104 also comprises forming the frequency input electrode 50 on the dielectric layer 40, the frequency input electrode 50 provided across the width x of the strip of graphene 20, wherein the frequency input electrode 50 is closer to the first end 21 of the strip of graphene than the second end 22. It will be appreciated that the formation of the frequency input electrode must be performed after the formation of the dielectric layer 40. Other contacts formed in step 104 may be performed at the same time as forming the frequency input electrode 50, or at a different time period, including before forming the dielectric layer 40.

[0098] Ste 104 further comprises forming the frequency output electrode 52 in electrical contact with the strip of graphene 20 at a location along the length of the strip of graphene 20 between the second electrode 32 and the frequency input electrode 50 and spaced apart from the second electrode 32.

[0099] Where the capacitor 70 is provided as part of AC to DC converter 2, third and fourth electrodes may be formed to connect the frequency output electrode 52 and the first electrode 30 to the capacitor 70.

[0100] The electrodes formed in step 104 may be formed in line with the deposition methods discussed in more detail above.

[0101] Thus, according to this disclosure an integrated frequency multiplier circuit 1 is provided. The active device of the integrated frequency multiplier circuit 1 comprises graphene. In particular, the active and passive components of the circuit are formed from a strip of graphene 20 having a defined length y and width x. The formation of the graphene strip having a precisely defined size (length y and width x) allows the properties of the frequency multiplier circuit to be tailored to the desired application.

[0102] Furthermore, it will be appreciated that integrating passive and active components using the strip of graphene provides for a circuit which is lightweight (the resistor and FET both comprising graphene) relative to frequency multiplier circuits formed from other semiconducting materials.

[0103] This disclosure also provides an AC to DC converter 2, which can be formed in an integrated manner similar to the integrated frequency multiplier circuit 1.