LEVEL SHIFTER AND INTEGRATED CIRCUIT SYSTEM INCLUDING THE SAME

Abstract

Disclosed are a circuit and a system which prevent unnecessary power consumption by cutting off static current occurring when a signal is transmitted from an integrated circuit with a low power supply voltage to an integrated circuit with a high power supply voltage.

Claims

1. A level shifter comprising: a sensing amplification unit; a transmitting switch unit; a pull-up/pull-down unit; a Schmitt trigger unit; and an inverter chain unit.

2. The level shifter of claim 1, wherein an output of the inverter chain unit is fed back to inputs of the sensing amplification unit, the pull-up/pull-down unit, and the Schmitt trigger unit.

3. The level shifter of claim 1, wherein only one of two or more switches in the transmitting switch unit is turned on according to a change in an input signal.

4. The level shifter of claim 1, wherein the sensing amplification unit is configured to have driving elements, latch elements, current source element, and load element.

5. A system, which comprises a level shifter, the system comprising: a first integrated circuit configured to use a first power supply voltage; a second integrated circuit configured to use a second power supply voltage, wherein the second integrated circuit comprises the level shifter comprising a sensing amplification unit, a pull-up/pull-down unit, a Schmitt trigger unit, and an inverter chain unit.

6. The system of claim 5, wherein an output of the inverter chain unit is fed back to inputs of the sensing amplification unit, the pull-up/pull-down unit, and the Schmitt trigger unit.

7. The system of claim 5, wherein only one of two or more switches in the transmitting switch unit is turned on according to a change in an input signal.

8. The system of claim 5, wherein the sensing amplification unit is configured to have driving elements, latch elements, current source element, and load element.

9. The system of claim 5, wherein the second power supply voltage is higher than the first power supply voltage.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0010] FIG. 1 is a view for schematically explaining a system according to the present disclosure.

[0011] FIG. 2 illustrates an embodiment according to the related art.

[0012] FIG. 3 illustrates another embodiment according to the related art.

[0013] FIG. 4 illustrates a configuration of an embodiment according to the present disclosure.

[0014] FIG. 5 illustrates a part of an operation of the configuration of the embodiment according to the present disclosure.

[0015] FIG. 6 illustrates a part of a timing diagram according to the present disclosure.

[0016] FIG. 7 illustrates another part of the operation of the configuration of the embodiment according to the present disclosure.

[0017] FIG. 8 illustrates another part of the timing diagram according to the present disclosure.

DETAILED DESCRIPTION OF THE DISCLOSURE

[0018] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings so that those with ordinary skill in the art to which the present disclosure pertains may easily carry out the embodiments. The same reference numerals refer to the same members among the reference numerals indicated in the respective drawings.

[0019] In the description of the present disclosure, the specific descriptions of publicly known related technologies will be omitted when it is determined that the specific descriptions may obscure the subject matter of the present disclosure.

[0020] The terms such as “first” and “second” may be used to describe various constituent elements, but the constituent elements should not be limited by the terms, and these terms are used only to distinguish one constituent element from another constituent element.

[0021] As schematically illustrated in FIG. 4, a level shifter 10 according to the present disclosure may be configured to include a sensing amplification unit 110, a transmitting switch unit 120, a pull-up/pull-down unit 130, a Schmitt trigger unit 140, and an inverter chain unit 150, and an input signal and an output signal are represented by IN and OUT, respectively. As is well known, according to the present disclosure, even though values of the input signal IN swing between 0 and V.sub.DDL, values of the output signal OUT are intended to swing between 0 and V.sub.DDH.

[0022] As widely known, the level shifter 10 according to the present disclosure is included in an integrated circuit (IC) using a higher power supply voltage among a plurality of integrated circuits (ICs). For example, referring to FIG. 1, more particularly, the level shifter 10 according to the present disclosure may be included in an IC2.

[0023] Hereinafter, a configuration and operation of each partial circuit will be described. First, a case in which the input signal IN transmitted from an IC1 to the level shifter 10 included in the IC2 transitions from LOW to HIGH will be described with reference to FIG. 5. In FIG. 5, elements that are turned on are represented in dark colors and elements that are turned off are represented in light colors to assist in easier understanding.

[0024] When the input signal IN transitions from LOW to HIGH, M.sub.P01, which is a switch element of the sensing amplification unit 110, is turned off, and a power supply voltage V.sub.DDH supplied to the sensing amplification unit 110 is cut off. Then, NMOS transistors M.sub.N01 and M.sub.N02, which are driving elements, are turned on to discharge a voltage of an output node SAOUT of the sensing amplification unit 110 to the ground. For reference, since a voltage value of HIGH of the input signal IN is V.sub.DDL, as described in the above problem, the switch element M.sub.P01 is not perfectly turned off, and thus there is always a possibility that some leakage current flows. Even in this case, the leakage current flow of the sensing amplification unit 110 is completely cut off by an operation in which the load elements M.sub.P02and M.sub.P03 are turned off. In this case, since gate voltages of some PMOS load transistors M.sub.P04 and M.sub.P05 change to LOW, the PMOS load transistors M.sub.P04 and M.sub.P05 are turned on, and the voltage of the output node SAOUT of the sensing amplification unit 110 is latched and maintained with being discharged to the ground.

[0025] The sensing amplification unit 110 is configured to have driving elements M.sub.N01 and M.sub.N02, latch elements M.sub.N03, M.sub.N04, M.sub.P04, and M.sub.P05, switch element M.sub.P01 and load elements M.sub.P02 and M.sub.P03.

[0026] When the input signal IN is LOW, that is, just before the input signal IN transitions from LOW to HIGH, switches SW.sub.0 and SW.sub.1 of the transmitting switch unit 120 are in turned-on and turned-off states, respectively, and a switch SW.sub.2 of the Schmitt trigger unit 140 is in a turned-on state. Since the LOW state of the input signal IN, that is, a ground voltage Vss, is transmitted to two inputs INN and INP of the Schmitt trigger unit 130 in advance by the operation of these switches. Therefore, an output of the Schmitt trigger unit 140 is in a HIGH state, and two outputs Q and QB of the inverter chain unit 150 are in LOW and HIGH states, respectively. Of course, accordingly, the output signal OUT of the level shifter 10 maintains a LOW state.

[0027] For reference, a drawing just before the transition of the input signal IN from LOW to HIGH may be easily understood by partially referring to the turned-on and turned-off states illustrated in FIG. 7.

[0028] Since the switches SW.sub.0 and SW.sub.1 of the transmitting switch unit 120 will maintain turned-on and turned-off states, respectively, immediately after the input signal IN transitions from LOW to HIGH, the two input signals INN and INP of the Schmitt trigger unit 140 start to be charged toward the V.sub.DDL value, which is the HIGH value of the input signal IN through the switches SW.sub.0 and SW.sub.2, and M.sub.P07 and M.sub.P09 elements positioned on a charging path of the Schmitt trigger unit 140 are turned off and cut off the charging path according to the charging of the input signal INP.

[0029] Then, according to the charging of the input signal INN, M.sub.N07 and M.sub.N09 elements positioned in a discharging path of the Schmitt trigger unit 140 are turned on, and the output of the Schmitt trigger unit 140 starts to be discharged. Each output of the inverter chain unit 150 sequentially transitions from the previous state, the Q and QB signals change to HIGH and LOW, respectively, and the output OUT of the level shifter 10 becomes HIGH.

[0030] The Q and QB signals of the inverter chain unit 150 are fed back, so that the states of the switches SW.sub.0 and SW.sub.1 of the transmitting switch unit 120 are changed to turned-off and turned-on states, respectively. As an M.sub.P06 element in a pull-up path of the pull-up/pull-down unit 130 is turned on, the INP, which is an input node of the Schmitt trigger unit 140, continues to be charged, in this case, with the V.sub.DDH value transmitted from the pull-up/pull-down unit 130. The switch SW.sub.2 of the Schmitt trigger unit 140 is cut off by the QB signal fed back, and the INP node and the INN node are separated.

[0031] It should be noted that the input node INP of the Schmitt trigger unit 140 is charged with the V.sub.DDH value, whereas another input node INN of the Schmitt trigger unit 140 is charged with the V.sub.DDL value, which is transmitted from the input signal IN of the level shifter 10.

[0032] Next, a case in which the input signal IN transmitted from the IC1 to the level shifter 10 included in the IC2 transitions from HIGH to LOW will be described with reference to FIG. 7. In FIG. 7, elements that are turned on are represented in dark colors and elements that are turned off are represented in light colors to assist in easier understanding.

[0033] The switch element M.sub.P01 of the sensing amplification unit 110 directly connected to the input signal IN is turned on immediately after the input signal IN transitions from HIGH to LOW, and the power supply voltage V.sub.DDH starts to be supplied to the sensing amplification unit 110. Then, the two driving transistors M.sub.N01 and M.sub.N02 are turned off, and a PMOS element M.sub.P10 of the pull-up/pull-down unit 130 is turned on.

[0034] The input node INN of the Schmitt trigger unit 140 connected to the input signal IN through the switch SW.sub.1 of the transmitting switch unit 120 also starts to be discharged. Another input node INP of the Schmitt trigger unit 140 is slowly discharged from V.sub.DDH through discharging paths of an M.sub.N05 element maintaining the previous turned-on state and the newly turned-on M.sub.P10 element in the pull-up/pull-down unit 130.

[0035] Therefore, the M.sub.P03 element of the sensing amplification unit 110 is turned on and starts to charge the SAOUT node, which is an output node. Thus, the charging of the SAOUT node is accelerated by the positive feedback effect of the four transistors M.sub.P04, M.sub.P05, M.sub.N03, and M.sub.N04 that form a latch structure in the sensing amplification unit 110.

[0036] As a voltage of the SAOUT node changes to V.sub.DDH, an M.sub.N06 element of the pull-up/pull-down unit 130 is turned on, and the INP node is discharged. The above process is further accelerated to turn on the charging transistors M.sub.P07 and M.sub.P09 of the Schmitt trigger unit 140, and thus the output of the Schmitt trigger unit 140 is rapidly charged to V.sub.DDH and the state thereof is changed. Each output of the inverter chain unit 150 sequentially transitions from the previous state, the Q and QB signals change to LOW and HIGH, respectively, and the output OUT of the level shifter 10 becomes LOW.

[0037] As the Q and QB signals of the inverter chain unit 150 are fed back, the states of the switches SW.sub.0 and SW.sub.1 of the transmitting switch unit 120 are changed to the turned-on and turned-off states, respectively, and the INN node of the Schmitt trigger unit 140, which started to be discharged according to the input signal IN, completes the discharging to the ground voltage Vss according to the INP as the switch SW.sub.2 is turned on.

[0038] For the summary of the above operations, a timing diagram for the input signal IN, the two inputs INN and INP of the Schmitt trigger unit 130, the output SAOUT of the sensing amplification unit, and the output OUT of the level shifter 10 is illustrated in FIG. 8.

[0039] In the operation of each circuit constituting the level shifter according to the present disclosure, there is no power loss due to the static current since all the static current paths from the power supply voltage V.sub.DDH to the ground are also cut off in this case.

[0040] For the summary of the above operations, a timing diagram for the two inputs INN and INP of the Schmitt trigger unit 130, the output SAOUT of the sensing amplification unit, and the output OUT of the level shifter 10 is illustrated in FIG. 6. For reference, the parts represented by Phase1 and Phase2 in the timing diagram mean a transition period and a stabilized period after the transition is completed, respectively.

[0041] Therefore, in the operation of each circuit constituting the level shifter 10 according to the present disclosure, there is no power loss due to the static current since all the static current paths from the power supply voltage V.sub.DDH to the ground are cut off.

[0042] When a signal is transmitted from the integrated circuit IC1 with a low power supply voltage to the integrated circuit IC2 with a high power supply voltage, the unnecessary consumption of static current may be prevented according to the system in which the level shifter 10 according to the present disclosure is included as an input circuit of the integrated circuit IC2 with a high power supply voltage. In addition, there is an advantage in that malfunction caused by the flow of static current may be prevented.

[0043] While the present disclosure has been described with reference to the embodiments illustrated in the drawings, the embodiments are for illustrative purposes only, and those skilled in the art to which the present disclosure pertains will understand that various modifications of the embodiment and any other embodiment equivalent thereto are available. Accordingly, the true technical protection scope of the present disclosure should be determined by the technical spirit of the appended claims.