SLOPE ANALOG-TO-DIGITAL CONVERTER, A SYSTEM AND A METHOD FOR CONVERTING AN ANALOG INPUT SIGNAL TO A DIGITAL REPRESENTATION

Abstract

A slope analog-to-digital converter, ADC, for converting an analog input signal to a digital representation, said slope ADC comprising: a comparator configured to compare two input signals, wherein a sampled value of the analog input signal and a slope signal are used in forming the two input signals; a memory element, which is configured to receive a trigger signal based on the comparator identifying a change in which of the two input signals is higher, and a counter signal, wherein a value of the counter signal when the trigger signal is received provides the digital representation of the sampled value of the analog input signal; wherein the slope signal and the counter signal have a nonlinear relationship, wherein the nonlinear relationship is adapted to improve linearity of a transfer function of the slope ADC for converting the analog input signal to the digital representation.

Claims

1. A slope analog-to-digital converter, ADC, for converting an analog voltage input signal to a digital representation, said slope ADC comprising: a comparator configured to compare two input signals, wherein a sampled value of the analog voltage input signal and a slope signal are used in forming the two input signals; a memory element, which is configured to receive a trigger signal based on the comparator identifying a change in which of the two input signals is higher, and a counter signal, wherein a value of the counter signal when the trigger signal is received provides the digital representation of the sampled value of the analog voltage input signal; wherein the slope signal and the counter signal have a nonlinear relationship, wherein the nonlinear relationship is adapted to compensate for a nonlinearity in processing of the analog voltage input signal.

2. The slope ADC according to claim 1, further comprising an input unit comprising a sampling capacitor, wherein the input unit is configured to receive the analog voltage input signal and hold the sampled value of the analog voltage input signal on the sampling capacitor, wherein the adaptation of the nonlinear relationship of the slope signal and the counter signal includes a compensation for a nonlinear relation between the analog voltage input signal and the sampled value held by the sampling capacitor.

3. The slope ADC according to claim 1, wherein the slope signal is configured to vary between a minimum value and a maximum value, wherein the slope signal is monotonically increasing or monotonically decreasing between the minimum value and the maximum value.

4. The slope ADC according to claim 3, wherein the slope signal is nonlinear in relation to time during monotonical increase or monotonical decrease.

5. The slope ADC according to claim 1, wherein the counter signal is nonlinear in relation to time.

6. The slope ADC according to claim 1, wherein said two input signals are the sampled value of the analog voltage input signal and the slope signal such that the comparator is configured to compare the sampled value of the analog voltage input signal and the slope signal.

7. The slope ADC according to claim 1, wherein the nonlinear relationship between the slope signal and the counter signal is based on a calibration of a nonlinear transfer function of the slope ADC for converting the analog voltage input signal to the digital representation.

8. The slope ADC according to claim 7, wherein the slope signal is based on a linear monotonically increasing or monotonically decreasing signal in combination with a nonlinear signal based on said calibration.

9. A system for analog-to-digital conversion of analog voltage input signals, wherein the system comprises a plurality of slope ADCs according to claim 1.

10. The system according to claim 9, wherein the system comprises a common slope signal generator and a common counter signal generator, such that the plurality of slope ADCs receive the same slope signal and the same counter signal.

11. The system according to claim 10, wherein the nonlinear relationship between the slope signal and the counter signal is adapted to improve an average error of transfer functions of the plurality of slope ADCs.

12. The system according to claim 9, wherein the system comprises a time-interleaved arrangement for providing a single analog voltage input signal to the plurality of slope ADCs, wherein the nonlinear relationship of the slope signal and the counter signal is configured to compensate for nonlinearity of the time-interleaved arrangement.

13. The system according to claim 9, wherein the system is configured to receive a single analog voltage input signal and the plurality of slope ADCs are configured to sample the single analog voltage input signal successively in time for forming a time-interleaved analog-to-digital converter.

14. A method for converting an analog voltage input signal to a digital representation, said method comprising: comparing by a comparator two input signals, wherein a sampled value of the analog voltage input signal and a slope signal are used in forming the two input signals, wherein a trigger signal is output by the comparator upon identifying a change in which of the two input signals is higher; receiving by a memory element a counter signal and the trigger signal, and determining by the memory element a value of the counter signal when the trigger signal is received as the digital representation of the sampled value of the analog voltage input signal, wherein the slope signal and the counter signal have a nonlinear relationship, wherein the nonlinear relationship is adapted to compensate for a nonlinearity in processing of the analog voltage input signal.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0072] The above, as well as additional objects, features, and advantages of the present inventive concept, will be better understood through the following illustrative and non-limiting detailed description, with reference to the appended drawings. In the drawings like reference numerals will be used for like elements unless stated otherwise.

[0073] FIG. 1 is a schematic view of a slope analog-to-digital converter (ADC) according to an embodiment.

[0074] FIG. 2 is a schematic view of a system of slope ADCs according to an embodiment forming a time-interleaved ADC.

[0075] FIG. 3 is a schematic timing diagram of signals of the time-interleaved ADC.

[0076] FIG. 4 is an output spectrum of a time-interleaved ADC with a simulated harmonic distortion.

[0077] FIG. 5 is a schematic view of graphs for forming a nonlinear slope voltage for compensating for nonlinearities in a slope ADC.

[0078] FIG. 6 is an output spectrum corresponding to FIG. 4 for a slope signal with nonlinearity compensation.

[0079] FIG. 7 is a graph illustrating fitting a nonlinearity compensation to nonlinear errors of a plurality of slope ADCs.

[0080] FIG. 8 is a schematic view of a slope signal generator and a counter signal generator.

[0081] FIG. 9 is a schematic view of calibration of a slope ADC according to a first embodiment.

[0082] FIG. 10 is a schematic view of calibration of a slope ADC according to a second embodiment.

[0083] FIG. 11 is a flowchart of a method according to an embodiment.

DETAILED DESCRIPTION

[0084] Referring now to FIG. 1, a slope analog-to-digital converter (ADC) 100 according to an embodiment will be described.

[0085] The slope ADC 100 may comprise an input unit 102 which is configured to receive an analog input signal. The input unit 102 may comprise a sampling capacitor 104, which is configured to receive the analog input signal. The analog input signal may be a voltage signal, such that the potential of a terminal of the sampling capacitor 104 may track the analog input signal when the sampling capacitor 104 is connected to receive the analog input signal and may hold (store) a value of the analog input signal when the sampling capacitor 104 is disconnected from the analog input signal. The input unit 102 may thus form a track and hold unit, but it should be realized that the input unit 102 may alternatively form a sample and hold unit.

[0086] The slope ADC 100 may receive a single-ended analog input signal V.sub.in. In such case, the sampling capacitor 104 may be configured to receive the analog input signal on a first terminal 106 of the sampling capacitor 104, while the second terminal 108 of the sampling capacitor 104 may be connected to a fixed reference voltage, such as ground.

[0087] However, according to an alternative, the analog input signal may be a differential analog input signal comprising a first analog input signal and a second analog input signal. The differential analog input signal may be connected to the sampling capacitor 104 such that the sampling capacitor 104 receives the first analog input signal on the first terminal 106 of the sampling capacitor 104 and receives the second analog input signal on the second terminal 108 of the sampling capacitor 104. This implies that the sampling capacitor 104 is configured to track and hold the differential input signal across the sampling capacitor 104 between the first terminal 106 and the second terminal 108.

[0088] The input unit 104 may comprise a sampling switch 110, which may be configured to selectively connect the analog input signal to the first terminal 106 of the sampling capacitor 104. The sampling switch 110 may thus be active to connect the analog input signal to the sampling capacitor 106 and allow sampling of the analog input signal to obtain a sampled value Vs of the analog input signal on the sampling capacitor 106. The sampling switch 110 may then be inactive disconnecting the analog input signal from the sampling capacitor 104.

[0089] The slope ADC 100 further comprises a comparator 120. The comparator 120 is configured to compare two input signals involving the sampled value of the analog input signal and a slope signal V.sub.slope. The slope signal may have a monotonically increasing or monotonically decreasing value between a minimum value and a maximum value of the slope signal. The comparator 120 in the slope ADC 100 shown in FIG. 1 is configured to directly compare the sampled value and the slope signal, but it should be realized that a comparison of signal values involving the sampled value and the slope signal may be set up in different ways. For instance, the sampled value of the analog input signal may be combined with the slope signal forming a combined signal. The comparator 120 may be configured to compare the combined signal with a fixed reference signal.

[0090] Input to the comparator 120 may comprise a first terminal 122 and a second terminal 124. The comparator 120 may be configured to provide an output which may toggle between two values depending on whether a signal level received at the first terminal 122 or the second terminal 124 is larger. When the sampled value of the analog input signal is directly compared to the slope signal, a toggling of the output by the comparator 120 thus implies that a value of the slope signal crosses the sampled value of the analog input signal.

[0091] The slope ADC 100 further comprises a memory element 130. The memory element 130 may for instance be a flip flop or latch circuit. The memory element 130 is configured to receive a counter signal counter that may be synchronized with the slope signal. It should be realized that FIG. 1 for brevity and simplicity only shows one flip flop, but as would be understood by a person skilled in the art, if the counter signal has X bits, the memory element 130 comprises X flip flops.

[0092] The memory element 130 may further be configured to receive the output from the comparator 120. A toggling of the output by the comparator 120 may trigger that a counter value from the counter signal is read into the memory element 130 (e.g., the flip flop or latch circuit).

[0093] The memory element 130 may comprise an input 132 for receiving a trigger signal. The input 132 of the memory element 130 may receive a signal which may assume to different levels, representing a 0 or 1. The memory element 130 may be directly connected to the output by the comparator 120 such that the output by the comparator 120 is received at the input 132 of the memory element 130. Alternatively, the output by the comparator 120 may be further processed before reaching the memory element 130. For instance, the slope ADC 100 may comprise an XOR gate which conditionally inverts an output by the comparator 120 so that the trigger signal to the memory element 130 is always received based on a change in the output of the comparator at a rising edge (or a falling edge) of the output of the comparator.

[0094] The memory element 130 may further comprise a data input 134 which is configured to receive the counter signal. The memory element 130 may be configured to hold a constant data value as long as the signal received on the input 132 does not change. When the signal received on the input 132 changes, the memory element 130 reads a value of the counter signal so as to change the data value held by the memory element 130. The memory element 132 may further comprise an output 136, which outputs the data value held by the memory element 130.

[0095] The memory element 130 may be implemented as a latch circuit such that the memory element 130 may be configured as a compact and power-efficient element. However, it should be realized that the memory element 130 may be implemented in other ways, such as using any kind of static random access memory.

[0096] The memory element 130 may be configured to store the value of the counter signal at the time the trigger signal is received by the memory element 130. The value of the counter signal provides a digital representation of the sampled value of the analog input signal. The output from the memory element 130 may thus provide the digital representation of the sampled value of the analog input signal as an output from the slope ADC 100.

[0097] The relationship between the slope signal and the counter signal may be expressed as a function mapping one signal onto the other signal, expressing the counter signal as a function of the slope signal or vice versa. It should be realized that both the slope signal and the counter signal vary with time and that the function maps one signal at a particular point in time to the other signal at the same particular point in time.

[0098] The output of the comparator 120 may toggle when the slope signal assumes a value that corresponds to the sampled value of the analog input signal. In response, the trigger signal is received by the memory element 130 controlling timing of reading of the value of the counter signal into the memory element 130.

[0099] The slope ADC 100 may have a transfer function, which defines the digital representation output by the slope ADC 100 as a function of the analog input signal input to the slope ADC 100. A linear transfer function of the slope ADC 100 implies that values of the digital representation can be expressed by a linear function of the values of the analog input signal, i.e., a function whose graph is a straight line. However, if processing of the analog input signal in the slope ADC exhibits nonlinearities, i.e., the analog input signal is not processed in the same manner if the value of the analog input signal changes, the digital representation output by the slope ADC 100 is affected.

[0100] According to the inventive concept, a nonlinear relationship between the slope signal and the counter signal is used. The nonlinear relationship between the slope signal and the counter signal is set so as to compensate for any nonlinearities in processing of the analog input signal by the slope ADC 100 such that the transfer function of the slope ADC 100 becomes closer to a straight line compared to if a linear relationship between the slope signal and the counter signal would be used.

[0101] The nonlinear relationship between the slope signal and the counter signal may be configured for providing a linear transfer function of the slope ADC. However, it should be realized that nonlinearities of the slope ADC 100 may not be perfectly compensated for, such that the nonlinear relationship between the slope signal and the counter signal may be configured to improve linearity of the transfer function of the slope ADC 100.

[0102] The slope signal may be configured to be monotonically increasing or monotonically decreasing between a minimum value and a maximum value of the slope signal. Thus, the slope signal may be monotonically increasing from a minimum value to a maximum value. Alternatively, the slope signal may be monotonically decreasing from a maximum value to a minimum value.

[0103] The slope signal may be nonlinear in relation to time, such that an increase rate or decrease rate of the slope signal is not constant during the monotonical increasing or monotonical decreasing, respectively. The slope signal may be configured to increase/decrease in steps and having a constant value therebetween, which inherently means that the slope signal will be nonlinear in relation to time.

[0104] However, the slope signal may further be configured to have a varying period between time steps or a varying height of the voltage steps, adding further nonlinearity of the slope signal.

[0105] The counter signal may be configured to provide a sequence of digital values, the digital values in the sequence being monotonically increasing or monotonically decreasing. The counter signal may be configured to increase or decrease at least a least significant bit of the digital value between subsequent values in the sequence, i.e., increasing or decreasing the digital value by 1.

[0106] The counter signal may be nonlinear in relation to time. This implies that a timing of a change of the counter signal may vary with time or that a change in the digital value of the counter signal between subsequent values in the sequence may vary with time.

[0107] The counter signal may be generated based on a clock frequency, such that the digital value of the counter signal may increase or decrease with each period of a clock signal. The counter signal may be nonlinear in relation to time by the clock frequency controlling the counter signal being varied. According to an alternative, the counter signal may be nonlinear in relation to time by the changing of the digital value of the counter signal being based on different number of periods of the clock signal, such as the counter signal being changed after 1 period, 2 periods, etc. of the clock signal.

[0108] Since the slope signal and the counter signal have a nonlinear relationship, the slope signal and the counter signal will not vary with time in the same manner. As mentioned above, the slope signal may be nonlinear in relation to time. Also, the counter signal may be nonlinear in relation to time. It should be realized that at least one of the slope signal or the counter signal is nonlinear in relation to time in order for the slope signal and the counter signal to have a nonlinear relationship. Thus, the slope signal may be nonlinear in relation to time, while the counter signal is linear in relation to time. Alternatively, the counter signal may be nonlinear in relation to time, while the slope signal is linear in relation to time. According to yet another alternative, the slope signal and the counter signal are both nonlinear in relation to time, but not in the same manner, such that the slope signal and the counter signal have a nonlinear relationship.

[0109] Many different causes of nonlinear processing of the analog input signal in the slope ADC 100 may be conceived. In a relatively simple slope ADC 100 as illustrated in FIG. 1, sampling of the analog input signal onto the sampling capacitor 104 may be a cause of a nonlinear effect on the sampled value of the analog input signal. Thus, the nonlinear relationship of the slope signal and the counter signal may be adapted to compensate for a nonlinear relation between the analog input signal and the sampled value held by the sampling capacitor 104.

[0110] However, it should be realized that nonlinear effects on the sampled value of the analog input signal may have other causes. The nonlinear relationship of the slope signal and the counter signal may be used to compensate for any nonlinear effect, regardless of its cause.

[0111] Referring now to FIG. 2, a system 200 for analog-to-digital conversion of analog input signals will be described. The system 200 comprises a plurality of slope ADCs, such as a plurality of slope ADCs 100 as described above. The system 200 in FIG. 2 illustrates a time-interleaved ADC 200.

[0112] The plurality of slope ADCs 100 may be arranged in parallel in order to achieve a plurality of parallel analog-to-digital conversion channels. The time-interleaved ADC 200 may comprise common input nodes 202 for receiving the analog input signal. For simplicity, only a single input node 202 is shown, but it should be realized that two input nodes may be used for receiving a differential analog input signal.

[0113] The time-interleaved ADC 200 may further comprise an input buffer 242, which is configured to receive the analog input signal from the input node 202. The input buffer 242 may be used for converting an impedance from a source of the analog input signal to a low value so that input impedance of the time-interleaved ADC 200 does not significantly affect the analog input signal.

[0114] The input buffer 242 may be implemented using a source follower circuit but it should be realized that other alternatives, such as using operational amplifiers, may be used.

[0115] The plurality of slope ADCs 100 may be connected to the common input node 202 via a time-interleaved sampling arrangement 250. The time-interleaved sampling arrangement 250 is configured to successively in time provide the analog input signal to each of the plurality of slope ADCs 100. The sampling arrangement 250 may thus provide a sampling network which provides sampling of a single analog input signal to the plurality of slope ADCs 100. Each of the slope ADCs 100 may thus obtain a sampled value of the analog input signal such that different slope ADCs 100 obtain sampled values representing the analog input signal at different points in time. This allows that plurality of ADCs 100 to be jointly used for increasing the sampling rate of the time-interleaved ADC 200.

[0116] The digital representation provided by each of the plurality of slope ADCs 100 may be output to a data aligner 260 which may combine the digital representation of the analog input signal from the plurality of slope ADCs 100 to form a combined sequence of digital values forming a complete digital representation of the analog input signal.

[0117] Referring now to FIG. 3, time-interleaving of sampling of the analog input signal will be discussed in relation to an exemplary timing diagram of the time-interleaved ADC 200.

[0118] The timing diagram illustrates three time-interleaved channels, channels 1, 2, . . . , L, in the time-interleaved ADC 200. Each of the channels is represented by a 4-bit slope ADC 100, enabling conversion of a sampled value of the analog input signal to a 4-bit digital representation.

[0119] For each channel k, a signal (ϕ.sub.k to the sampling switch 110, the common slope signal V.sub.slope, the sampled value of the analog input signal V.sub.i, and the output comp.sub.k from the comparator 120 is illustrated. The analog input signal V.sub.iis sampled at different moments in time in the different channels by the time-interleaved sampling arrangement 250, resulting in a sampled input signal V.sub.i,k(k=1, 2, . . . , L) in the respective channels.

[0120] A common slope signal V.sub.slope may be shared for all the channels. Thus, a single slope signal may be generated, which implies that a common slope signal generator 270 may be used for all of the plurality of slope ADCs 100, providing a compact time-interleaved ADC 200.

[0121] The slope signal may be a monotonically increasing signal. As illustrated in FIG. 3, the slope signal may be nonlinear in relation to time. However, the same slope signal may be provided to each of the plurality of slope ADCs 100.

[0122] The slope signal may have a rise time T.sub.rise and a fall time T.sub.fall to reset the slope signal. The slope signal thus exhibits a slope repetition with a period T.sub.slope defined by: T.sub.slope=T.sub.rise+T.sub.fall.

[0123] The time-interleaved ADC 200 may provide an overall sampling frequency F.sub.s, which may be distributed on L interleaved channels such that each interleaved channel operate on a frequency L times lower than the overall sampling frequency F.sub.s. Each channel is thus provided with a conversion time corresponding to L*F.sub.s. The analog-to-digital conversion of each channel involves sampling of the analog input signal during a period T.sub.track, at which the signal to the sampling switch (ϕ.sub.k is high and the analog input signal is tracked by the sampling capacitor 104, and hold time T.sub.hold during which the sampled value of the analog input signal is held by the sampling capacitor 104 and the sampled value is provided to the comparator 120 for converting the sampled value to a digital representation.

[0124] The slope repetition period T.sub.slope should be smaller than the hold time T.sub.hold for correct operation. When a common slope signal is used for all the slope ADCs 100, the timing of the period T.sub.hold may not align with a complete rising slope of the slope signal. However, thanks to the slope repetition period T.sub.slope being smaller than the hold time T.sub.hold, the slope signal may during the hold time T.sub.hold assume all possible values between the minimum value and the maximum value at least once, although not necessarily in one consecutive monotonic rising slope. Rather, the slope signal may assume a first sub-range of the values in a first slope and may assume a second sub-range of the values in a second slope.

[0125] The counter signal D.sub.CNTR illustrated in section (d) of FIG. 3 may also be common to all of the plurality of ADCs 100. Thus, a single counter signal may be generated, which implies that a common counter signal generator 272 may be used for all of the plurality of slope ADCs 100, providing a compact time-interleaved ADC 200.

[0126] The memory element 130 of each channel may receive the common counter signal and may read in the value of the counter signal upon receiving a trigger signal. The trigger signal may be provided when the rising slope of the slope signal crosses the sampled value of the analog input signal. Since the slope repetition period T.sub.slope is smaller than the hold time T.sub.hold, the slope signal will cross the sampled value of the analog input signal at least once.

[0127] The digital representation provided by each of the plurality of slope ADCs 100 may be output to the data aligner 260 which may re-sample the output from the plurality of slope ADCs such that the output from the data aligner 260 is synchronous with the overall sampling frequency F.sub.s.

[0128] In section (a) of FIG. 3, the digital-to-analog conversion of channel 1 is illustrated. The first conversion 301 of channel 1 resembles a conversion of a conventional slope ADC, wherein the slope signal is monotonously increasing from the minimum value to the maximum value during the hold time T.sub.hold. The signal comp, from the comparator 120 changes sign when the slope signal V.sub.slope crosses the sampled value of the analog input signal V.sub.i, 1 at the first conversion 301 and the corresponding value “9” of the counter signal is read into the memory element 130. In the second conversion 302, the slope signal does not start at the minimum value when the hold time begins. Nevertheless, the slope signal is smaller than the sampled value of the analog input signal when the hold time begins and the signal comp.sub.1 from the comparator 120 changes sign when the slope signal V.sub.slope crosses the sampled value of the analog input signal V.sub.i, 1 at the second conversion 302 and the corresponding value “13” of the counter signal is read into the memory element 130. In the third conversion, the slope signal V.sub.slope crosses the sampled value of the analog input signal V.sub.i, 1 during the track period at a third conversion 303 providing an incorrect determination of the counter signal into the memory element. However, during the hold time, the signal comp.sub.1 from the comparator 120 changes sign when the slope signal V.sub.slope again crosses the sampled value of the analog input signal V.sub.i,1 at the fourth conversion 304 and the corresponding, correct value “4” of the counter signal is read into the memory element 130, overwriting the previously read, incorrect value.

[0129] In section (b) of FIG. 3, the digital-to-analog conversion of channel 2 is illustrated. In the first conversion 305 of channel 2, the slope signal is higher than the sample value when the hold time begins. The slope signal thus increases to its maximum value without the comparator 120 changing sign. Then, the slope signal is reset to its minimum value and the signal comp.sub.2 from the comparator 120 changes sign when the slope signal V.sub.slope crosses the sampled value of the analog input signal V.sub.i, 1 at the first conversion 305 and the corresponding value “6” of the counter signal is read into the memory element 130. In the second conversion 306, the slope signal again is higher than the sample value when the hold time begins. After reset of the slope signal, the signal comp.sub.2 from the comparator 120 changes sign when the slope signal V.sub.slope crosses the sampled value of the analog input signal V.sub.i, 1 at the second conversion 306 and the corresponding value “13” of the counter signal is read into the memory element 130. In the third conversion, the signal comp.sub.2 from the comparator 120 changes sign when the slope signal V.sub.slope crosses the sampled value of the analog input signal V.sub.1,2 at the third conversion 307 and the corresponding value “4” of the counter signal is read into the memory element 130.

[0130] In section (c) of FIG. 3, the digital-to-analog conversion of channel L is illustrated. In the first conversion 308 of channel L, the signal comp.sub.L from the comparator 120 changes sign when the slope signal V.sub.slope crosses the sampled value of the analog input signal V.sub.i,L at the first conversion 308 and the corresponding value “13” of the counter signal is read into the memory element 130. In the second conversion 309, 310, the signal comp.sub.L from the comparator 120 changes sign when the slope signal V.sub.slope crosses the sampled value of the analog input signal V.sub.i,L at the conversion 309 and the corresponding value “4” of the counter signal is read into the memory element 130. Then, after reset of the slope signal, the signal comp.sub.L from the comparator 120 again changes sign when the slope signal V.sub.slope crosses the sampled value of the analog input signal V.sub.i,L at the conversion 310 and the corresponding value “4” of the counter signal is again read into the memory element 130.

[0131] Referring again to FIG. 2, the time-interleaved sampling arrangement 250 may be configured to provide a hierarchical sampling arrangement, wherein sampling in at least two hierarchical levels is provided. The plurality of slope ADCs 100 may be arranged in a two-dimensional array in columns and rows and the hierarchical sampling arrangement may be configured to implement time-interleaving of the analog input signal over the rows of the array and over the columns of the array.

[0132] The hierarchical sampling arrangement 250 may split the analog input signal in N channels for N rows of the array. The input signal may thus be sampled by one of N interleaved sampling clocks at a frequency of F.sub.sIN. The signals from this sampling may be distributed to the channels in each row and may each be further split into M channels. Each of the plurality of slope ADCs 100 may thus sample the analog input signal using interleaved sampling clocks at a frequency of F.sub.sI(N*M).

[0133] This two-dimensional arrangement of the slope ADCs 100 is a convenient way to time-interleave a large number of N×M slope ADC channels in a limited area.

[0134] The signals from the sampling through the hierarchical sampling arrangement may be distributed to the plurality of slope ADCs 100 through a buffered path. The sampling network may introduce nonlinear effects on the processing of the analog input signal, for instance, through the analog input signal being passed through a buffered path. Thus, the nonlinear relationship of the slope signal and the counter signal may be adapted to compensate for any nonlinearity on the analog input signal caused by the sampling network.

[0135] Although the system 200 is described above as providing a time-interleaved ADC, it should be realized that a system comprising a plurality of slope ADCs may alternatively be used for analog-to-digital conversion of a plurality of different analog input signals. Thus, the system may be configured to receive a plurality of analog input signals, and each slope ADC may be configured to receive a unique analog input signal among the plurality of analog input signals. The system may still be configured to use the same slope signal and the same counter signal by all of the plurality of slope ADCs, such that a compact and power-efficient system is provided.

[0136] The use of the nonlinear relation between the slope signal and the counter signal will now be discussed in more detail.

[0137] The slope signal and the counter signal have a nonlinear relationship, which may be used for compensating static nonlinearities. The static nonlinearities may occur in the input path for passing the analog input signal to an input terminal of the comparator 120.

[0138] The analog input signal V.sub.in may be mapped onto a signal at the input terminal of the comparator 120 via a function f(V.sub.in) which has a linear part, f.sub.linear(V.sub.in) and a nonlinear part, f.sub.nonlinear(V.sub.in). Thus, the signal V.sub.s at the input terminal of the comparator may be defined as:

V.sub.s=f(V.sub.in)=f.sub.linear(V.sub.in)+f.sub.nonlinear(V.sub.in)=m×V.sub.in+V.sub.0+f.sub.nonlinear(V.sub.in),

where m, V.sub.0 are scalars, wherein m defines a slope of the linear function and V.sub.0 defines an offset, i.e., a value of the signal V.sub.s when the analog input signal is zero.

[0139] If the comparator 120 compares the signal V.sub.s directly to the slope signal, the comparator 120 toggles when the slope signal V.sub.slope gets equal to V.sub.s. The corresponding value of the counter signal at that moment provides a result of the comparison, as a digital representation of the sampled value of the analog input signal.

[0140] If the slope signal V.sub.slope varies linearly with time t of conversion (toggling of the comparator 120), the slope signal V.sub.slope may be defined as:

[00001]$V_{\mathrm{slope}}\left(t\right)=\frac{V_{\mathrm{step}}}{t_{\mathrm{step}}}t+V_{\mathrm{start}},$

where t.sub.step is a time between subsequent changes of a value of the counter signal, V.sub.step is a size of a change of the slope signal during t.sub.step, and V.sub.start is a value of the slope signal corresponding to the counter signal being 0.

[0141] As mentioned above, in a time-interleaved ADC 200, the slope signal is not necessarily 0 at beginning of conversion of the sampled value of the analog input signal. However, when the slope signal is reset, t starts again at 0 and the definition of V.sub.slope above remains valid.

[0142] Further, if the counter signal counter also varies linearly with time t, the counter signal may be defined as:

[00002]$\mathrm{counter}=\frac{t}{t_{\mathrm{step}}}.$

[0143] Based on the above, a relation may be defined for a value of the analog input signal V.sub.in=X and the digital number DN output by the slope ADC corresponding to a value read into the memory element 130 when the slope signal V.sub.slope equals the sampled value V.sub.s of the analog input signal:

m×X+V.sub.0+f.sub.nonlinear(X)=DN×V.sub.step+V.sub.start,

which may be rewritten as:

[00003]$\mathrm{DN}=\frac{m}{V_{\mathrm{step}}}X+\frac{V_0-V_{\mathrm{start}}}{V_{\mathrm{step}}}+\frac{f_{\mathrm{nonlinear}}\left(X\right)}{V_{\mathrm{step}}}.$

[0144] According to the present inventive concept, the slope signal and the counter signal have a nonlinear relationship configured to compensate for the nonlinear part f.sub.nonlinear(X) so as to improve linearity of a transfer function between the analog input signal and the output digital representation.

[0145] According to an embodiment, the slope signal V.sub.slope may be provided with a nonlinear part g.sub.nonlinear such that the slope signal is nonlinear in relation to time. The nonlinear part g.sub.nonlinear may be expressed as a function of t l t.sub.step, where t.sub.step is merely a constant value. Then, the slope signal may be defined as:

[00004]$V_{\mathrm{slope}}=\frac{V_{\mathrm{step}}}{t_{\mathrm{step}}}t+V_{\mathrm{start}}+g_{\mathrm{nonlinear}}\left(\frac{t}{t_{\mathrm{step}}}\right),$

which may be written as:

[00005]$V_{\mathrm{slope}}=\frac{V_{\mathrm{step}}}{t_{\mathrm{step}}}t+V_{\mathrm{start}}+g_{\mathrm{nonlinear}}\left(\mathrm{counter}\right).$

[0146] The digital number DN output for the analog input signal V.sub.in=X may now be expressed as:

[00006]$\mathrm{DN}=\frac{m}{V_{\mathrm{step}}}X+\frac{V_0-V_{\mathrm{start}}}{V_{\mathrm{step}}}+\frac{f_{\mathrm{nonlinear}}\left(X\right)-g_{\mathrm{nonlinear}}\left(\mathrm{DN}\right)}{V_{\mathrm{step}}}.$

[0147] Thus, if the nonlinear part g.sub.nonlinear of the slope signal corresponds to the nonlinear part of the function f, the nonlinear terms cancel out and the slope ADC 100 provides a linear transfer function for converting the analog input signal to the digital representation.

[0148] Referring now to FIGS. 4-6, use of a nonlinear relationship between the slope signal and the counter signal for improving linearity of the transfer function of the slope ADC 100 will be further discussed in relation to simulations.

[0149] If there are nonlinear effects on the analog input signal in the path to the input terminal of the comparator 120, such as through an input buffer having nonlinearities, an output spectrum of the slope ADC 100 will be affected. In particular, harmonic distortion tones may occur in the output spectrum.

[0150] In FIG. 4, an output spectrum of a slope ADC 100 using a linear relationship between the slope signal and the counter signal is illustrated. In order to simulate nonlinear effects, a third harmonic distortion of −20 dBc has been added, which is shown as a peak in the output spectrum.

[0151] Using a nonlinear relationship between the slope signal and the counter signal, the linearity of the transfer function of the slope ADC 100 may be improved.

[0152] In FIG. 5, a slope signal with a nonlinear relation to time for compensating the nonlinear effects illustrated in FIG. 4 is shown. In the rightmost graph of FIG. 5, the nonlinear part f.sub.nonlinear of the function for mapping the analog input signal V.sub.in onto the signal V.sub.s at the input terminal of the comparator 120 is shown as an input error compared to the input voltage V.sub.in. In the center graph of FIG. 5, a corresponding nonlinear part g.sub.nonlinear of the function for defining the slope signal is shown as a function of the counter value. In the leftmost graph of FIG. 5, the slope signal is illustrated as a solid line, the linear part of the slope signal is illustrated as a dashed line, and the nonlinear part of the slope signal is illustrated as a dotted line. The slope signal is adapted to compensate for the nonlinear part f.sub.nonlinear.

[0153] In FIG. 6, the output spectrum of the slope ADC 100 using the nonlinear relationship between the slope signal and the counter signal is illustrated. As illustrated in FIG. 6, second and third harmonic distortions are suppressed by cancellation of the nonlinear effects using a nonlinear relation between the slope signal and the counter signal.

[0154] When using a common slope signal and common counter signal for a plurality of slope ADCs 100 in a system 200, such as in a time-interleaved ADC, a common nonlinear relationship between the slope signal and the counter signal will be used for all channels (slope ADCs 100).

[0155] This implies that the nonlinear relationship between the slope signal and the counter signal may compensate for any nonlinear effects that are common to all of the channels. However, if there are differences in the nonlinear effects between different channels, the nonlinear relationship between the common slope signal and the common counter signal cannot perfectly compensate for the nonlinear effects of all channels. For instance, there may be mismatches in gain of different buffers for different channels, giving rise to different nonlinear effects for different channels.

[0156] The nonlinear effects may be seen as a nonlinear error between the output of the slope ADCs 100 and the analog input signal, when using a linear relationship between the slope signal and the counter signal. This nonlinear error may thus be different for different levels of the analog input signal and may further be different for different channels.

[0157] In FIG. 7, nonlinear errors are illustrated for a plurality of channels simulated to have different gain mismatches of input buffers. The nonlinear relationship between the slope signal and the counter signal may be defined by fitting a curve to an average nonlinear error, wherein the average nonlinear error is determined for different levels of the analog input signal. The nonlinear relationship may be determined by fitting a polynomial, such as a third order polynomial to the average nonlinear error values.

[0158] The slope signal may then be formed by adding the nonlinear compensation, as illustrated in FIG. 7, to a linear part of the function that defines the slope signal. The nonlinear relationship between the slope signal and the counter signal that is obtained in this manner may then improve an average error of the transfer functions of the plurality of slope ADCs.

[0159] The above discussion is based on the nonlinear relationship between the slope signal and the counter signal being formed by the slope signal being nonlinear in relation to time. However, it should be realized that, according to an alternative, the nonlinear relationship between the slope signal and the counter signal may be achieved by the counter signal being nonlinear in relation to time or by both the slope signal and the counter signal being nonlinear in relation to time.

[0160] Referring now to FIG. 8, a counter signal generator 272 and a slope signal generator 270 according to an embodiment will be described.

[0161] The counter signal generator 272 may be connected to a clock 274 for receiving a clock signal. The counter signal generator 272 may be configured to store a value and increment the stored value by 1 on each pulse from the clock. The counter signal generator outputs a N-bit value counter signal, the value of which is increased with every clock pulse.

[0162] The counter signal generator 272 may for instance be constructed of a number of flip-flops connected in cascade. The counter signal generator 272 may be synchronous such that all flip-flops are triggered by a common clock.

[0163] The slope signal generator 270 may be configured to generate the slope signal based on the counter signal output by the counter signal generator 272. The counter signal may be received by a mapping element 276, which is configured to map a value of the counter signal to a corresponding desired value of the slope signal according to a set nonlinear relationship between the slope signal and the counter signal.

[0164] The mapping element 276 may be configured to perform a digital processing of the counter signal in order to determine a digital representation of the desired value of the slope signal. The mapping element 276 may store a mapping of values of the counter signal to values of the slope signal, such that the mapping element may determine the desired value of the slope signal through look-up in a look-up table. The mapping element 276 may output the desired value of the slope signal represented by M bits, wherein M>N, such that an increased resolution of representing the slope signal is used compared to the resolution of the counter signal.

[0165] The signal from the mapping element 276 may be forwarded to a digital-to-analog converter (DAC) 278 for forming an analog slope signal. The DAC 278 is illustrated here as a voltage DAC 278, but it should be realized that a current DAC may be used instead. The current DAC outputs a current signal, which may then be converted to voltage slope signal for input to the slope ADC 100.

[0166] As illustrated in FIG. 8, the slope ADC 100 may thus receive the counter signal from the counter signal generator 272 and the slope signal from the slope signal generator 270 (e.g., from the DAC 278).

[0167] Referring now to FIGS. 9-10, calibration of the relation between the slope signal and the counter signal to be used for the slope ADC 100 will be discussed. The calibration may be based on a signal input to the slope ADC 100 and the corresponding signal output by the slope ADC 100, such that the nonlinear relationship between the slope signal and the counter signal may compensate for any nonlinearities in the slope ADC 100 regardless of the cause.

[0168] As illustrated in FIG. 9, the calibration may be based on applying a known analog input signal V.sub.in, which is compared to the digital representation output by the slope ADC 100. The known analog input signal Vin may be controlled to assume values in an entire range of values accepted by the slope ADC 100. For instance, the known analog input signal may be a saw-tooth shaped signal providing a slope with monotonically increasing values of the analog input signal.

[0169] The slope ADC 100 may initially be provided with a counter signal and a slope signal having a linear (ideal) relationship.

[0170] The output from the slope ADC 100 may be analyzed for determining a difference between values of the analog input signal that correspond to each step of 1 least significant bit (LSB) in the digital representation. Thus, integral nonlinearities (INL) corresponding to variations in the difference between values of the analog input signal corresponding to 1 LSB may be determined in an INL extraction stage 280.

[0171] Based on determining the INL for each level of the analog input signal, a nonlinear error of the transfer function of the slope ADC 100 may be determined. A function f describing the nonlinear error may be inverted, f.sup.1() and the inverted function may be provided to the mapping element 276 so that the mapping is updated, and the nonlinear error is compensated for. Thus, the mapping element 276 may add a nonlinear part to the linear part of the slope signal.

[0172] The calibration may be run in several iterations for sequentially updating the mapping of the mapping element 276 until nonlinearities of the transfer function of the slope ADC 100 are sufficiently compensated for.

[0173] As illustrated in FIG. 10, the calibration may instead be based on applying a varying analog input signal Vu with known statistics. Thus, the value of the analog input signal at every moment in time may not be known, but the statistics may be known (such as a histogram of values).

[0174] Instead of comparing individual values of the digital representation output by the slope ADC 100 to corresponding values of the analog input signal, statistics of the values of the digital representation may be monitored. The statistics of the digital representation may be compared to the known statistics of the analog input signal and a transfer function of the slope ADC 100 may be extracted based on the comparison.

[0175] The calibration may thus use a monitoring and transfer function extracting stage 290, which determines the transfer function of the slope ADC 100. This transfer function may be used for updating mapping of the mapping element 276.

[0176] Referring now to FIG. 11, a method for converting an analog input signal to a digital representation will be described.

[0177] The method comprises comparing 402 by a comparator two input signals involving a sampled value of the analog input signal and a slope signal. For instance, the comparator may directly compare the sampled value of the analog input signal and the slope signal. The comparing outputs a trigger signal upon identifying a change of which signal input to the comparator is higher.

[0178] The method further comprises receiving 404 by a memory element a counter signal and the trigger signal. Thus, the memory element may be triggered when the comparator identifies a change of which signal input to the comparator is higher.

[0179] The method further comprises determining 406 by the memory element a value of the counter signal when the trigger signal is received. The value of the counter signal may be read into the memory element when the trigger signal is received. The value of the counter signal may then be output as the digital representation of the sampled value of the analog input signal.

[0180] As described in detail above, the slope signal and the counter signal have a nonlinear relationship, wherein the nonlinear relationship is adapted to improve linearity of a transfer function for converting the analog input signal to the digital representation.

[0181] In the above the inventive concept has mainly been described with reference to a limited number of examples. However, as is readily appreciated by a person skilled in the art, other examples than the ones disclosed above are equally possible within the scope of the inventive concept, as defined by the appended claims.