INDUCTORLESS SELF-TUNED INPUT-MATCHING LOW-NOISE AMPLIFIER WITH VERY LOW NOISE FIGURE AND Gm BOOST

Abstract

A low-noise amplifier is disclosed having a first transistor with a first current terminal coupled to a supply voltage rail through a load resistor and a second current terminal coupled to an input node, wherein a bias resistor is coupled between the input node and a fixed voltage node. A second transistor has a third current terminal coupled to an output node and a fourth current terminal coupled to the fixed voltage node. A feedback capacitor is coupled between the input node and the output node, wherein capacitance of the feedback capacitor is sized to eliminate the need for coupling an input impedance matching inductor to the input node.

Claims

1. A low-noise amplifier comprising: a first transistor having a first current terminal coupled to a supply voltage rail through a load resistor and a second current terminal coupled to an input node, wherein a bias resistor is coupled between the input node and a fixed voltage node; a second transistor having a third current terminal coupled to an output feedback node and a fourth current terminal coupled to the fixed voltage node; and a feedback capacitor coupled between a gate of the first transistor and the output feedback node, wherein capacitance of the feedback capacitor is sized to eliminate the need for coupling an input impedance matching inductor to the input node.

2. The low-noise amplifier of claim 1 wherein the fixed voltage node is ground.

3. The low-noise amplifier of claim 1 wherein a capacitance value for the feedback capacitor is between 100 femtofarads and 500 femtofarads.

4. The low-noise amplifier of claim 1 wherein a capacitance value of the feedback capacitor is 250 femtofarads ±20%.

5. The low-noise amplifier of claim 1 wherein a capacitance value for the feedback capacitor is 250 femtofarads ±10%.

6. The low-noise amplifier of claim 1 further comprising a third transistor having a gate coupled to the first current terminal of the first transistor, a fifth current terminal coupled to the feedback output node, and a sixth current terminal coupled to the fixed voltage node.

7. The low-noise amplifier of claim 6 wherein the gate of the third transistor is coupled to the first current terminal of the first transistor by way of a coupling capacitor.

8. The low-noise amplifier of claim 6 wherein the second transistor is coupled to the feedback output node through a cascode-configured fourth transistor.

9. The low-noise amplifier of claim 8 wherein the feedback output node is coupled to an output node through a cascode-configured fifth transistor.

10. The low-noise amplifier of claim 1 wherein the noise factor contribution of the load resistor and the bias resistor is less than 5% of total noise.

11. A method of amplifying a low-noise signal using a low-noise amplifier having a first transistor having a first current terminal coupled to a supply rail through a load resistor and a second current terminal coupled to an input node, a bias resistor coupled between the input node and a fixed voltage node, a second transistor having a third current terminal coupled to an output feedback node and a fourth current terminal coupled to the fixed voltage node, and a feedback capacitor between a gate of the first transistor and the output feedback node, the method comprising: applying a signal to the input node without employing an input matching inductor at the input node; and amplifying the signal using the first transistor and the second transistor, thereby generating an amplified output signal at the output feedback node.

12. The method of amplifying the low-noise signal using the low-noise amplifier of claim 11 wherein the fixed voltage node is ground.

13. The method of amplifying the low-noise signal using the low-noise amplifier of claim 11 wherein a capacitance value for the feedback capacitor is between femtofarads and 500 femtofarads.

14. The method of amplifying the low-noise signal using the low-noise amplifier of claim 11 wherein a capacitance value of the feedback capacitor is 250 femtofarads ±20%.

15. The method of amplifying the low-noise signal using the low-noise amplifier of claim 11 wherein a capacitance value for the feedback capacitor is 250 femtofarads ±10%.

16. The method of amplifying the low-noise signal using the low-noise amplifier of claim 11 further comprising a third transistor having a gate coupled to the first current terminal of the first transistor, a fifth current terminal coupled to the feedback output node, and a sixth current terminal coupled to the fixed voltage node.

17. The method of amplifying the low-noise signal using the low-noise amplifier of claim 16 wherein the gate of the third transistor is coupled to the first current terminal of the first transistor by way of a coupling capacitor.

18. The method of amplifying the low-noise signal using the low-noise amplifier of claim 16 wherein the second transistor is coupled to the feedback output node through a cascode-configured fourth transistor.

19. The method of amplifying the low-noise signal using the low-noise amplifier of claim 18 wherein the feedback output node is coupled to an output node through a cascode-configured fifth transistor.

20. The method of amplifying the low-noise signal using the low-noise amplifier of claim 11 wherein the noise factor contribution of the load resistor and the bias resistor is less than 5% of the total noise.

21. A wireless communication device comprising: receive circuitry configured to receive radio frequency (RF) signals, wherein the receive circuitry comprises a low-noise amplifier (LNA) configured to amplify the RF signals; a baseband processor configured to process a digitized version of the RF signals received by the receive circuitry and to extract the information or data bits conveyed in the received RF signals; and a low-noise amplifier comprising: a first transistor having a first current terminal coupled to a supply voltage rail through a load resistor and a second current terminal coupled to an input node, wherein a bias resistor is coupled between the input node and a fixed voltage node; a second transistor having a third current terminal coupled to an output feedback node and a fourth current terminal coupled to the fixed voltage node; and a feedback capacitor coupled between a gate of the first transistor and the output feedback node, wherein capacitance of the feedback capacitor is sized to eliminate the need for coupling an input impedance matching inductor to the input node.

22. The wireless communication device of claim 21 wherein the fixed voltage node is ground.

23. The wireless communication device of claim 21 wherein a capacitance value for the feedback capacitor is between 100 femtofarads and 500 femtofarads.

24. The wireless communication device of claim 21 wherein a capacitance value of the feedback capacitor is 250 femtofarads ±20%.

25. The wireless communication device of claim 21 wherein a capacitance value for the feedback capacitor is 250 femtofarads ±10%.

26. The wireless communication device of claim 21 further comprising a third transistor having a gate coupled to the first current terminal of the first transistor, a fifth current terminal coupled to the feedback output node, and a sixth current terminal coupled to the fixed voltage node.

27. The wireless communication device of claim 26 wherein the gate of the third transistor is coupled to the first current terminal of the first transistor by way of a coupling capacitor.

28. The wireless communication device claim 26 wherein the second transistor is coupled to the feedback output node through a cascode-configured fourth transistor.

29. The wireless communication device of claim 28 wherein the feedback output node is coupled to an output node through a cascode-configured fifth transistor.

30. The wireless communication device of claim 21 wherein the noise factor contribution of the load resistor and the bias resistor is less than 5% of total noise.

Description

BRIEF DESCRIPTION OF THE DRAWING FIGURES

[0009] The accompanying drawing figures incorporated in and forming a part of this specification illustrate several aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure.

[0010] FIG. 1 is a schematic of a wideband differential output low-noise amplifier (LNA) with noise cancellation (bias circuit is not shown).

[0011] FIG. 2 is a schematic of a wideband single-ended LNA with noise cancellation (bias circuit is not shown).

[0012] FIG. 3 is a schematic of a self-tuned input-matching LNA with reduced noise contribution of a load resistor and a bias resistor in accordance with the present disclosure (bias circuit is not shown).

[0013] FIG. 4 is a schematic showing another embodiment based on the circuit of FIG. 3 and using a p-type metal oxide semiconductor as an inverter to reuse the bias current and cancelling harmonics.

[0014] FIG. 5A is a graph showing input return loss for the LNA in accordance with the present disclosure.

[0015] FIG. 5B is a graph showing reverse isolation for the LNA in accordance with the present disclosure.

[0016] FIG. 5C is a graph showing gain for the LNA in accordance with the present disclosure.

[0017] FIG. 5D is a graph showing output return loss for the LNA in accordance with the present disclosure.

[0018] FIG. 6 is a graph showing self-tuned input matching over a frequency range of 1.4 GHz to 2.7 GHz for the LNA in accordance with the present disclosure.

[0019] FIG. 7A is a plot showing noise figure for the LNA in accordance with the present disclosure.

[0020] FIG. 7B is a plot showing the stability factor for the LNA in accordance with the present disclosure.

[0021] FIG. 8A is a graph showing input-referred IP3 with an extraction point of −30 dBm for the LNA in accordance with the present disclosure.

[0022] FIG. 8B is a graph showing input-referred IP2 with two extraction points of −15 dBm and −30 dBm for the LNA in accordance with the present disclosure.

[0023] FIG. 9 is a diagram showing how the disclosed LNA may interact with user elements such as wireless communication devices.

DETAILED DESCRIPTION

[0024] The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

[0025] It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

[0026] It will be understood that when an element such as a layer, region, or substrate is referred to as being “on” or extending “onto” another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, there are no intervening elements present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being “over” or extending “over” another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly over” or extending “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.

[0027] Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.

[0028] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and/or “including” when used herein specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

[0029] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0030] Embodiments are described herein with reference to schematic illustrations of embodiments of the disclosure. As such, the actual dimensions of the layers and elements can be different, and variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are expected. For example, a region illustrated or described as square or rectangular can have rounded or curved features, and regions shown as straight lines may have some irregularity. Thus, the regions illustrated in the figures are schematic and their shapes are not intended to illustrate the precise shape of a region of a device and are not intended to limit the scope of the disclosure. Additionally, sizes of structures or regions may be exaggerated relative to other structures or regions for illustrative purposes and, thus, are provided to illustrate the general structures of the present subject matter and may or may not be drawn to scale. Common elements between figures may be shown herein with common element numbers and may not be subsequently re-described.

[0031] The narrow band low-noise amplifier (LNA) is used widely for mobile applications since it provides a very low noise figure (NF<1 dB) while consuming reasonable current. The narrow band input matching is achieved by a series resonator at the input which is composed of off-chip components and the source degenerated inductor. The off-chip matching network is usually composed of a series inductor (L) and shunt capacitor (C) surface-mount devices that occupy considerable area in front-end modules and add cost. On the other hand, conventional wideband LNAs match over a wide frequency range without using off-chip components but suffer from a poor noise figure (NF>2 dB), which makes them less attractive for 4G or 5G front-end modules. Therefore, there is challenging trade-off between achievable noise figure and the input matching requirement. Disclosed is an LNA that addresses this trade-off and introduces a LNA without requiring any off-chip matching components (like a wideband LNA) while reducing the noise figure below 1 dB (like a narrow band LNA).

[0032] The schematic of conventional common gate-common source (CG-CS) wideband low-noise amplifier (LNA) 10 is shown in related art in FIG. 1. As depicted in related art in FIG. 1, the LNA 10 has a first transistor M.sub.1 and a second transistor M.sub.2. A drain of the first transistor M.sub.1 is coupled to a supply rail V.sub.DD through a first resistor R.sub.1, and a drain of the second transistor M.sub.2 is coupled through a second resistor R.sub.2. The first resistor R.sub.1 and the second resistor R.sub.2 may also be referred to generally as load resistors. A source of the first transistor M.sub.1 is coupled to a fixed voltage node GND1 through a bias resistor R.sub.b1. Note that complete bias circuitry is not shown and that drain and source terminals may also be commonly referred to as current terminals, while gates may be referred to as control terminals. A gate of the first transistor M.sub.1 is coupled to bias voltage (not shown in FIG. 1), which configures the first transistor M.sub.1 as a common gate amplifier. A current source I.sub.bias represents a bias current that flows to the bias resistor R.sub.b1 from the source of the first transistor M.sub.1. A source of the second transistor M.sub.2 is coupled to the fixed voltage node GND1, which configures the second transistor M.sub.2 as a common source amplifier. The fixed node GND1 is ground in this case.

[0033] A gate of the second transistor M.sub.2 is coupled to a first node N1 that is between the source of the first transistor M.sub.1 and the bias resistor R.sub.b1. A radio frequency signal (RF) source V.sub.in with a RF source resistance R.sub.s is coupled across the bias resistor R.sub.b1. An amplifier output voltage V.sub.out is shown between a second node N2 and a third node N3. The second node includes the drain of the first transistor M.sub.1, and the third node N3 includes the drain of the second transistor M.sub.2. Channel noise generated by the first transistor M.sub.1 is represented by a jagged signal trace, and an RF signal generated by the RF source V.sub.in is represented by a sinusoidal signal trace at the first node N1. Out of phase amplified channel noise and the RF signal are depicted at the second node N2 and the third node N3, respectively.

[0034] Input impedance matching is provided by the first transistor M.sub.1 that is common gate configured where R.sub.s=1/gm.sub.1. In parallel to the first transistor M.sub.2, the second transistor M.sub.2 provides some cancellation of the channel noise generated in the first transistor M.sub.1. The channel noise of the first transistor M.sub.1 is substantially cancelled because the channel noise appears in phase at the drains of the first transistor M.sub.1 and the second transistor M.sub.2, as shown in related art in FIG. 1, while the RF input signal appears in the opposite phase at the outputs. Therefore, noise cancellation occurs under the following conditions:

R.sub.s.Math.gm.sub.2.Math.R.sub.2=R.sub.1  (1)

[0035] Assuming that input is matched to R.sub.s, Equation (1) is simplified to

gm.sub.2.Math.R.sub.2=gm.sub.1.Math.R.sub.1  (2)

which means that if the gain of the first transistor M.sub.1 and the second transistor M.sub.2 are the same, taking differentially the outputs at the drains of the first transistor M.sub.1 and the second transistor M.sub.2 cancels the channel noise of first transistor M.sub.1 while the output voltage V.sub.out is amplified.

[0036] FIG. 2 is a schematic of another version of the related-art amplifier 10 that adds a third transistor M.sub.3 that is to invert the output of the first transistor M.sub.1 and sum the transconductance of the second transistor M.sub.2 and the third transistor M.sub.3 at the third node N3. Moreover, the third transistor M.sub.3 is configured to convert differential output to single-ended output.

[0037] As depicted in FIG. 3, the channel noise can be cancelled if

R.sub.s.Math.gm.sub.2=gm.sub.3.Math.R.sub.1.Math.  (3)

[0038] Assuming that input impedance is matched to R.sub.s, Equation (3) is simplified to

gm.sub.2/gm.sub.3=gm.sub.1.Math.R.sub.1  (4)

[0039] However, the channel noise of the first transistor M.sub.1 can be cancelled, but the noise contribution from the bias resistor R.sub.b1 and first resistor R.sub.1 is substantial, which leads to an increased noise factor (NF) of more than 2 dB.

[0040] FIG. 3 is a schematic of an LNA 12 that is structured and configured in accordance with the present disclosure to substantially improve the NF over the related-art LNA 10 depicted in FIGS. 1 and 2. In this exemplary embodiment, a coupling capacitor C.sub.C1 is coupled between the gate of M.sub.3 and the second node N2. The coupling capacitor C.sub.C1 makes possible to have individual bias voltage for M.sub.3, which plays an important role for harmonic cancellation of two concurrent paths (CG and CS). In the exemplary embodiment depicted in FIG. 3, a second coupling capacitor C.sub.C2 is coupled between a source resistor R.sub.s and the first node N1. A third coupling capacitor C.sub.C3 is coupled between a gate of the second transistor M.sub.2 and the source resistor R.sub.s and the second coupling capacitor C.sub.C2, which effectively couples the gate of the second transistor M.sub.2 to the first node N1.

[0041] In the present disclosure two cascode devices have been employed as follows. A fourth transistor M.sub.4 in cascode with the second transistor M.sub.2 is coupled between the third node N3 and the drain of the second transistor M.sub.2. The fourth transistor M.sub.4 improves the gain provided by the second transistor M.sub.2, which in turn lowers the level of bias current flowing through the first resistor R.sub.1 and the bias resistor R.sub.b1. As such, the LNA 12 reduces the noise contributions of the first resistor R.sub.1 and the bias resistor R.sub.b1. A fifth transistor M.sub.5 is coupled in cascode with the third transistor M.sub.3 and provides isolation between the output at a fourth node N4 and the input of the LNA 12 at the first node N1.

[0042] The LNA 12 is configured to employ transconductance (gm) enhancement that allows the first transistor M.sub.1 to operate with lower bias current while providing the required gm for input matching. To enhance the gm of the transistor M.sub.1, a feedback capacitor C.sub.f1 (abbreviated as C.sub.f in the following equations) is coupled between the gate of the first transistor M.sub.1 and the third node N3 that is coupled to the drain of the third transistor M.sub.3. In this exemplary embodiment, the third node N3 may be referred to as a feedback output node. A capacitance value for the feedback capacitor C.sub.f1 is between 100 femtofarads and femtofarads. In some embodiments, the capacitance value of the feedback capacitor C.sub.f1 is 250 femtofarads ±20%. In other exemplary embodiments, the capacitance value for the feedback capacitor is 250 femtofarads ±10%. The feedback capacitor C.sub.f1 may be a metal-insulator-metal that occupies no more than around 10×12 micrometers of die real estate. A first optional resistor R.sub.f1 shown in dashed line may be coupled parallel with feedback capacitor C.sub.f1, and/or a second optional resistor R.sub.f2, also shown in dashed line, may be added in series with feedback capacitor C.sub.f1 to increase the reverse isolation and improve the stability factor with a trade-off to degraded input matching. Resistances of the first optional resistor R.sub.f1 and the second optional resistor R.sub.f2 may be optimized to provide the best performance considering the trade-off between stability factor and reverse isolation. Since the third node N3 is in the opposite phase of input voltage with no need for an additional inverter amplifier, the source-gate voltage of the first transistor M.sub.1 is increased as follows:

Vsg=(1+A.sub.v).Math.v.sub.in  (5)

where A.sub.v is boosting factor. The boosting factor A.sub.v is equal to the gain from the input to the feedback output node, which is the sum of the gain of the stage of the first transistor M.sub.1 followed by the inverter-configured third transistor M.sub.3 and the gain of the stage of the second transistor M.sub.2 as follows:

[00001]$\begin{array}{cc}\begin{array}{cc}{A}_v=\frac{Rcas.\left(gm2+R1.gm1.gm3\right)}{1-Rcas.R1.gm1.gm3}& \mathrm{Cf}\gg \mathrm{Cgs}1\end{array}& \left(6\right)\end{array}$

where R.sub.cas is the impedance seen from the third node N3 to which the source of the fifth transistor M.sub.5 is coupled. Increased source-gate voltage is equivalent to enhancing the transconductance, and the gate-source capacitance, with the same boosting factor. Therefore, the input-matching condition changes to the following:

[00002]$\begin{array}{cc}{R}_{in}=\frac{1}{\left(1+A_v\right).g{m}_1}=R_s& \left(7\right)\end{array}$

[0043] Then, the noise of M.sub.1 is cancelled if:

gm.sub.2/gm.sub.3=(1+A.sub.v).Math.gm.sub.1.Math.R.sub.1  (8)

[0044] It is worth mentioning that a large boosting factor in this design can be achieved because of amplification through both the amplifier stage of the first transistor M.sub.1 and the amplifier of the second transistor M.sub.2. Therefore, the required transconductance gm.sub.1 of the first transistor M.sub.1 for input matching is reduced considerably as large as the boosting factor, which can be achieved relatively easily by lower bias current and by preserving substantial gate-source overdrive voltage for better linearity performance. On the other hand, lower current flowing through the first transistor M.sub.1 releases voltage headroom, which allows large load and bias resistors such as the first resistor R.sub.1 to be used to reduce the noise contribution.

[0045] In the present embodiment, by using two cascode devices, the boosting factor (A.sub.v) can be increased, which further reduces the bias current of the CG stage and consequently the noise contribution of the load and bias resistor of the CG stage. Using one cascode device or taking the drain of M.sub.2/source of M.sub.4 as output feedback node only provides smaller boosting factor, which does not lead to considerable noise reduction. For applications for which still higher noise figure is acceptable, one cascode device can be used to preserve more voltage headroom, or M.sub.2/source of M.sub.4 can be taken as the feedback output node.

[0046] As depicted in FIG. 4, a schematic of another embodiment of the LNA has a positive metal oxide semiconductor (PMOS) transistor instead of a negative metal oxide semiconductor (NMOS) transistor used as an inverter (M.sub.3). This allows bias current of the third transistor M.sub.3 to be re-used by the second transistor M.sub.2, and therefore a substantial current is saved. Another benefit of this embodiment is the cancelling of harmonics by using complementary devices. This embodiment can be implemented in advanced technology nodes where PMOS has similar cut-off frequency as NMOS.

Self-Tuned Input Matching

[0047] Since the 4G/5G front-end modules are designed based on the carrier aggregation concept, for each band a dedicated LNA core is used. As depicted in FIG. 3, each dedicated LNA core as represented by the LNA 12 has an output tank 14 having a tank inductor Li and a tank capacitor C1. A resonance frequency of the output tank 14 of each LNA core is centered at the mid-frequency of the band and is matched to 50Ω to drive an external receiver module. In this design a conventional resonator is used as load of the LNA 12 and is matched to 50Ω by a capacitor transformer, made up of a first impedance matching capacitor C.sub.1 and a second impedance matching capacitor C.sub.2.

[0048] An important feature of the disclosed LNA 12 is that the input impedance matching is not wideband but rather is narrow band, which automatically without any additional circuitry is tunable over a wide frequency range at the same center frequency of the output tank 14. The input matching condition is met if the required gain (A.sub.v) to boost gm.sub.1 is obtained. The required gain from input to cascode node (A.sub.v) is achieved at the resonance frequency of the output tank since a resistance R.sub.cas seen from the third node N3 reaches to its maximum value. In other words, the impedance seen from the third node N3 depends on an impedance Z.sub.l of output tank 14 as follows:

[00003]$\begin{array}{cc}{R}_{cas}=\frac{Z_l+r_{o5}}{1+g{m}_5.r_{o5}}.Math.r_{o3}.Math.r_{o4}.\left(1+g{m}_4.r_{o2}\right)& \left(9\right)\end{array}$

[0049] Considering the gate-source capacitance Cgs.sub.1 of the first transistor M.sub.1 and the gate-to-source capacitance Cgs.sub.2 of the second transistor M.sub.2 and substituting Equation (9) in Equation (6), then Equation (7) gives the input impedance Zin as follows:

[00004]$\begin{array}{cc}{Z}_{in}=\left[\left(\frac{1}{{\mathrm{gm}}_1}.Math.\frac{1}{Cg{s}_1}\right).Math.\left(\frac{1-\left(\frac{Z_l+r_{o5}}{1+g{m}_5.r_{o5}}.Math.r_{o3}.Math.r_{o4}.\left(1+g{m}_4.r_{o2}\right)\right).Rl.gm1.gm3}{1+\mathrm{gm}2\left(\frac{Z_l+r_{o5}}{1+g{m}_5.r_{o5}}.Math.r_{o3}.Math.r_{o4}.\left(1+g{m}_4.r_{o2}\right)\right)}\right)\right].Math.\frac{1}{Cg{s}_2}& \left(10\right)\end{array}$

[0050] From Equation (9), the input impedance Zin follows the impedance of output tank 14, which means that the input impedance Zin resonates at very close frequency to the center frequency of output tank 14 (deviation is mainly because of Cgs.sub.2 and Cgs.sub.1), where at the resonance frequency the input resistance is set to be equal to the resistance of the RF source resistance R.sub.s.

Simulation Results

[0051] The LNA 12 was implemented in 90 nm silicon-on-insulator technology with a supply voltage V.sub.DD of 1.2 V for frequency range of 1.4 GHz to 2.7 GHz. The first transistor M.sub.1 is biased with very low current of 0.28 mA. The bias currents of the second transistor M.sub.2 and the third transistor M.sub.3 are about 11.4 mA and 0.3 mA, respectively. The current consumption is in the level of a conventional narrow band LNA. About 20 femtofarads of capacitance for an input pad at the first node N1 and 100 picohenries of parasitic inductance for the fixed voltage node GND1 pad are considered. The LNA 12 is matched to 50Ω at both the first node N1 (i.e., the input node) and the fifth node N5 (i.e., the output node).

[0052] A high gain of >20 dB can be reached using an inductance value of 2.5 nanohenries with a quality factor of 12 for the tank inductor L.sub.l. The reverse isolation is relatively high because of the cascode configuration of the fourth transistor M.sub.4 and the fifth transistor M.sub.5, which also acts as a cascode device for the first transistor M.sub.1. The third transistor M.sub.3 also provides additional isolation. Small signal parameters for input matching, reverse isolation, gain, and output matching at 2 GHz are shown in FIGS. 5A to 5D.

[0053] To demonstrate self-tuning of input matching, the center frequency of the output tank 14 is tuned at three frequency points: 1.4 GHz, 2 GHz, and 2.7 GHz. As can be observed from FIG. 6, the input matching is self-tuned along with tuning the center frequency of output tank 14 (FIG. 3). The selectivity at input helps to attenuate out-of-band components to improve the linearity.

[0054] Very low noise figure of 0.51 dB to 0.81 dB is achieved within the 1.4 GHz to 2.7 GHz frequency range, as shown in FIG. 7A. The noise contribution of each of the first transistor M.sub.1, the second transistor M.sub.2, the third transistor M.sub.3, the fourth transistor M.sub.4, the fifth transistor M.sub.5, load resistor (R.sub.1), and bias resistor (Rb) is given by the following Table 1. As can be observed from Table 1, the noise of the first transistor M.sub.1 is cancelled and the noise contribution of the first resistor R.sub.1 and the bias resistor R.sub.b1 is considerably reduced (5% of total noise) by using this disclosed gm boosting technique. Table 1 also demonstrates the effectiveness of the disclosed embodiments to reduce noise figure of the LNA 12, because without using gm boosting, the noise contribution of load and bias resistors can be quite large and comparable with noise of the first transistor M.sub.1. The noise figure is mainly determined by the gm of the second transistor M.sub.2.

TABLE-US-00001 TABLE 1 Noise contribution of devices Device Parameter Noise Contribution (V2) % of Total Input rn 4.183e−9 76.06 M2 id 8.061e−10 14.66 Rb Thermal 1.424e−10 2.59 R1 Thermal 1.291e−10 2.35 M5 id 6.120e−11 1.11 M3 id 2.801e−11 0.51 M1 id 2.632e−11 0.48

[0055] According to FIG. 7B, the LNA 12 is unconditionally stable over a wide frequency range, since the stability factor is larger than one and because of high reverse isolation provided by employing two cascode devices.

[0056] The second-order and third-order input-referred interference points are shown in FIGS. 8A and 8B, respectively, for 2 GHz input power. The LNA gain is set to 20.4 dB, and an IIP3 of −6 dBm is achieved. The second-order harmonic indicates cancellation effects at input power 25 dBm (specially notched around −20 dBm input power). Therefore, IIP2 value depends on the extraction point. Two extraction points of small input power (−30 dBm) and large input power (−15 dBm) give +5.5 dBm and +13.5 dBm for IIP2, respectively.

[0057] With reference to FIG. 9, the concepts described above may be implemented in various types of wireless communication devices or user elements 16, such as mobile terminals, smart watches, tablets, computers, navigation devices, access points, and the like that support wireless communications, such as cellular, wireless local area network (WLAN), Bluetooth, and near-field communications. The user elements 16 will generally include a control system 18, a baseband processor 20, transmit circuitry 22, receive circuitry 24 that includes the LNA 12 (FIG. 3 and FIG. 4), antenna switching circuitry 26, multiple antennas 28, and user interface circuitry 30. The receive circuitry 24 receives radio frequency signals via the antennas 28 and through the antenna switching circuitry 26 from one or more basestations. A low-noise amplifier and a filter cooperate to amplify and remove broadband interference from the received signal for processing. Downconversion and digitization circuitry (not shown) will then downconvert the filtered, received signal to an intermediate or baseband frequency signal, which is then digitized into one or more digital streams.

[0058] The baseband processor 20 processes the digitized received signal to extract the information or data bits conveyed in the received signal. This processing typically comprises demodulation, decoding, and error correction operations. The baseband processor 20 is generally implemented in one or more digital signal processors and application-specific integrated circuits.

[0059] For transmission, the baseband processor 20 receives digitized data, which may represent voice, data, or control information, from the control system 18, which it encodes for transmission. The encoded data is output to the transmit circuitry 22, where it is used by a modulator to modulate a carrier signal that is at a desired transmit frequency or frequencies. A power amplifier will amplify the modulated carrier signal to a level appropriate for transmission and deliver the modulated carrier signal through the antenna switching circuitry 26 to the antennas 28. The antennas 28 and the replicated transmit circuitry 22 and receive circuitry 24 may provide spatial diversity. Modulation and processing details will be understood by those skilled in the art.

[0060] It is contemplated that any of the foregoing aspects, and/or various separate aspects and features as described herein, may be combined for additional advantage. Any of the various embodiments as disclosed herein may be combined with one or more other disclosed embodiments unless indicated to the contrary herein.

[0061] Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.