ON-CHIP CAPACITANCE MEASUREMENT METHOD AND APPARATUS

Abstract

An on-chip capacitance measurement method and associated systems and devices are provided. Embodiments described herein rely on using the capacitor under test in an on-chip relaxation oscillator configuration whose charging/discharging currents, supply voltage, and output frequency are measured individually in a measurement block. The voltage thresholds of the relaxation oscillation are calculated from the circuit elements and the measured supply voltage. Because the oscillation frequency of the relaxation oscillator is a function of the capacitance under test, the charging/discharging currents, and the supply voltage (via voltage thresholds), the capacitance under test can be calculated using the measured values of the other quantities. Embodiments described herein provide an accurate, low-power, small-area on-chip system capable of measuring capacitance with high accuracy. An algorithm employing the above method and apparatus for tuning a crystal oscillator is also provided. Relevant circuit implementations used in the on-chip measurement system are also disclosed.

Claims

1. A method for measuring on-chip capacitance, the method comprising: disconnecting a target capacitance from a main circuit of an integrated circuit; connecting the target capacitance to a relaxation oscillator on the integrated circuit; measuring an output of the relaxation oscillator; and measuring the target capacitance based on the measured output.

2. The method of claim 1, further comprising disconnecting the target capacitance from the main circuit simultaneously with connecting the target capacitance to the relaxation oscillator.

3. The method of claim 1, further comprising tuning the target capacitance based on the measured target capacitance.

4. The method of claim 1, wherein the target capacitance is measured based on an output frequency of the relaxation oscillator.

5. The method of claim 4, wherein the target capacitance is measured further based on a measured voltage and measured currents of the relaxation oscillator.

6. The method of claim 1, wherein the target capacitance comprises a first capacitor and a second capacitor associated with a crystal oscillator.

7. The method of claim 6, wherein disconnecting the target capacitance comprises disconnecting a crystal oscillator core of the crystal oscillator from the main circuit.

8. The method of claim 6, further comprising measuring a second capacitance of the second capacitor based on the output of the relaxation oscillator.

9. The method of claim 8, further comprising measuring a first capacitance of the first capacitor based on the measured second capacitance and another output of the relaxation oscillator.

10. The method of claim 9, wherein measuring the target capacitance comprises determining a first target capacitance based on the first capacitance.

11. The method of claim 10, further comprising tuning the first capacitor to the first target capacitance.

12. An integrated circuit, comprising: a main circuit; a relaxation oscillator; switching circuitry configured to selectively connect a target capacitance to the main circuit or to the relaxation oscillator; and a measurement block configured to measure the target capacitance based on an output of the relaxation oscillator.

13. The integrated circuit of claim 12, wherein the relaxation oscillator is configured to be disabled when disconnected from the target capacitance.

14. The integrated circuit of claim 12, wherein the switching circuitry comprises: a first switch coupled between the main circuit and the target capacitance; and a second switch coupled between the capacitor and the target capacitance, wherein a selection signal selectively causes the first switch to close simultaneous with the second switch opening and the first switch to open simultaneous with the second switch closing.

15. The integrated circuit of claim 12, wherein the measurement block comprises voltage measurement circuitry, current measurement circuitry, and frequency measurement circuitry.

16. The integrated circuit of claim 12, wherein the target capacitance comprises a first capacitor and a second capacitor associated with a crystal oscillator.

17. The integrated circuit of claim 12, wherein the target capacitance comprises a digitally controlled capacitor bank.

18. A tuning circuit, comprising: a relaxation oscillator; switching circuitry configured to selectively disconnect a target capacitance from a main circuit and connect the target capacitance to the relaxation oscillator; a measurement block configured to measure a value of the target capacitance based on an output of the relaxation oscillator; and a tuning block configured to adjust the target capacitance based on the measured value.

19. The integrated circuit of claim 18, wherein the measurement block comprises voltage measurement circuitry, current measurement circuitry, and frequency measurement circuitry.

20. The integrated circuit of claim 19, wherein the tuning block is configured to cause: the voltage measurement circuitry to measure a threshold voltage associated with the target capacitance; the current measurement circuitry to measure a current through the relaxation oscillator; and the frequency measurement circuitry to measure a frequency output of the relaxation oscillator.

Description

BRIEF DESCRIPTION OF THE DRAWING FIGURES

[0016] The accompanying drawing figures incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description serve to explain the principles of the disclosure.

[0017] FIG. 1A is a circuit diagram of a previously proposed capacitance measurement approach based on measurement of transient currents.

[0018] FIG. 1B is a circuit diagram of another previously proposed capacitance measurement approach based on measuring amplitudes of sinusoidal signals.

[0019] FIG. 1C is a circuit diagram of another previously proposed capacitance measurement approach.

[0020] FIG. 1D is a circuit diagram of another previously proposed capacitance measurement approach.

[0021] FIG. 2 is a schematic block diagram of an integrated circuit with a measurement circuit according to the present disclosure.

[0022] FIG. 3A is a schematic diagram of an exemplary embodiment of the measurement circuit of FIG. 2.

[0023] FIG. 3B is a schematic diagram of an exemplary digitally controlled capacitor bank for the measurement circuit of FIG. 3A.

[0024] FIG. 4 is a schematic diagram of an exemplary tuning circuit for the integrated circuit of FIG. 2.

[0025] FIG. 5 is a schematic diagram of an exemplary relaxation oscillator for the integrated circuit of FIG. 2.

[0026] FIG. 6 is a graphical representation of exemplary waveforms of the relaxation oscillator of FIG. 5.

[0027] FIG. 7 is a schematic diagram of an exemplary comparator for the relaxation oscillator of FIG. 5.

[0028] FIG. 8 is a schematic diagram of another exemplary embodiment of the measurement circuit of FIG. 2.

[0029] FIG. 9 is a schematic diagram of another exemplary embodiment of the measurement circuit of FIG. 2.

[0030] FIG. 10 is a flow diagram of a tuning algorithm for the tuning circuit of FIG. 4.

[0031] FIG. 11 is a flow diagram of a process for measuring on-chip capacitance.

[0032] FIG. 12 is a block diagram of a computer system suitable for implementing on-chip capacitance measurement and/or tuning according to embodiments disclosed herein.

DETAILED DESCRIPTION

[0033] The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

[0034] It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

[0035] It will be understood that when an element such as a layer, region, or substrate is referred to as being “on” or extending “onto” another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, there are no intervening elements present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being “over” or extending “over” another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly over” or extending “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.

[0036] Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.

[0037] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and/or “including” when used herein specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

[0038] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0039] An on-chip capacitance measurement method and associated systems and devices are provided. Embodiments described herein rely on using the capacitor under test in an on-chip relaxation oscillator configuration whose charging/discharging currents, supply voltage, and output frequency are measured individually in a measurement block. The voltage thresholds of the relaxation oscillation are calculated from the circuit elements and the measured supply voltage. Because the oscillation frequency of the relaxation oscillator is a function of the capacitance under test, the charging/discharging currents, and the supply voltage (via voltage thresholds), the capacitance under test can be calculated using the measured values of the other quantities.

[0040] Using digitally controlled switches and other dedicated circuitry, a capacitor normally associated with other circuits (such as crystal oscillators) can be tested by putting the main circuit where the capacitor is used in high-impedance (high-Z) mode and connecting the capacitor to the relaxation oscillator for measurement. After the measurement is done, the capacitor is disconnected from the relaxation oscillator and the main circuit is returned to the normal mode. This can be done for a multiplicity of capacitors associated with a given circuit and can also be employed for tuning by adjusting the control code of digitally programmable capacitive loads in cases where highly accurate capacitances must be presented to a resonator for ensuring oscillation at the specified frequency.

[0041] Embodiments described herein provide an accurate, low-power, small-area on-chip system capable of measuring capacitance with high accuracy. An algorithm employing the above method and apparatus for tuning a crystal oscillator is also provided. Relevant circuit implementations used in the on-chip measurement system are also disclosed.

[0042] FIG. 2 is a schematic block diagram of an integrated circuit 10 with a measurement circuit 12 according to the present disclosure. The measurement circuit 12 measures on-chip a single-ended capacitance C associated with the integrated circuit 12, such as an oscillator. In normal operation, when digital control signal SELC is at logic 0, switch sw.sub.C is open and switch sw.sub.Cb is closed, connecting capacitance C to the main circuit 14 with which it is associated. When SELC is at logic 1, switch sw.sub.C is closed and switch sw.sub.Cb is open, effectively disconnecting capacitance C from the main circuit and connecting it to a relaxation oscillator 16 (present on the same chip) whose frequency is a function of capacitance C and other circuit parameters.

[0043] The value of capacitance C is measured with high accuracy by measuring the output frequency of the relaxation oscillator 16, and all the quantities involved in producing its output waveform (such as voltage thresholds and charging/discharging currents) using dedicated circuitry in a measurement block 18. This information may then be used in determining other quantities of interest associated with the main circuit 14 (e.g., its own oscillation frequency), once the capacitance C is reconnected to the main circuit 14 (e.g., by setting SELC to logic 0). In some embodiments, the relaxation oscillator 16 can be enabled or disabled by control signal RELOSCEN.

[0044] FIG. 3A is a schematic diagram of an exemplary embodiment of the measurement circuit 12 of FIG. 2. Here, two adjustable capacitors C.sub.1, C.sub.2 primarily associated with a van den Homberg crystal (XTAL) oscillator can be functionally disconnected from the crystal oscillator core 20 and can be in turn connected to the relaxation oscillator 16 via switches sw.sub.C1 and sw.sub.C2. respectively. The switches sw.sub.C1 and sw.sub.C2 can be controlled by capacitor select signals SELC1 and SELC2, respectively.

[0045] The functional disconnect from the crystal oscillator core 20 can be achieved by putting the crystal oscillator core 20 in high-impedance (high-Z) mode (e.g., by cutting off its supply current) using control signal HIGHZ, and by disconnecting the rest of the circuit (such as bias resistors R.sub.x1, R.sub.x2) using switches (sw.sub.Rx1, sw.sub.Rx2, respectively). The rest of the measurement circuit 12 in FIG. 3A is similar in form and function to the diagram of FIG. 2.

[0046] FIG. 3B is a schematic diagram of an exemplary digitally controlled capacitor bank 22 for the measurement circuit 12 of FIG. 3A. In an exemplary aspect, one or both of capacitors C.sub.1 and C.sub.2 can be implemented as digitally controlled capacitor banks 22. Each digitally controlled capacitor bank 22 can include M different capacitors C.sub.0, C.sub.1, . . . , C.sub.M−1 selectively connected to node A (for capacitor C.sub.1) or node B (for capacitor C.sub.2) of FIG. 3A using corresponding switches sw.sub.b0, sw.sub.b1, . . . , sw.sub.b(M−1) (e.g., using control signals b.sub.0, b.sub.1, . . . , b.sub.M−1). It should be understood that the capacitor bank 22 of FIG. 3B is illustrative in nature and other circuit arrangements may be used in other embodiments.

[0047] FIG. 4 is a schematic diagram of an exemplary tuning circuit 24 for the integrated circuit 10 of FIG. 2. The tuning circuit 24 is similar to the measurement circuit 12, with a tuning block 26 added to control the settings for capacitors C.sub.1 and C.sub.2 associated with the crystal oscillator core 20. Accordingly, in an exemplary aspect the tuning block 26 provides digital control for one or more digitally controlled capacitor banks 22 as in FIG. 3B.

[0048] The tuning block 26 controls the capacitors C.sub.1 and C.sub.2 based on the data extracted by means of the relaxation oscillator 16 and the measurement block 18. In some examples, capacitor C.sub.1 cannot be physically separated from the parasitic capacitance C.sub.P when switch sw.sub.c1 is closed, and the tuning algorithm must take this aspect into account. For tuning purposes (e.g., connecting a specified capacitance in parallel with the crystal oscillator core 20), if capacitors C.sub.1 and C.sub.2 are identical all the information relevant to capacitor C.sub.1 (in particular, the size of the minimum capacitance step) can be extracted by measuring capacitor C.sub.2, which does not have any board parasitic capacitance C.sub.P connected in parallel to it. By measuring C.sub.1 at the minimum setting (together with C.sub.P), the previously extracted capacitance step using C.sub.2 can be used to calculate the target value of the (C.sub.1+C.sub.P) combination. This tuning algorithm is further discussed below with respect to FIG. 10).

[0049] The tuning block 26 and/or the measurement block 18 can be implemented using discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. In some embodiments the tuning block 26 and/or the measurement block 18 may be implemented with a microprocessor or any conventional processor, controller, microcontroller, or state machine.

[0050] FIG. 5 is a schematic diagram of an exemplary relaxation oscillator 16 for the integrated circuit 10 of FIG. 2. Here, C.sub.t is the capacitance under test. A comparator COMP provides output V.sub.OUT based on an inverting input and a noninverting input. A first resistor R.sub.1 is connected between supply voltage V.sub.DD and the noninverting input, and a second resistor R.sub.2 is connected between the noninverting input and ground (e.g., forming a voltage divider coupled to the noninverting input). A third resistor is connected between the output V.sub.OUT and the noninverting input. The resistor arrangement permits the comparator COMP to operate with input voltage ranges that do not include the V.sub.DD/2 point. This is advantageous in low-voltage systems in that the internal structure of the comparator COMP can be topologically simple and ensure operation of transistors away from the triode region (in CMOS implementations).

[0051] The capacitance under test C.sub.t is connected between the inverting input of the comparator COMP and ground. A first current source I.sub.1 is coupled between the supply voltage V.sub.DD and the inverting input, and a second current source I.sub.2 is coupled between the inverting input and ground. The current sources I.sub.1 and I.sub.2 are connected using switches sw.sub.I1, sw.sub.I1b (connected to the first current source I.sub.1) and sw.sub.I2, sw.sub.I2b (connected to the first current source I.sub.2) such that the capacitance under test C.sub.t oscillates between being charged and discharged. In this regard, the enabling inputs of switches sw.sub.I1, sw.sub.I1b, sw.sub.I2, sw.sub.I2b are connected to the output V.sub.OUT such that in a first period the first current source I.sub.1 is connected to the inverting input such that the capacitance under test C.sub.t is charged while the second current source I.sub.2 is disconnected. Once the capacitance under test C.sub.t is charged, in a second period the first current source I.sub.1 is disconnected and the second current source I.sub.2 is connected to the inverting input such that the capacitance under test C.sub.t is discharged.

[0052] FIG. 6 is a graphical representation of exemplary waveforms of the relaxation oscillator 16 of FIG. 5. With the notations in FIG. 6, assuming rail-to-rail swing of the comparator output V.sub.OUT, the following equations can be derived for the circuit of FIG. 5:

[00001]$\begin{array}{cc}{V}_{\mathrm{UTH}}=\frac{R_2}{R_2+R_1.Math.R_3}{V}_{\mathrm{DD}}& \mathrm{Equation}1\end{array}$$\begin{array}{cc}{V}_{\mathrm{LTH}}=\frac{R_2.Math.R_3}{R_2+R_2.Math.R_3}{V}_{\mathrm{DD}}& \mathrm{Equation}2\end{array}$$\begin{array}{cc}\Delta V=V_{\mathrm{UTH}}-V_{\mathrm{LTH}}=\frac{R_1{R}_2}{R_2{R}_3+R_1\left(R_2+R_3\right)}{V}_{\mathrm{DD}}& \mathrm{Equation}3\end{array}$$\begin{array}{cc}\Delta T_1=\frac{C_t.Math.\Delta V}{I_1}& \mathrm{Equation}4\end{array}$$\begin{array}{cc}\Delta T_2=\frac{C_t.Math.\Delta V}{I_2}& \mathrm{Equation}5\end{array}$$\begin{array}{cc}{f}_{\mathrm{OUT}}=\frac{1}{\Delta T_1+\Delta T_2}=\frac{I_1{I}_2}{C_t.Math.\Delta V\left(I_1+I_2\right)}& \mathrm{Equation}6\end{array}$

[0053] In the above equations, I.sub.1 and I.sub.2 are the capacitor charging and discharging currents, respectively. V.sub.UTH and V.sub.LTH are the upper and lower voltage thresholds, respectively, of the relaxation oscillator 16. ΔT.sub.1 and ΔT.sub.2 are the capacitor charging and discharging times, respectively. The output frequency of the relaxation oscillator 16 is obtained according to Equation 6, being a function of I.sub.1, I.sub.2, ΔV (and implicitly a function of V.sub.DD through Equation 3), and C.sub.t.

[0054] From Equation 6, if I.sub.1, I.sub.2, V.sub.DD are known or can be accurately measured (assuming R.sub.1, R.sub.2, R.sub.3 are accurately known from the design of the circuit, which permits the accurate calculation of V.sub.UTH, V.sub.LTH, and ΔV according to Equations 1, 2, and 3), and if the output frequency of the relaxation oscillator 16 can be measured accurately, then the capacitance under test C.sub.t can be obtained as:

[00002]$\begin{array}{cc}{C}_t=\frac{I_1{I}_2}{f_{\mathrm{OUT}}.Math.\Delta V\left(I_1+I_2\right)}& \mathrm{Equation}7\end{array}$

where ΔV is given by Equation 3. In accordance with embodiments described herein, the measurement block 18 in FIG. 2, 3A, or 4 performs the measurement of I.sub.1, I.sub.2, V.sub.DD, and f.sub.OUT and calculates C.sub.t using Equation 7 and the known values of R.sub.1, R.sub.2, R.sub.3.

[0055] FIG. 7 is a schematic diagram of an exemplary comparator COMP for the relaxation oscillator 16 of FIG. 5. This illustrates a complementary metal-oxide-semiconductor (CMOS) implementation of the comparator COMP using field-effect transistors (FETs), though the comparator COMP may also be implemented using bipolar junction transistors (BJTs) or other types of transistors. The inverting input is connected to the gate of a first transistor M.sub.1 (e.g., a p-type MOSFET (PMOS)) and the noninverting input is connected to the gate of a second transistor M.sub.2 (e.g., a PMOS). The first transistor M.sub.1 is connected in series with a complementary third transistor M.sub.3 (e.g., an n-type MOSFET (NMOS)), which is connected to ground. Similarly, the second transistor M.sub.2 is connected in series with a complementary fourth transistor M.sub.4 (e.g., an NMOS), which is connected to ground. The gates of the third transistor M.sub.3 and the fourth transistor M.sub.4 are connected to the gates of a corresponding fifth transistor M.sub.5 and sixth transistor M.sub.6, respectively. These gates are further connected to the corresponding drains of the third transistor M.sub.3 and the fourth transistor M.sub.4.

[0056] The fifth transistor M.sub.5 is connected in series with a complementary seventh transistor M.sub.7 (e.g., a PMOS), which is connected to the supply voltage V.sub.DD. Similarly, the sixth transistor M.sub.6 is connected in series with a complementary eight transistor M.sub.8 (e.g., a PMOS), which is connected to the supply voltage V.sub.DD. The gates of the seventh transistor M.sub.7 and the eighth transistor M.sub.8 are connected together and to the drain of the seventh transistor M.sub.7.

[0057] Finally, a ninth transistor M.sub.9 (e.g., a PMOS) is connected between the supply voltage V.sub.DD and the sources of the first transistor M.sub.1 and the second transistor M.sub.2. The output V.sub.OUT of the comparator COMP is connected to the drain of the ninth transistor M.sub.9 and the sources of the first transistor M.sub.1 and the second transistor M.sub.2. A bias signal bias for the comparator COMP is connected to the gate of the ninth transistor M.sub.9.

[0058] FIG. 8 is a schematic diagram of another exemplary embodiment of the measurement circuit 12 of FIG. 2. Copies I.sub.1c, I.sub.2c, of the charging and discharging currents I.sub.1, I.sub.2, respectively, of the relaxation oscillator 16 are fed to the measurement block 18. The measurement block 18 includes voltage measurement circuitry 28, current measurement circuitry 30, and frequency measurement circuitry 32. These circuits are selectively connected using voltage measurement switch sw.sub.VM (controlled by signal VCVM), current measurement switch sw.sub.IM (controlled by signal VCIM), and frequency measurement switch sw.sub.FM (controlled by signal VCFM).

[0059] When current measurement switch sw.sub.IM is closed (e.g., signal VCIM is logic 1), the currents to be measured are selected by control signal VCID. More specifically, if VCID is at logic 0, then sw.sub.snk1,.Math.sw.sub.src1b are closed and sw.sub.snk1b,.Math.sw.sub.src1 are open, which connects I.sub.2c to the measurement block 18 (e.g., the current measurement circuitry 30). If VCID is at logic 1, then sw.sub.snk1,.Math.sw.sub.src1b are open and sw.sub.snk1v,.Math.sw.sub.src1 are closed, which connects I.sub.1c to the measurement block 18.

[0060] In the configuration shown in FIG. 8, it is not necessary to stop the relaxation oscillator 16 from oscillating when measuring I.sub.1c and I.sub.2c because these currents are copies of the actual charging and discharging currents I.sub.1 and I.sub.2 of the relaxation oscillator 16 and have no effect on its actual operation. Therefore, the configuration of FIG. 8 allows a rapid measurement of all the quantities needed in the calculation of C.sub.t from Equation 7.

[0061] FIG. 9 is a schematic diagram of another exemplary embodiment of the measurement circuit 12 of FIG. 2. Here, the actual charging and discharging currents I.sub.1, I.sub.2 of the relaxation oscillator 16 are fed to the measurement block 18. In this way, the measurement accuracy of capacitance C.sub.t is improved by eliminating the errors associated with copying currents I.sub.1, I.sub.2 (which was illustrated in FIG. 8). To achieve this, control signal VCCT set to logic 0 performs the essential function of stopping the oscillation of the relaxation oscillator 16 by disconnecting the inputs of comparator COMP and feedback resistor R.sub.3 from the relaxation oscillator feedback loop (by opening switches sw.sub.osc1, sw.sub.osc2, and sw.sub.R3), and allowing forced large DC voltages to be applied to the inputs of the comparator COMP by closing switches sw.sub.en1b and sw.sub.en2b.

[0062] The polarity of the forced large DC voltages is controlled by signal VCTI and its associated control inverter INV.sub.f1. Thus, when VCTI is at logic 0, the output of INV.sub.f1 is at logic 1, switches sw.sub.fin1, sw.sub.fin3 are open, sw.sub.fin2, sw.sub.fin4 are closed, the noninverting input of the comparator COMP is at ground, the inverting input of the comparator COMP is at V.sub.DD, causing the output V.sub.OUT to be at ground, thus closing sw.sub.I1b, sw.sub.I2, opening sw.sub.I1, sw.sub.I2b, in this way sending I.sub.2 to the measurement block 18 as a sink current. When VCTI is at logic 1, the output of INV.sub.f1 is at logic 0, switches sw.sub.fin1, sw.sub.fin3 are closed, sw.sub.fin2, sw.sub.fin4 are open, the noninverting input of the comparator COMP is at V.sub.DD, the inverting input of the comparator COMP is at ground, causing the output V.sub.OUT to be at V.sub.DD, thus opening sw.sub.I1b, sw.sub.I2, closing sw.sub.I1, sw.sub.I2b, in this way sending I.sub.1 to the measurement block 18 as a source current.

[0063] Unlike in FIG. 8, in the embodiment of FIG. 9 it is necessary to stop the relaxation oscillator 16 from oscillating when measuring currents I.sub.1, I.sub.2, therefore the frequency measurement cannot be done at the same time as measuring I.sub.1, I.sub.2, which causes the overall measurement process to be slower. However, there is improved accuracy relative to embodiment of FIG. 8, because the errors associated with current copying are eliminated.

[0064] FIG. 10 is a flow diagram of a tuning algorithm for the tuning circuit 24 of FIG. 4. This algorithm is described with reference to the capacitance measurement approaches described above with respect to FIG. 8 and FIG. 9. The algorithm begins with disconnecting the crystal oscillator core 20 from the integrated circuit 10 (block 1000). Adjustable capacitor C.sub.2 is then connected to the relaxation oscillator 16 and set to its minimum value (block 1002). The voltage, currents and frequency are measured and used to calculate the minimum value of C.sub.2 (block 1004).

[0065] C.sub.2 is connected to the relaxation oscillator 16 and set to its maximum value (block 1006). The voltage, currents and frequency are measured and used to calculate the maximum value of C.sub.2 (block 1008). The C.sub.2 minimum capacitance step value C.sub.2STEP is then calculated (block 1010). By design, C.sub.2STEP is the same as the C.sub.1 minimum capacitance step value C.sub.1STEP.

[0066] Adjustable capacitor C.sub.1 is then connected to the relaxation oscillator 16 and set to its minimum value (block 1012). The board parasitic capacitance C.sub.P is present as it is connected to C.sub.1. The voltage, currents and frequency are measured and used to calculate the minimum value of (C.sub.1+C.sub.P) (block 1014). C.sub.1CODE is calculated such that the minimum value of (C.sub.1+C.sub.P+C.sub.2LSB*C.sub.1CODE) is the target load capacitance for the crystal oscillator core 20 (block 1016). Finally, the value of C.sub.1 is set using C.sub.1CODE (block 1018).

[0067] FIG. 11 is a flow diagram of a process for measuring on-chip capacitance. Dashed boxes represent optional steps. The process begins at operation 1100, with disconnecting a target capacitance from a main circuit of an integrated circuit. In an exemplary aspect, the target capacitance is disconnected from the main circuit simultaneously with connecting the target capacitance to the relaxation oscillator. The process continues at operation 1102, with connecting the target capacitance to a relaxation oscillator on the integrated circuit.

[0068] The process continues at operation 1104, with measuring an output of the relaxation oscillator. The measured output may be one or more of a voltage (e.g., threshold voltage), a current (e.g., currents through the relaxation oscillator), or a frequency (e.g., a frequency of an output of the relaxation oscillator). The process continues at operation 1106, with measuring the target capacitance based on the measured output. The process optionally continues at operation 1108, with tuning the target capacitance based on the measured target capacitance.

[0069] In an exemplary aspect, the target capacitance includes two capacitors associated with a crystal oscillator. As described above with respect to FIG. 10, the capacitances of the two capacitors may be measured in sequence, beginning with the second capacitor C.sub.2 which is not connected to the parasitic capacitance C.sub.P. One or both of the capacitors may be tuned based on the measured capacitances.

[0070] Although the operations of FIGS. 10 and 11 are illustrated in a series, this is for illustrative purposes and the operations are not necessarily order dependent. Some operations may be performed in a different order than that presented. For example, operations 1100 and 1102 may be performed simultaneously. Further, processes within the scope of this disclosure may include fewer or more steps than those illustrated in FIGS. 10 and 11.

[0071] FIG. 12 is a block diagram of a computer system 1200 suitable for implementing on-chip capacitance measurement and/or tuning according to embodiments disclosed herein. The computer system 1200 comprises any computing or electronic device capable of including firmware, hardware, and/or executing software instructions that could be used to perform any of the methods or functions described above. In this regard, the computer system 1200 may be a circuit or circuits included in an electronic board card, such as a printed circuit board (PCB), a server, a personal computer, a desktop computer, a laptop computer, an array of computers, a personal digital assistant (PDA), a computing pad, a mobile device, or any other device, and may represent, for example, a server or a user's computer.

[0072] The exemplary computer system 1200 in this embodiment includes a processing device 1202 or processor, a system memory 1204, and a system bus 1206. The processing device 1202 represents one or more commercially available or proprietary general-purpose processing devices, such as a microprocessor, central processing unit (CPU), or the like. More particularly, the processing device 1202 may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, a processor implementing other instruction sets, or other processors implementing a combination of instruction sets. The processing device 1202 is configured to execute processing logic instructions for performing the operations and steps discussed herein.

[0073] In this regard, the various illustrative logical blocks, modules, and circuits described in connection with the embodiments disclosed herein may be implemented or performed with the processing device 1202, which may be a microprocessor, field programmable gate array (FPGA), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), or other programmable logic device, a discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. Furthermore, the processing device 1202 may be a microprocessor, or may be any conventional processor, controller, microcontroller, or state machine. The processing device 1202 may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0074] The system memory 1204 may include non-volatile memory 1208 and volatile memory 1210. The non-volatile memory 1208 may include read-only memory (ROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), and the like.

[0075] The volatile memory 1210 generally includes random-access memory (RAM) (e.g., dynamic random-access memory (DRAM), such as synchronous DRAM (SDRAM)). A basic input/output system (BIOS) 1212 may be stored in the non-volatile memory 1208 and can include the basic routines that help to transfer information between elements within the computer system 1200.

[0076] The system bus 1206 provides an interface for system components including, but not limited to, the system memory 1204 and the processing device 1202. The system bus 1206 may be any of several types of bus structures that may further interconnect to a memory bus (with or without a memory controller), a peripheral bus, and/or a local bus using any of a variety of commercially available bus architectures.

[0077] The computer system 1200 may further include or be coupled to a non-transitory computer-readable storage medium, such as a storage device 1214, which may represent an internal or external hard disk drive (HDD), flash memory, or the like. The storage device 1214 and other drives associated with computer-readable media and computer-usable media may provide non-volatile storage of data, data structures, computer-executable instructions, and the like. Although the description of computer-readable media above refers to an HDD, it should be appreciated that other types of media that are readable by a computer, such as optical disks, magnetic cassettes, flash memory cards, cartridges, and the like, may also be used in the operating environment, and, further, that any such media may contain computer-executable instructions for performing novel methods of the disclosed embodiments.

[0078] An operating system 1216 and any number of program modules 1218 or other applications can be stored in the volatile memory 1210, wherein the program modules 1218 represent a wide array of computer-executable instructions corresponding to programs, applications, functions, and the like that may implement the functionality described herein in whole or in part, such as through instructions 1220 on the processing device 1202. The program modules 1218 may also reside on the storage mechanism provided by the storage device 1214. As such, all or a portion of the functionality described herein may be implemented as a computer program product stored on a transitory or non-transitory computer-usable or computer-readable storage medium, such as the storage device 1214, volatile memory 1210, non-volatile memory 1208, instructions 1220, and the like. The computer program product includes complex programming instructions, such as complex computer-readable program code, to cause the processing device 1202 to carry out the steps necessary to implement the functions described herein.

[0079] An operator, such as the user, may also be able to enter one or more configuration commands to the computer system 1200 through a keyboard, a pointing device such as a mouse, or a touch-sensitive surface, such as the display device, via an input device interface 1222 or remotely through a web interface, terminal program, or the like via a communication interface 1224. The communication interface 1224 may be wired or wireless and facilitate communications with any number of devices via a communications network in a direct or indirect fashion. An output device, such as a display device, can be coupled to the system bus 1206 and driven by a video port 1226. Additional inputs and outputs to the computer system 1200 may be provided through the system bus 1206 as appropriate to implement embodiments described herein.

[0080] The operational steps described in any of the exemplary embodiments herein are described to provide examples and discussion. The operations described may be performed in numerous different sequences other than the illustrated sequences. Furthermore, operations described in a single operational step may actually be performed in a number of different steps. Additionally, one or more operational steps discussed in the exemplary embodiments may be combined.

[0081] Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.