FORMING CONTROL METHOD APPLIED TO RESISTIVE RANDOM-ACCESS MEMORY CELL ARRAY

Abstract

A forming control method for a resistive random-access memory cell array is provided. While a forming action of the resistive random-access memory cell array is performed, a verification action is performed to judge whether the forming action on the resistive random-access memory cells has been successfully done. By properly changing a forming voltage or a pulse width, the forming actions on all of the resistive random-access memory cells of the resistive random-access memory cell array can be successfully done.

Claims

1. A forming control method for a resistive random-access memory cell array, the resistive random-access memory cell array comprising m resistive random-access memory cells, m being a positive integer, the forming control method comprising steps of: (a) setting i as 1; (b) providing an initial value of a forming voltage; (c) generating a forming pulse according to the forming voltage, and performing a forming action on an i-th resistive random-access memory cell of the resistive random-access memory cell array according to the forming pulse; (d) performing a verification action on the i-th resistive random-access memory cell, and judging whether the i-th resistive random-access memory cell passes the verification action; (e) if the i-th resistive random-access memory cell does not pass the verification action and a change number of the forming voltage provided to the i-th resistive random-access memory cell does not reach a preset value, increasing the forming voltage and performing the step (c) again; (f) if the i-th resistive random-access memory cell does not pass the verification action and the change number of the forming voltage provided to the i-th resistive random-access memory cell reaches the preset value, increasing i by 1 and performing the step (c) again; (g) if the i-th resistive random-access memory cell passes the verification action and i is not equal to m, increasing i by 1 and performing the step (c) again; and (h) if the i-th resistive random-access memory cell passes the verification action and i is equal to m, ending the forming control method.

2. The forming control method as claimed in claim 1, wherein the forming pulse has a pulse width and a pulse height, wherein the pulse height is equal to a voltage level of the forming voltage.

3. The forming control method as claimed in claim 1, wherein the resistive random-access memory cell array is an mx1 resistive random-access memory cell array, and the i-th resistive random-access memory cell comprises: a resistive element, wherein a first terminal of the resistive element is connected to a bit line; and a select transistor, wherein a first drain/source terminal of the select transistor is connected to a second terminal of the resistive element, a second drain/source terminal of the select transistor is connected to a source line, and a gate terminal of the select transistor is connected to an i-th word line.

4. The forming control method as claimed in claim 3, wherein when the forming action is performed on the i-th resistive random-access memory cell, an on voltage is provided to the i-th word line, the forming pulse is provided to the bit line, and a ground voltage is provided to the source line.

5. The forming control method as claimed in claim 4, wherein when the verification action is performed on the i-th resistive random-access memory cell, the on voltage is provided to the i-th word line, a read voltage is provided to the i-th resistive random-access memory cell, wherein a control circuit judges whether the i-th resistive random-access memory cell passes the verification action according to a read current generated by the i-th resistive random-access memory cell.

6. The forming control method as claimed in claim 5, wherein if the read current is higher than a reference current, the control circuit judges that the i-th resistive random-access memory cell passes the verification action, wherein if the read current is lower than the reference current, the control circuit judges that the i-th resistive random-access memory cell does not pass the verification action.

7. The forming control method as claimed in claim 1, wherein if a judging condition of the step (f) is satisfied, it is determined that the i-th resistive random-access memory cell is a bad cell.

8. The forming control method as claimed in claim 1, wherein if a judging condition of the step (e) is satisfied, the forming voltage plus an increment voltage is updated as a new value of the forming voltage.

9. A forming control method for a resistive random-access memory cell array, the forming control method comprising steps of: (a) providing an initial value of a forming voltage; (b) providing an initial value of a pulse width; (c) generating a forming pulse according to the forming voltage and the pulse width, and performing a forming action on plural resistive random-access memory cells in a selected row of the resistive random-access memory cell array according to the forming pulse (d) judging whether all of the plural resistive random-access memory cells in the selected row pass a verification action; (e) if all of the plural resistive random-access memory cells in the selected row pass the verification action, determining a next selected row and performing the step (b) again; (f) if not all of the plural resistive random-access memory cells in the selected row pass the verification action and a change number of the pulse width does not reach a first preset value, increasing the pulse width and performing the step (c) again; (g) if not all of the plural resistive random-access memory cells in the selected row pass the verification action, the change number of the pulse width reaches the first preset value and a change number of the forming voltage does not reach a second preset value, increasing the forming voltage and performing the step (b) again; and (h) if not all of the plural resistive random-access memory cells in the selected row pass the verification action, the change number of the pulse width reaches the first preset value and the change number of the forming voltage reaches the second preset value, determining the next selected row and performing the step (b) again.

10. The forming control method as claimed in claim 9, wherein the step (c) further comprises: performing the forming action on the plural resistive random-access memory cells in the selected row according to the forming pulse, and the plural resistive random-access memory cells have not passed the verification action.

11. The forming control method as claimed in claim 9, wherein the forming pulse has a pulse height, and the pulse height is equal to a voltage level of the forming voltage.

12. The forming control method as claimed in claim 9, wherein the resistive random-access memory cell array being an mxn resistive random-access memory cell array, and the selected row contains n resistive random-access memory cells, wherein a first resistive random-access memory cell of the n resistive random-access memory cells comprises: a resistive element, wherein a first terminal of the resistive element is connected to a first bit line; and a select transistor, wherein a first drain/source terminal of the select transistor is connected to a second terminal of the resistive element, a second drain/source terminal of the select transistor is connected to a first source line, and a gate terminal of the select transistor is connected to a first word line.

13. The forming control method as claimed in claim 12, wherein when the forming action is performed on the first resistive random-access memory cell, an on voltage is provided to the first word line, the forming pulse is provided to the first bit line, and a ground voltage is provided to the first source line.

14. The forming control method as claimed in claim 13, wherein when the verification action is performed on the first resistive random-access memory cell, the on voltage is provided to the first word line, a read voltage is provided to the first resistive random-access memory cell, wherein a control circuit judges whether the first resistive random-access memory cell passes the verification action according to a read current generated by the first resistive random-access memory cell.

15. The forming control method as claimed in claim 14, wherein if the read current is higher than a reference current, the control circuit judges that the first resistive random-access memory cell passes the verification action, wherein if the read current is lower than the reference current, the control circuit judges that the first resistive random-access memory cell does not pass the verification action.

16. The forming control method as claimed in claim 12, wherein the step of determining the next selected row is continuously performed until the forming action on the n resistive random-access memory cells in an m-th row of the resistive random-access memory cell array is completed, wherein after the forming action on the n resistive random-access memory cells in the m-th row of the resistive random-access memory cell array is completed, the forming control method is ended.

17. The forming control method as claimed in claim 12, wherein the step (h) further comprises sub-steps of: (h1) if a number of the resistive random-access memory cells in the selected row failing to pass the verification action is smaller than a threshold value, determining the next selected row, and performing the step (b) again; and (h2) if the number of the resistive random-access memory cells in the selected row failing to pass the verification action is larger than or equal to the threshold value, confirming the selected row is a failed row, determining the next selected row, and performing the step (b) again.

18. The forming control method as claimed in claim 9, wherein if a judging condition of the step (g) is satisfied, the forming voltage plus an increment voltage is updated as a new value of the forming voltage.

19. The forming control method as claimed in claim 9, wherein after performing the steps (f) and (g), the step (c) further comprises: performing the forming action on the plural resistive random-access memory cells in the selected row that have not passed the verification action and inhibit the plural resistive random-access memory cells in the selected row that have passed the verification action.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0043] The above objects and advantages of the present invention will become more readily apparent to those ordinarily skilled in the art after reviewing the following detailed description and accompanying drawings, in which:

[0044] FIG. 1 (prior art) schematically illustrates the structure of a conventional resistive element;

[0045] FIG. 2 (prior art) is a schematic equivalent circuit diagram illustrating a resistive random-access memory cell array;

[0046] FIGS. 3A, 3B and 3C (prior art) are schematic circuit diagrams illustrating a conventional forming control method for the resistive random-access memory cell array;

[0047] FIGS. 4A, 4B and 4C (prior art) are schematic circuit diagrams illustrating another conventional forming control method for the resistive random-access memory cell array;

[0048] FIGS. 5A, 5B and 5C (prior art) are schematic circuit diagrams illustrating another conventional forming control method for the resistive random-access memory cell array;

[0049] FIG. 6A is a flowchart of a forming control method for a resistive random-access memory cell array according to a first embodiment of the present invention;

[0050] FIG. 6B is a statistical graph illustrating the relationships between the number of forming actions performed on the resistive memory cells of the resistive random-access memory cell array and the corresponding forming voltages by using the forming control method of FIG. 6A;

[0051] FIG. 7A is a flowchart of a forming control method for a resistive random-access memory cell array according to a second embodiment of the present invention;

[0052] FIG. 7B is a statistical graph illustrating the relationships between the number of forming actions performed on the resistive memory cells of the resistive random-access memory cell array and the corresponding forming voltages by using the forming control method of FIG. 7A;

[0053] FIG. 8A is a schematic circuit diagram illustrating a resistive random-access memory according to an embodiment of the present invention; and

[0054] FIG. 8B is a flowchart of a forming control method for a resistive random-access memory cell array according a third embodiment of the present invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

[0055] As mentioned above, the conventional forming control method for the resistive random-access memory cell array has some drawbacks. For example, as the number of the resistive random-access memory cells that have successfully undergone the forming action gradually increases, the leakage current on the source line gradually increases, and the bit line voltage gradually decreases. Consequently, the subsequent forming actions on the other resistive random-access memory cells are adversely affected.

[0056] For solving the drawbacks of the conventional technologies, the present invention provides a novel forming control method for a resistive random-access memory cell array. In accordance with a feature of the present invention, the forming voltage V.sub.form or the pulse width w of the forming pulse is adjusted. Consequently, the forming actions on all of the resistive random-access memory cells of the resistive random-access memory cell array can be successfully done.

[0057] FIG. 6A is a flowchart of a forming control method for a resistive random-access memory cell array according to a first embodiment of the present invention. After the forming control method is started, set i = 1 (Step S602). Then, an initial value of a forming voltage V.sub.form is provided (Step S604). Then, a forming pulse is generated according to the forming voltage V.sub.form, and the resistive random-access memory cells ci~cm are sequentially subjected to forming actions according to the forming pulse (Step S606).

[0058] Then, a step S608 is performed to judge whether the resistive random-access memory cell ci passes a verification action. If the resistive random-access memory cell ci passes the verification action, a step S610 is performed to judge whether the resistive random-access memory cell ci is the last resistive random-access memory cell (i.e., i is equal to m). If the judging condition of the step S610 is not satisfied, i = I + 1 (Step S612) and the step S608 is repeatedly done. If the judging result of the step S608 indicates that the resistive random-access memory cell ci passes the verification action and the judging result of the step S610 indicates that the resistive random-access memory cell ci is the last resistive random-access memory cell (i.e., i = m), the flowchart is ended.

[0059] If the judging result of the step S608 indicates that the resistive random-access memory cell ci fails to pass the verification action, the forming voltage V.sub.form is increased (Step S614) and the step S606 is repeatedly done. For example, the initial forming voltage V.sub.form is increased by one increment voltage ΔV. That is, V.sub.form = V.sub.form + ΔV.

[0060] For example, the forming control method of this embodiment can be applied to the resistive random-access memory cell array as shown in FIG. 5A. The resistive random-access memory cell array comprises m×1 resistive random-access memory cells c1~cm. For example, m is 1024. That is, the resistive random-access memory cell array comprises 1024 word lines WL1~WL1024.

[0061] FIG. 6B is a statistical graph illustrating the relationships between the number of forming actions performed on the resistive memory cells of the resistive random-access memory cell array and the corresponding forming voltages by using the forming control method of FIG. 6A. For example, the initial value of a forming voltage V.sub.form is 2.8 V, and the increment voltage ΔV is 0.2 V.

[0062] After the forming control method of the first embodiment is started, the value i is equal to 1 and the initial value of the forming voltage V.sub.form is 2.8 V (see the statistical graph of FIG. 6B). The on voltage V.sub.on is provided to the word lines WL1~WL1024 sequentially. Consequently, the resistive random-access memory cells c1~c1024 are subjected to a first forming action (1 st).

[0063] Meanwhile, the value i is equal to 1. After the resistive random-access memory cells c1~c1024 are subjected to the first forming action, the verification action is performed on the resistive random-access memory cell c1. Since the resistive random-access memory cell c1 passes the verification action, i is added by 1 (i.e., i = 2). Then, the verification action is performed on the resistive random-access memory cell c2. The rest may be deduced by analog. That is, the verification action is performed on the following resistive random-access memory cells sequentially.

[0064] Please refer to FIG. 6B again. When i is equal to 21, the resistive random-access memory cell c21 fails to pass the verification action. Then, the forming voltage V.sub.form is increased to 3.0 V (i.e., 2.8 V + 0.2 V = 3.0 V). The forming pulse is generated according to the forming voltage V.sub.form of 3.0 V. The on voltage V.sub.on is provided to the word lines WL21~WL1024 sequentially. Consequently, the resistive random-access memory cells c21~c1024 are subjected to a second forming action (2nd).

[0065] Meanwhile, the value i is equal to 21. After the resistive random-access memory cells c21~c1024 are subjected to the second forming action, the verification action is performed on the resistive random-access memory cell c21. In addition, the verification action is performed on the following resistive random-access memory cells sequentially.

[0066] Please refer to FIG. 6B again. When i is equal to 150, the resistive random-access memory cell c150 fails to pass the verification action. Then, the forming voltage V.sub.form is increased to 3.2 V (i.e., 3.0 V + 0.2 V = 3.2 V). The forming pulse is generated according to the forming voltage V.sub.form of 3.2 V. The on voltage V.sub.on is provided to the word lines WL150-WL1024 sequentially. Consequently, the resistive random-access memory cells c150~c1024 are subjected to a third forming action (3rd).

[0067] Meanwhile, the value i is equal to 150. After the resistive random-access memory cells c150~c1024 are subjected to the second forming action, the verification action is performed on the resistive random-access memory cell c150. In addition, the verification action is performed on the following resistive random-access memory cells sequentially.

[0068] Similarly, when i is equal to 510, the resistive random-access memory cell c510 fails to pass the verification action. Consequently, the forming voltage V.sub.form is increased to 3.4 V, and the resistive random-access memory cells c510~c1024 are subjected to a fourth forming action (4th). Similarly, when i is equal to 775, the resistive random-access memory cell c775 fails to pass the verification action. Consequently, the forming voltage V.sub.form is increased to 3.6 V, and the resistive random-access memory cells c775~c1024 are subjected to a fifth forming action (5th).

[0069] Afterwards, the forming voltage V.sub.form is increased to 3.8 V. The forming pulse is generated according to the forming voltage V.sub.form of 3.8 V. Consequently, the resistive random-access memory cells c930~c1024 are subjected to a sixth forming action (6th). Then, all of the resistive random-access memory cells c930~c1024 pass the verification action.

[0070] After the flowchart of the above forming control method is completed, it is confirmed that all of the resistive random-access memory cells c1~c1024 pass the verification action successfully. Then, the flowchart of the forming control method is ended.

[0071] However, the forming control method of the first embodiment still has some drawbacks. For example, since many resistive random-access memory cells are subjected to the forming actions for many times, the forming control method is time-consuming. For example, the resistive random-access memory cells c930~c1024 need to undergo the forming actions for six times. In other words, the forming control method of the first embodiment needs to be modified.

[0072] FIG. 7A is a flowchart of a forming control method for a resistive random-access memory cell array according to a second embodiment of the present invention. After the forming control method is started, set i = 1 (Step S702). Then, an initial value of a forming voltage V.sub.form is provided (Step S704). Then, a forming pulse is generated according to the forming voltage V.sub.form, and the resistive random-access memory cell ci is subjected to a forming action according to the forming pulse (Step S706).

[0073] Then, a step S708 is performed to judge whether the resistive random-access memory cell ci passes a verification action. If the resistive random-access memory cell ci passes the verification action, a step S710 is performed to judge whether the resistive random-access memory cell ci is the last resistive random-access memory cell (i.e., i is equal to m). If the judging condition of the step S710 is not satisfied, i = i + 1 (Step S712) and the step S706 is repeatedly done. If the judging result of the step S708 indicates that the resistive random-access memory cell ci passes the verification action and the judging result of the step S710 indicates that the resistive random-access memory cell ci is the last resistive random-access memory cell (i.e., i = m), the flowchart is ended.

[0074] If the judging result of the step S708 indicates that the resistive random-access memory cell ci fails to pass the verification action, a step S714 is performed to judge whether the change number of the forming voltage V.sub.form reaches a preset value. If the judging condition of the step S714 is not satisfied, the forming voltage V.sub.form is increased (Step S716) and the step S706 is repeatedly done. For example, the initial forming voltage V.sub.form is increased by one increment voltage ΔV. That is, V.sub.form = V.sub.form + ΔV. If the judging condition of the step S714 is satisfied, it is confirmed that the resistive random-access memory cell ci is a bad cell, and the step S712 is performed.

[0075] For example, the forming control method of this embodiment can be applied to the resistive random-access memory cell array as shown in FIG. 5A. The resistive random-access memory cell array comprises m×1 resistive random-access memory cells c1~cm. For example, m is 1024. That is, the resistive random-access memory cell array comprises 1024 word lines WL1~WL1024.

[0076] FIG. 7B is a statistical graph illustrating the relationships between the number of forming actions performed on the resistive memory cells of the resistive random-access memory cell array and the corresponding forming voltages by using the forming control method of FIG. 7A. For example, the initial value of a forming voltage V.sub.form is 2.8 V, and the increment voltage ΔV is 0.2 V. In an embodiment, the preset value corresponding to the change number of the forming voltage V.sub.form is 1.

[0077] After the forming control method of the first embodiment is started, the value i is equal to 1 and the initial value of the forming voltage V.sub.form is 2.8 V (see the statistical graph of FIG. 7B). Then, the resistive random-access memory cell c1 is subjected to a forming action and a verification action according to the forming pulse with the pulse height of 2.8 V. If the resistive random-access memory cell c1 passes the verification action, i is added by 1 (i.e., i = 2). Then, the resistive random-access memory cell c2 is subjected to the forming action and the verification action according to the forming pulse with the pulse height of 2.8 V. The rest may be deduced by analog.

[0078] Please refer to FIG. 7B again. When i is equal to 21, the resistive random-access memory cell c21 is subjected to the forming action according to the forming pulse with the pulse height of 2.8 V. However, the resistive random-access memory cell c21 fails to pass the verification action. Since the forming voltage V.sub.form provided to the resistive random-access memory cell c21 does not reach the preset value corresponding to the change number of the forming voltage V.sub.form (i.e., 1), the forming voltage V.sub.form is increased to 3.0 V (i.e., 2.8 V + 0.2 V = 3.0 V). The forming pulse is generated according to the forming voltage V.sub.form of 3.0 V. Then, the resistive random-access memory cell c21 is subjected to a forming action and a verification action according to the forming pulse with the pulse height of 3.0 V. If the resistive random-access memory cell c21 passes the verification action, i is added by 1 (i.e., i = 22). Then, the resistive random-access memory cell c22 is subjected to the forming action and the verification action according to the forming pulse with the pulse height of 3.0 V. The rest may be deduced by analog.

[0079] Please refer to FIG. 7B again. When i is equal to 150, the resistive random-access memory cell c150 is subjected to the forming action according to the forming pulse with the pulse height of 3.0 V. However, the resistive random-access memory cell c150 fails to pass the verification action. Since the forming voltage V.sub.form provided to the resistive random-access memory cell c150 does not reach the preset value corresponding to the change number of the forming voltage V.sub.form (i.e., 1), the forming voltage V.sub.form is increased to 3.2 V (i.e., 3.0 V + 0.2 V = 3.2 V). The forming pulse is generated according to the forming voltage V.sub.form of 3.2 V. Then, the resistive random-access memory cell c150 is subjected to a forming action and a verification action according to the forming pulse with the pulse height of 3.2 V. If the resistive random-access memory cell c150 passes the verification action, i is added by 1 (i.e., i = 151). Then, the resistive random-access memory cell c151 is subjected to the forming action and the verification action according to the forming pulse with the pulse height of 3.2 V. The rest may be deduced by analog. Similarly, when i is equal to 510, the resistive random-access memory cell c510 fails to pass the verification action. Consequently, the forming voltage V.sub.form is increased to 3.4 V. Similarly, when i is equal to 775, the resistive random-access memory cell c775 fails to pass the verification action. Consequently, the forming voltage V.sub.form is increased to 3.6 V.

[0080] Afterwards, the forming voltage V.sub.form is increased to 3.8 V. The forming pulse is generated according to the forming voltage V.sub.form of 3.8 V. After the resistive random-access memory cells c930~c1024 are subjected to the forming action and the verification action, it is confirmed that the resistive random-access memory cells c930~c1024 pass the verification actions.

[0081] After the flowchart of the above forming control method is completed, it is confirmed that all of the resistive random-access memory cells c1~c1024 pass the verification action successfully. Then, the flowchart of the forming control method is ended.

[0082] As mentioned above descriptions, the forming control method of the second embodiment is advantageous over the forming control method of the first embodiment. For example, since the number of forming actions that the resistive random-access memory cells are subjected to the forming actions is reduced, the time period of implementing the forming control method of the second embodiment is largely reduced. It is noted that the preset value corresponding to the change number of the forming voltage V.sub.form is not restricted. For example, if the preset value is 2, each resistive random-access memory cell is subjected to the forming action for at most three times.

[0083] As mentioned above, the forming control method of the first embodiment and the forming control method of the second embodiment can be applied to the m×1 resistive random-access memory cell array to perform the forming actions on a column of resistive random-access memory cells.

[0084] The forming control method of the present invention can be also applied to the 1×n resistive random-access memory cell array. Under this circumstance, the number “m” in the step S710 is replaced by the number “n”. After the word line WL1 receives the on voltage V.sub.on, a forming pulse is provided to the bit lines BL1~BLn sequentially. Consequently, a row of resistive random-access memory cells can be subjected to the forming actions.

[0085] Similarly, the forming control method of the first embodiment and the forming control method of the second embodiment can be applied to the m×n resistive random-access memory cell array. After m resistive random-access memory cells in a first column are subjected to the forming actions, the m resistive random-access memory cells in a second column are subjected to the forming actions. The rest may be deduced by analog. After the m resistive random-access memory cells in the n-th column are subjected to the forming actions, the forming control method is completed. Alternatively, after n resistive random-access memory cells in a first row are subjected to the forming actions, the n resistive random-access memory cells in a second row are subjected to the forming actions. The rest may be deduced by analog. After the n resistive random-access memory cells in the m-th column are subjected to the forming actions, the forming control method is completed.

[0086] In the first embodiment and the second embodiment, the pulse height of the forming pulse is according to the forming voltage V.sub.form. That is, the pulse width w is not changed. In some other embodiment, the pulse width is changeable.

[0087] FIG. 8A is a schematic circuit diagram illustrating a resistive random-access memory according to an embodiment of the present invention. As shown in FIG. 8A, the resistive random-access memory comprises a control circuit 810, a resistive random-access memory cell array, a sense amplifier (SA) 860, a word line selector 820, a bit line selector 830 and a source line selector 840. The resistive random-access memory cell array is an m×n resistive random-access memory cell array, wherein m and n are positive integers. For example, m is equal to 1024, and n is equal to 2048. The structure of the resistive random-access memory cell array is identical to that of FIG. 2, and not redundantly described herein.

[0088] The control circuit 810 generates the word line select signal WL.sub.sel, the bit line select signal BL.sub.sel and the source line select signal SL.sub.sel to determine the selected memory cell of the resistive random-access memory cell array. Moreover, the control circuit 810 can perform the forming action, the set action, the reset action, read action and the verification action on the selected memory cell.

[0089] In an embodiment, the control circuit 810 comprises a pulse width controller 816 and a voltage generator 814. For example, when the forming action is performed, the operation voltage V.sub.OP generated by the voltage generator 814 is the forming voltage V.sub.form and the pulse width controller 816 generates the pulse width control signal W.sub.ctrl. Consequently, the forming action on the selected memory cell is performed. Similarly, when the set action is performed, the operation voltage V.sub.OP generated by the voltage generator 814 is the set voltage, and the selected memory cell undergoes the set action. When the reset action is performed, the operation voltage V.sub.OP generated by the voltage generator 814 is the reset voltage, and the selected memory cell undergoes the reset action.

[0090] The control circuit 810 further comprises a verification controller 812 receives the storage state signal S.sub.s and judges whether the selected memory cell passes the verification action according to the storage state signal S.sub.s. In addition, the verification controller 812 can control the voltage generator 814 to change the operation voltage V.sub.OP (i.e., forming voltage V.sub.form) or control the pulse width controller 816 to change the pulse width control signal W.sub.ctrl during the forming action.

[0091] The word line selector 820 is connected to the word lines WL1~WLm. According to a word line select signal WL.sub.sel, the word line selector 820 provides the on voltage V.sub.on to one of the word lines WL1~WLm and provides the off voltage V.sub.off to the other word lines. For example, according to the word line select signal WL.sub.sel, the word line selector 820 provides the on voltage V.sub.on to the word line WL1 and provides the off voltage V.sub.off to the WL2~WLm. Under this circumstance, the word line WL1 is the selected word line and the first row of the resistive random-access memory cell array connected to the word line WL1 is the selected row.

[0092] The bit line selector 830 is connected to the bit lines BL1~BLn. According to a bit line select signal BL.sub.sel, a pulse width control signal W.sub.ctrl and the operation voltage V.sub.OP, the bit line selector 830 is capable of provides the forming pulse, the set voltage or the reset voltage to the selected bit line. In an embodiment, the bit line selector 830 comprises a switching circuit 832 and plural drivers 851~85n. The plural drivers 851~85n receive the pulse width control signal W.sub.ctrl and the operation voltage V.sub.OP. In addition, the switching circuit 832 are connected between the plural drivers 851~85n and the bit lines BL1~BLn. According to the bit line select signal BL.sub.sel, the switching circuit 832 determines one of the plural drivers 851~85n as the selected driver and determines the corresponding bit line as the selected bit line. Furthermore, the selected driver is connected to the selected bit line by the switching circuit 832. According to the pulse width control signal W.sub.ctrl and the forming voltage V.sub.form, the selected driver of the bit line selector 830 provides the forming pulse to the selected bit line during the forming action. Similarly, the bit line selector 830 provides the set voltage to the selected bit line during the set action. The bit line selector 830 provides the reset voltage to the selected bit line during the reset action.

[0093] The source line selector 840 is connected to the source lines SL1~SLn. According to a source line select signal SL.sub.sel, the source line selector 840 determines one of the source line SL1~SLn as the selected source line and the selected source line is connected to the ground voltage GND during the forming action, the set action and the reset action. That is to say, the selected memory cell of the resistive random-access memory cell array is determined in response to the selected word line, the selected bit line and the selected source line.

[0094] Furthermore, during the read action or the verification, the source line selector 840 is capable of providing the read voltage to the selected source line. Also, the switching circuit 832 of the bit line selector 830 is capable of conducting the current on the selected bit line to the sense amplifier 860, and the sense amplifier 860 is capable of generating a storage state signal S.sub.s according to a reference current I.sub.ref and a current on the selected source line. Thus, the storage state of the selected memory cell is determined according to the storage state signal S.sub.s.

[0095] FIG. 8B is a flowchart of a forming control method for a resistive random-access memory cell array according a third embodiment of the present invention. After the forming control method is started, an initial value of a forming voltage V.sub.form is provided (Step S802) and an initial value of a pulse width w is provided (Step S804). Then, a forming pulse is generated according to the forming voltage V.sub.form and the pulse width w, and plural resistive random-access memory cells in a selected row that have not passed the verification action are subjected to a forming action according to the forming pulse (Step S806).

[0096] Then, a step S808 is performed to judge whether all of the plural resistive random-access memory cells in the selected row pass a verification action. According to the embodiment of the invention, the forming actions are firstly performed on the resistive random-access memory cells in the selected row. Then, the resistive random-access memory cells in the same selected row are followed by the verification actions after the forming actions.

[0097] That is, the step S808 is used to judge whether the resistive random-access memory cells subjected to the forming action in the step S806 pass the verification action. If all of the resistive random-access memory cells pass the verification action, it means that the forming action on all of the resistive random-access memory cells in the selected row has been successfully done. Then, a next selected row is determined (Step S814), and the step S804 is repeatedly done.

[0098] If some of the resistive random-access memory cells fail to pass the verification action, it means that the forming action on some of the resistive random-access memory cells in the selected row has not been successfully done. Then, a step S810 is performed to judge whether a change number of the pulse width w reaches a first preset value. If the judging condition of the step S810 is not satisfied, the pulse width w is increased (Step S812) and the step S806 is repeatedly done. For example, if the first preset value corresponding to the change number of the pulse width w is 2, there are three pulse widths. For example, the initial value of the pulse width is 100 ns. After a first change, the pulse width w is 500 ns. After a second change, the pulse width w is 1 .Math.s. In other words, if the forming voltage V.sub.form is not change, the steps S806~S810 are performed for at most three times.

[0099] If the judging condition of the step S810 is satisfied, a step S816 is performed to judge whether the change number of the forming voltage V.sub.form reaches a second preset value. For example, the second preset value is 1. If the judging condition of the step S816 is not satisfied, the forming voltage V.sub.form is increased (Step S818) and the step S804 is repeatedly done. For example, the initial forming voltage V.sub.form is increased by one increment voltage ΔV. That is, V.sub.form = V.sub.form + ΔV.

[0100] If the change number of the forming voltage V.sub.form reaches the second preset value and some of the resistive random-access memory cells in the selected row are still not verified, the selected row is no longer subjected to the forming action and the next selected row is determined (Step S814). Optionally, before the step S814, an additional step is performed to judge whether the number of the resistive random-access memory cells in the selected row that fail to pass the verification action is smaller than a threshold value. If the judging condition is satisfied, it means that the forming action on the selected row has been successfully done. Whereas, if the judging condition is not satisfied, it is confirmed that the selected row is a failed row.

[0101] For example, the selected row contains 2048 resistive random-access memory cells, and the threshold value is 3. If the number of the resistive random-access memory cells in the selected row that fail to pass the verification action is smaller than 3, it is determined that the forming action on the selected row has been successfully done. Whereas, if the number of the resistive random-access memory cells in the selected row that fail to pass the verification action is larger than or equal to 3, the selected row is determined as a failed row and discarded. The discarded row will not be used to store data.

[0102] Moreover, the step of determining the next selected row (i.e., the step S814) is continuously performed until the forming action on the resistive random-access memory cells in the last selected row of the resistive random-access memory cell array is completed. Meanwhile, the forming control method is ended. In some embodiments, if not all of the plural resistive random-access memory cells in the selected row pass the verification action, the step 806 is performed after the steps 812 and 818, and the forming action in the step 806 can be performed on the resistive random-access memory cells in the selected row that have not pass the verification action, and the random-access memory cells in the selected row that have pass the verification action can be inhibited, that is, the forming action is not performed on the inhibited random-access memory cells in the selected row which have pass the verification action.

[0103] From the above descriptions, the present invention provides a forming control method for a resistive random-access memory cell array. While the forming action of the resistive random-access memory cell array is performed, the verification action is performed to judge whether the forming action on the resistive random-access memory cells has been successfully done. By properly changing the forming voltage or the pulse width, the forming actions on all of the resistive random-access memory cells of the resistive random-access memory cell array can be successfully done.

[0104] While the invention has been described in terms of what is presently considered to be the most practical and preferred embodiments, it is to be understood that the invention needs not be limited to the disclosed embodiment. On the contrary, it is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims which are to be accorded with the broadest interpretation so as to encompass all such modifications and similar structures.