CONSTANT-GM CURRENT SOURCE

Abstract

A constant-g.sub.m current source, arranged to generate a supply current for a Pierce oscillator. First and second transistors have source terminals connected to first and second supply rails, respectively, and drain terminals connected together and to the gate terminal of the first transistor. Third and fourth transistors have source terminals connected to the first and second supply rails, respectively, and drain terminals are connected together and to the gate terminal of the fourth transistor. An output portion varies the supply current in response to a voltage at the drain terminals of the third and fourth transistors. The gate terminals of the first and third transistors are connected together, and the gate terminals of the second and fourth transistors are connected together. An auto-calibration transistor has its source terminal connected to the first supply rail and its drain terminal connected to the source terminal of the first transistor.

Claims

1. A constant-g.sub.m current source arranged to generate a supply current for a Pierce oscillator, the constant-g.sub.m current source comprising: a first transistor and a second transistor, arranged such that the source terminal of the first transistor is connected to a first supply rail, the source terminal of the second transistor is connected to a second supply rail, and the drain terminals of the first and second transistors are connected to each other and to the gate terminal of the first transistor; a third transistor and a fourth transistor, arranged such that the source terminal of the third transistor is connected to the first supply rail, the source terminal of the fourth transistor is connected to the second supply rail, and the drain terminals of the third and fourth transistors are connected to each other and to the gate terminal of the fourth transistor; an output portion arranged to vary the supply current in response to a voltage at the drain terminals of the third and fourth transistors wherein the gate terminals of the first and third transistors are connected to each other and are each supplied with a gate voltage, and wherein the gate terminals of the second and fourth transistors are connected to each other; the constant-g.sub.m current source further comprising: a reference resistive element connected between the source terminal of the third transistor and the first supply rail, wherein the resistance of said reference resistive element is set to a predetermined value; and an auto-calibration transistor having its source terminal connected to the first supply rail and its drain terminal connected to the source terminal of the first transistor, wherein the gate terminal of said auto-calibration transistor is supplied with the gate voltage.

2. The constant-g.sub.m current source as claimed in claim 1, wherein the auto-calibration transistor comprises a PMOS transistor, the first and third transistors comprise PMOS transistors, and the second and fourth transistors comprise NMOS transistors.

3. The constant-g.sub.m current source as claimed in claim 2, wherein the first supply rail comprises a positive voltage supply rail and the second supply rail comprises ground or a negative voltage supply rail.

4. The constant-g.sub.m current source as claimed in claim 1, wherein the auto-calibration transistor comprises an NMOS transistor, the first and third transistors comprise NMOS transistors, and the second and fourth transistors comprise PMOS transistors.

5. The constant-g.sub.m current source as claimed in claim 3, wherein the second supply rail comprises a positive voltage supply rail and the first supply rail comprises ground or a negative voltage supply rail.

6. The constant-g.sub.m current source as claimed in claim 1, wherein the output portion comprises an output transistor having its gate terminal connected to the drain terminals of the third and fourth transistors, wherein a voltage at the gate terminal of the output transistor varies a drain-source current through said output transistor, wherein the supply current is or is derived from said drain-source current.

7. The constant-g.sub.m current source as claimed in claim 5, wherein the source terminal of the output transistor is connected to the second supply rail.

8. The constant-g.sub.m current source as claimed in claim 5, wherein the output transistor comprises a PMOS transistor, optionally wherein the drain-source current of the output transistor is supplied directly to the inverter of the Pierce oscillator.

9. The constant-g.sub.m current source as claimed in claim 5, comprising a current mirror comprising first and second current mirror transistors, arranged such that: the source terminals of the first and second current mirror transistors are connected to the first supply rail; the gate terminals of the first and second current mirror transistors are connected to each other, to the drain terminal of the first current mirror transistor, and to the drain terminal of the output transistor; and the drain terminal of the second current mirror transistor is connected to the inverter or is arranged for connection to the inverter.

10. The constant-g.sub.m current source as claimed in claim 1, wherein the reference resistive element comprises a variable resistor.

11. The constant-g.sub.m current source as claimed in claim 9, wherein the reference resistive element may comprise a plurality of resistors and a switching arrangement that selectively enables a selection of said plurality of resistors thereby setting the resistance of said reference resistive element.

12. The constant-g.sub.m current source as claimed in claim 1, wherein a W/L ratio of the third transistor is greater than a W/L ratio of the first transistor.

13. The constant-g.sub.m current source as claimed in claim 11, wherein the W/L ratio of the third transistor is four times greater than the W/L ratio of the first transistor.

14. The constant-g.sub.m current source as claimed in claim 1, wherein a respective W/L ratio of the second transistor is substantially equal to a respective W/L ratio of the fourth transistor.

15. An electronic device comprising a Pierce oscillator and the constant-g.sub.m current source as claimed in any preceding claim, wherein the Pierce oscillator comprises: an inverter having an input terminal and an output terminal, said inverter being arranged to receive a supply current from the constant-g.sub.m current source; a piezoelectric element connected between the input and output terminals of the inverter; a resistor connected between the input and output terminals of the inverter; a first capacitor connected between the input terminal of the inverter and ground; and a second capacitor connected between the output terminal of the inverter and ground.

Description

BRIEF DESCRIPTION OF DRAWINGS

[0055] Certain embodiments of the invention will now be described, by way of example only, with reference to the accompanying drawings in which:

[0056] FIG. 1 is a circuit diagram of a prior art NMOS-based constant-g.sub.m current source for use with a Pierce oscillator;

[0057] FIG. 2 is a circuit diagram of a prior art PMOS-based constant-g.sub.m current source for use with a Pierce oscillator;

[0058] FIG. 3 is a circuit diagram of a constant-g.sub.m current source in accordance with an embodiment of the present invention;

[0059] FIG. 4 is a circuit diagram of a trimmable resistor for use in the arrangement of FIG. 3;

[0060] FIG. 5 is a table of simulation results for the prior art arrangement of FIG. 2;

[0061] FIG. 6 is a table of simulation results for the arrangement of FIG. 3; and

[0062] FIG. 7 is a table of simulation results for the arrangement of FIG. 3 without the auto-calibration resistor.

DETAILED DESCRIPTION

[0063] FIG. 1 is a circuit diagram of a prior art NMOS-based constant-g.sub.m current source 2 for use with a Pierce oscillator, and in particular to supply the inverter 4 of the Pierce oscillator. The details of the Pierce oscillator are not described in detail as the structure and function of a Pierce oscillator are well known in the art per se.

[0064] The constant-g.sub.m current source 2 provides a dynamically-adjusted supply current I.sub.PIERCE to the inverter 4 of the Pierce oscillator, i.e. to the ‘Pierce inverter’. This supply current I.sub.PIERCE is adjusted during operation to keep the transconductance g.sub.m of the current source substantially constant across corners and temperatures. However, this only works within certain limits.

[0065] The dynamically-adjusted supply current I.sub.PIERCE to the Pierce inverter 4 is achieved with the ‘NMOS-based’ topology shown in FIG. 1. Note that the terms ‘NMOS-based’ and ‘PMOS-based’ as used herein do not mean that the associated current source only uses NMOS or PMOS devices respectively, but instead refers to which device type is used for which purpose.

[0066] The two PMOS transistors P1, P2 have substantially equal W/L ratios, i.e. there is a 1:1 relationship between the W/L ratios of P1 and P2. However, the two NMOS transistors N1, N2 are scaled such that the W/L ratio of N2 is four times greater than the W/L ratio of N1, i.e. there is a 1:4 relationship between the W/L ratios of N1 and N2. It will be appreciated, however, that other factors between the W/L ratios of N1 and N2, and thus in general the W/L of N2 is a factor ‘m’ greater than the W/L of N1.

[0067] The constant-g.sub.m current source 2 is constructed from a pair of PMOS transistors P1, P2 and a pair of NMOS transistors N1, N2. The first PMOS transistor P1 and the first NMOS transistor N1 form a ‘first branch’ and the second PMOS transistor P2 and the second NMOS transistor N2 form a ‘second branch’.

[0068] The first branch is arranged such that the source terminal of N1 is connected to ground, and the source terminal of P1 is connected to the positive supply rail AVDD. The drain terminals of P1 and N1 are connected to each other and to the gate terminal of N1.

[0069] The gate terminals of P1 and P2 are connected to each other. Similarly, the gate terminals of N1 and N2 are also connected to each other.

[0070] The second branch is arranged such that the source terminal of N2 is connected to ground via a fixed resistor R1, and the source terminal of P2 is connected to the positive supply rail AVDD. The drain terminals of P2 and N2 are connected to each other and to the gate terminal of P2.

[0071] A PMOS output transistor P3 is arranged such that its gate terminal is connected to the drain terminals of P2 and N2. Thus the voltage at the gate terminal of the output transistor P3 varies the drain-source current through the output transistor P3, which is provided as the supply current I.sub.PIERCE to the Pierce inverter 4, i.e. the drain terminal of P3 is connected to the Pierce inverter 4. The source terminal of P3 is connected to the positive supply rail AVDD.

[0072] Generally, the current through N2 is equal to the magnitude of the difference between the gate-source voltages of the N1 and N2 divided by the resistance of R1 in accordance with Equation 1:

[00001]$\begin{array}{cc}\mathrm{The}\mathrm{current}\mathrm{through}\mathrm{the}\mathrm{first}\mathrm{and}\mathrm{third}\mathrm{transistors}& \mathrm{Equation}1\end{array}$$I_2=\frac{.Math.V_{gs1}-V_{gs2}.Math.}{R_1}=\frac{\Delta V_{gs}}{R_1}=\frac{\Delta V_{\mathrm{od}}}{R_1}=I_1=I$

where: I is the current, I.sub.1 is the current through N1, I.sub.2 is the current through N2, V.sub.gs1 is the gate-source voltage of N1, V.sub.gs2 is the gate-source voltage of N2, ΔV.sub.gs is the difference in these gate-source voltages, V.sub.od is the difference between the gate-source voltage V.sub.gs and the threshold voltage V.sub.th for a given transistor (as outlined further below below) and thus ΔV.sub.od is the difference between this value for the two transistors N1, N2.

[0073] The transconductance g.sub.m is given as per Equation 2 below:

[00002]$\begin{array}{cc}\mathrm{The}\mathrm{transconductance}\mathrm{of}\mathrm{the}\mathrm{current}\mathrm{source}2& \mathrm{Equation}2\end{array}$$g_{m1}=\frac{2\times I}{V_{\mathrm{od}1}}=\frac{2\left(\Delta V_{\mathrm{od}}\right)}{\left(R1\times V_{\mathrm{od}1}\right)}=\left(2\times R1\right)\times \left(1-\frac{V_{\mathrm{od}2}}{V_{\mathrm{od}1}}\right)=\frac{2}{R1}\left(1-\frac{1}{\sqrt{m}}\right)$

where: g.sub.m1 is the transconductance of N1, V.sub.od1 is the difference between the respective gate-source voltage V.sub.gs and the threshold voltage V.sub.th of N1, V.sub.od2 is the difference between the respective gate-source voltage V.sub.gs and the threshold voltage V.sub.th of N2, and m is the factor by which the aspect ratio W/L of N2 is greater than the aspect ratio W/L of N1.

[0074] By using Equation 3 below:

[00003]$\begin{array}{cc}\mathrm{Relationship}\mathrm{between}\mathrm{the}\mathrm{output}\mathrm{voltages}\mathrm{and}\mathrm{the}\mathrm{factor}m& \mathrm{Equation}3\end{array}$$\frac{V_{\mathrm{od}2}}{V_{\mathrm{od}1}}=\sqrt{\frac{W1}{W2}}=\frac{1}{\surd \left(m\right)}$

and setting m to 4, then the transconductance of N1

[00004]$g_{m1}=\frac{1}{R1},$

and thus the transconductance g.sub.m1 depends only on the value of R1, thereby providing the constant-g.sub.m function of the current source 2.

[0075] By simulating the negative resistance R.sub.NEG generated by the Pierce inverter 4 for a given supply current I.sub.PIERCE, the ratio between the maximum and minimum negative resistances seen—i.e. Max(R.sub.NEG)/Min(R.sub.NEG)—is 1.64. Reducing this ratio would be preferable because this would indicate less fluctuation in the negative resistance R.sub.NEG generated by the Pierce inverter 4 across these corners and temperatures.

[0076] As will be appreciated by those skilled in the art, the Pierce inverter 4 would typically have a crystal (e.g. a quartz crystal) connected across its terminals XC1, XC2. However, there are many possible options when choosing commercial crystals. For examples, different Q-factors, different package types, and different model parameters even with the same package size, all influence the need to have sufficient negative resistance R.sub.NEG generated by the Pierce inverter 4 in order to drive the crystal and to sustain the oscillation. With the conventional arrangement of FIG. 1 (and that of FIG. 2 as outlined below), the supply current I.sub.PIERCE needs to be adjusted manually for different crystals, which is cumbersome.

[0077] FIG. 2 is a circuit diagram of a prior art PMOS-based constant-g.sub.m current source 2′, which supplies the inverter 4 of a Pierce oscillator. As before, the Pierce inverter 4 would typically have a crystal (e.g. a quartz crystal) connected across its terminals XC1, XC2.

[0078] The PMOS-based constant-g.sub.m current source 2′ provides the dynamically-adjusted supply current I.sub.PIERCE to the inverter 4 of the Pierce oscillator, and this supply current I.sub.PIERCE is adjusted during operation to keep the transconductance g.sub.m of the current source substantially constant across corners and temperatures. However, as with the arrangement of FIG. 1, this only works within certain limits.

[0079] In this arrangement, the two NMOS transistors N1, N2 have substantially equal W/L ratios, i.e. there is a 1:1 relationship between the W/L ratios of N1 and N2. However, the two PMOS transistors P1, P2 are scaled such that the W/L ratio of P2 is four times greater than the W/L ratio of P1, i.e. there is a 1:4 relationship between the W/L ratios of P1 and P2. As before, the 1:4 relationship is only given as an example, and in practice there may be a 1:m relationship between the W/L ratios of P1 and P2.

[0080] The constant-g.sub.m current source 2′ is constructed from a pair of PMOS transistors P1, P2 and a pair of NMOS transistors N1, N2. The first PMOS transistor P1 and the first NMOS transistor N1 form a ‘first branch’ and the second PMOS transistor P2 and the second NMOS transistor N2 form a ‘second branch’.

[0081] The first branch is arranged such that the source terminal of N1 is connected to ground, and the source terminal of P1 is connected to the positive supply rail AVDD. The drain terminals of P1 and N1 are connected to each other and to the gate terminal of P1.

[0082] The second branch is arranged such that the source terminal of N2 is connected to ground, and the source terminal of P2 is connected to the positive supply rail AVDD via a fixed resistor R1. The drain terminals of P2 and N2 are connected to each other and to the gate terminal of N2. The gate terminals of P1 and P2 are connected to each other. Similarly, the gate terminals of N1 and N2 are also connected to each other.

[0083] An NMOS output transistor N3 is arranged such that its gate terminal is connected to the drain terminals of P2 and N2. Thus, the voltage at the gate terminal of the output transistor P3 varies the drain-source current through the output transistor N3.

[0084] The drain terminal of the output transistor N3 is connected to a current mirror formed from a pair of PMOS transistors P4, P5. These transistors P4, P5 are arranged in a current mirror arrangement such that the first mirror transistor P4 is arranged in a ‘diode-connected’ arrangement, such that its source terminal is connected to AVDD, and its gate and drain terminals are both connected to the drain terminal of the NMOS output transistor N3. The second mirror transistor P5 is arranged such that its source terminal is connected to AVDD, its gate terminal is connected to the gate and drain terminals of P4 (and thus to the drain terminal of N3), and its drain terminal is connected to the Pierce inverter 4.

[0085] The drain-source current flowing through the output transistor N3, and thus the drain-source current through the first mirror transistor P4 is ‘mirrored’ through the second mirror transistor P5. The mirrored current through P5 is provided as the supply current I.sub.PIERCE to the Pierce inverter 4, i.e. the drain terminal of P3 is connected to the Pierce inverter 4.

[0086] Like the NMOS-based arrangement of FIG. 1, in the PMOS-based arrangement of FIG. 2, the supply current I.sub.PIERCE needs to be adjusted manually for different crystals, which is cumbersome. Additionally, the PMOS-based arrangement of FIG. 2 suffers from wide variation in the ratio between the maximum and minimum negative resistances seen—i.e. Max(R.sub.NEG)/Min(R.sub.NEG).

[0087] In order to find this value, operation of the arrangement of FIG. 2 across 5 corners was simulated. These five corners are: [0088] 1) Typical operation=Room temperature; AVDD at its nominal value [0089] 2) Fast 0=High temperature; Nominal AVDD [0090] 3) Fast_1=Low temperature; Nominal AVDD [0091] 4) Slow_0=High temperature; Nominal AVDD [0092] 5) Slow_1=Low temperature; Nominal AVDD

[0093] It will be appreciated that ‘Nominal AVDD’ means that the value of AVDD is simulated as its nominal ‘design’ value.

[0094] The results of this simulation can be seen in the table of FIG. 5, which relates to a simulation of a typical ‘FA128’ crystal. The metric Max(R.sub.NEG)/Min(R.sub.NEG) has been found by simulation to be 1.64 (to two decimal places).

[0095] FIG. 3 is a circuit diagram of a constant-g.sub.m current source in accordance with an embodiment of the present invention. The overall topology of the arrangement of FIG. 3 resembles that of the NMOS-based topology of FIG. 2, and elements having like reference numerals to the arrangement of FIG. 2 are alike in structure and function.

[0096] However, unlike the arrangement of FIG. 2, the constant-g.sub.m current source 102 of FIG. 3 replaces the fixed resistor between the source terminal of P2 and AVDD with a ‘trim’ resistor R1′. This resistor R1′ provides a ‘reference’ resistive element. In order to provide the trimmable behaviour, the ‘resistor R1’ is typically not a single fixed resistor, but instead a matrix (i.e. an array) of resistors and associated switches—such as the matrix shown in FIG. 4—that allow for a given selection of the resistors in the matrix to be ‘switched in’, thereby setting the resistance of R1′. Other mechanisms suitable for varying the resistance of R1′ could be used instead, however.

[0097] As can be seen in FIG. 4, the resistance R1′ in this embodiment is controlled by varying a four-bit control word TRIM<0-3>. Depending on the value of each bit TRIM<0-3>, the associated resistor is either ‘switched in’ or bypassed by the associated switch. In this particular embodiment, the resistors within R1′ have increasing resistance, from 1 ‘unit’ resistance, to 2 units, to 4 units, and then 8 units. With all resistors switched in, the total resistance of R1′ can be set up to 31 units of resistance. Of course, the resistances do not need to step in this way, or at all (these could all be the same value, for example), and any suitable selection may be made for a particular implementation.

[0098] In this case the switches are PMOS transistors but other suitable switches such as NMOS transistors could be used with suitable modification to the circuit and which value of the bits TRIM<0-3> enables and disables the associated resistor.

[0099] Referring back to FIG. 3, an additional ‘auto-calibration’ resistor R2 is provided between the source terminal of P1 and AVDD. In practice, R2 is constructed from a PMOS transistor P6, arranged such that its source terminal is connected to AVDD, and its drain terminal is connected to the source terminal of P1.

[0100] While the voltage vgp at the gate terminals of P1 and P2 depends on the process, supply voltage, and temperature (PVT) variations of the device, the auto-calibration transistor P6 is also subject to these same PVT variations.

[0101] The gate terminal of P6 (i.e. the auto-calibration resistor R2) is arranged to receive the same voltage vgp that is applied to the gate terminals of P1 and P2. This may be achieved by physically connecting the gates of P1 and P2 to one another, or by supplying the same voltage to both (without a direct connection between them). As the gate terminal of P6 is supplied with the same voltage vgp as the gates of P1 and P2, this auto-calibration transistor P6 operates in its triode region. This means that the transistor P6 has resistor-like behaviour, i.e. there is a relatively linear, Ohmic like relationship between its drain-source voltage and drain-source current.

[0102] Like the arrangement of FIG. 2, an NMOS output transistor N3 is arranged such that its gate terminal is connected to the drain terminals of P2 and N2. Thus, the voltage at the gate terminal of the output transistor P3 varies the drain-source current through the output transistor N3. A current mirror formed from a pair of PMOS transistors P4, P5 mirrors the current through this output transistor N3, and supplies the mirrored current IPIERCE to the Pierce inverter 4.

[0103] The resistance of R1′, i.e. the trimmable resistor, determines the voltage vgp at the gate terminals of P1 and P2, and at the gate terminal of the auto-calibration transistor P6. For a given selected crystal (i.e. to be connected between the XC1 and XC2 terminals of the Pierce inverter 4), the resistance of R1′ can be trimmed to a value appropriate for ‘normal’ operation of the circuit, i.e. with AVDD at its nominal value and room temperature conditions.

[0104] Compared to the arrangements of FIGS. 1 and 2, the arrangement of FIG. 3 in accordance with an embodiment of the present invention has a far more consistent the ratio between the maximum and minimum negative resistances seen. As before, the simulated corners are: [0105] 1) Typical operation=Room temperature; AVDD at its nominal value [0106] 2) Fast_0=High temperature; Nominal AVDD [0107] 3) Fast_1=Low temperature; Nominal AVDD [0108] 4) Slow_0=High temperature; Nominal AVDD [0109] 5) Slow_1=Low temperature; Nominal AVDD

[0110] The results of this simulation can be seen in the table of FIG. 6. A direct comparison of the typical FA128 crystal (FA128_TYPICAL) to the simulation results associated with the prior art arrangement of FIG. 2 shown in the table of FIG. 5 shows a significant improvement in the ratio of the maximum to minimum negative resistance seen. Specifically, through this simulation, the ratio Max(R.sub.NEG)/Min(R.sub.NEG) for the arrangement of FIG. 3 has been found to be 1.12.

[0111] The simulation results in the table of FIG. 6 also show the values found for several other commercially available crystals: NX1210AB; NX1612AA; FA20H; and TSX3225. The ‘_TYPICAL’ and ‘_WORST’ suffixes indicate typical and worst-case simulation results. As can be seen from the results, the ratio Max(R.sub.NEG)/Min(R.sub.NEG) for the arrangement of FIG. 3 has been found to be consistently 1.12 (to two decimal places) for all simulated crystals and scenarios.

[0112] Thus, the metric Max(R.sub.NEG)/Min(R.sub.NEG) is significantly lower for the topology of FIG. 3 compared to the prior art arrangements of FIGS. 1 and 2. In other words, the arrangement of FIG. 3 is more consistent across the simulated corners when compared to the described prior art arrangements.

[0113] To illustrate the impact of the auto-calibration transistor P6 as an ‘automatic’ resistance, FIG. 7 provides a further table of simulation results in which R1 is ‘trimmed’ as above, but no R2 (i.e. no P6) is provided. The ratio Max(R.sub.NEG)/Min(R.sub.NEG) is consistently between 1.29 and 1.30 (to two decimal places) for the same crystals and scenarios as in the table of FIG. 6. While the ratio Max(R.sub.NEG)/Min(R.sub.NEG) is improved compared to the prior art arrangement, the results are not as consistent as they are for the arrangement of FIG. 3 with an auto-configuration resistor R2, as evidenced in the table of FIG. 6.

[0114] It can be seen, therefore, that embodiments of the present invention provide an improved constant-g.sub.m current source for use with a Pierce oscillator, suitable for a variety of different crystals, that is more resilient to PVT variations. The constant-g.sub.m current source of the present invention advantageously results in more consistent negative resistance exhibited by a Pierce oscillator supplied by the constant-g.sub.m current source across different corners.

[0115] Those skilled in the art will appreciate that the specific embodiments described herein are merely exemplary and that many variants within the scope of the invention are envisaged.