XRF ANALYZER WITH IMPROVED RESOLUTION BY USING MICRO-RESET

Abstract

Disclosed is an electronic system for resetting the voltage of a charge-sensitive pre-amplifier having input from an X-ray detector and output to an ADC. The pre-amplifier gain is increased so that the RMS ADC noise is less than 1% of a representative digitized X-ray signal. The reset logic is configured to avoid loss of X-ray counts and to prevent the pre-amplifier output being outside the allowable input range of the ADC. Reset is initiated when the pre-amplifier output rises above an upper level, which is below the maximum allowable ADC input. Reset is also initiated when a pile-up event is detected, provided that such reset will not cause the pre-amplifier output to fall below the minimum allowable ADC input. At each reset a known amount of charge is removed from the pre-amplifier, and the reset time is continuously adjusted to ensure that the charge amount does not drift.

Claims

1. An X-ray detector reset control circuit used in an X-ray analytical instrument, the instrument is configured to induce and analyze a series of events of induced X-rays, the -ray detector reset control circuit comprising: an X-ray detector configured to detect the events of induced X-rays with energy E ke V and send detector analog voltage response signals indicative of the events of X-rays; a charge-sensitive preamplifier connected to the detector and configured to amplify the response signals and produce amplified signals; an analog-to-digital converter (ADC) for providing a digitization of the amplified signals, the ADC having an ADC output level and producing a series of digitized signal values corresponding to the events of X-rays, the series of digitized signal values causing a stair-like increase of the ADC output level; and a micro-reset unit configured to receive signals from the ADC and trigger a reset for a reset time t.sub.R to decrease the ADC output level with a charge reset drop and vary the reset time t.sub.R according to the ADC output level.

2. The X-ray detector reset control circuit of claim 1, wherein the micro-reset unit is configured to trigger the reset according to two or more reset logic criteria including a) an upper level reset criterion, for which the ADC output level has surpassed an upper level threshold, and b) a pile-up reset criterion, for which two of the events of X-rays are within a predetermined time with or without surpassing the upper level threshold.

3. The X-ray detector reset control circuit of claim 2, including: a pulse indicator producing a fast pulse timing signal indicative of each of the events of X-rays; and wherein the micro-reset unit includes a fast logic unit configured to receive the ADC output level and the fast pulse timing signal as input and produce an upper level reset signal and a pile-up reset enable signal as output to detect the pile-up reset criterion.

4. The X-ray detector reset control circuit of claim 3, wherein: a) the upper level reset criterion includes the ADC output level surpassing the upper level threshold and a predetermined peaking time t.sub.p elapsing since a most recent of the fast pulse timing signals; and b) the pile-up reset criterion includes the corresponding fast pulse timing signals of two of the events of X-rays being within the peaking time t.sub.p.

5. The X-ray detector reset control circuit of claim 3, wherein the micro-reset unit is configured to: a) receive the digitized signal values with the corresponding fast pulse timing signals, b) wait until the ADC output level has surpassed an upper level threshold, c) wait until a peaking time t.sub.p has elapsed since a most recent of the fast pulse timing signals, wherein the peaking time t.sub.p is indicative of a time span required to establish the ADC output level after the corresponding fast pulse timing signal, and d) triggering a reset.

6. The X-ray detector reset control circuit of claim 3, wherein the micro-reset unit is configured to: a) receive a first of the signal values with a first of the corresponding pulse timing signals, b) determine whether a second of the signal values with a second of the corresponding pulse timing signals is received before the peaking time t.sub.p has elapsed since the first of the pulse timing signals, c) determine whether the ADC output level is above a lower level threshold, and d) trigger a reset when b) and c) are true.

7. The X-ray detector reset control circuit of claim 1, wherein the charge reset drop is a variable value depending on the value of the ADC output level.

8. The X-ray detector reset control circuit of claim 1, wherein the charge reset drop is a predetermined reset drop determined by the reset time t.sub.R which is an input to the micro-reset unit.

9. The X-ray detector reset control circuit of claim 8, further including a reset time adjustment unit which receives digitized signal values from the ADC indicative of an actual charge reset drop for each reset, wherein the reset time adjustment unit is configured to provide an adjusted reset time to replace the reset time t.sub.R in order to increase or decrease the actual charge reset drop during the reset to be substantially equal to the predetermined charge reset drop.

10. The X-ray detector reset control circuit of claim 1, wherein the decision module further includes a lower level threshold, and is configured to ignore the reset decision when the ADC output level is lower than the lower level threshold.

11. An automated method of measurement of X-rays using an X-ray analytical instrument, the method comprising: generating analog voltage response signals associated with detected X-ray events; digitizing the generated analog voltage response signals to a series of digitized signal values corresponding to the detected X-ray events; resetting the series of digitized signal values for a reset time using a first signal reset drop when the series of digitized signal values increases to a predetermined upper signal level; varying the reset time according to the digitized signal values; and resetting the series of digitized signal values using a second signal reset drop when detecting an X-ray pile-up event that includes two of the detected X-ray events occurring within a predetermined X-ray pile-up event detection time, wherein the second signal reset drop is less than the first signal reset drop.

12. The method of claim 11, wherein the generating the analog voltage response signals includes generating the analog voltage response signals using a pre-amplifier; and wherein the resetting the series of digitized values includes resetting the pre-amplifier using a first reset time duration when the series of digitized signal values increases to the predetermined upper signal level, and resetting the pre-amplifier using a second reset time duration shorter than the first reset time duration when detecting the X-ray pile-up event.

13. The method of claim 12, including: converting the analog voltage response signals to the series of digitized signal values using an analog-to-digital converter (ADC) circuit; determining one or both of a first change in the digitized signal values resulting from the first reset time and a second change in the digitized signal values resulting from the second reset time; and changing one or both of the first reset time and the second reset time based on the determined one or both of the first change and the second change in the digitized signal values.

14. The method of claim 12, wherein resetting the pre-amplifier using the second reset time includes resetting the pre-amplifier using a second reset time based on a digitized signal value when detecting the X-ray pile-up event,

15. The method of claim 11, wherein the digitizing the generated analog voltage response signals includes converting the analog voltage response signals using an analog-to-digital converter (ADC) circuit having a least significant bit (LSB) signal value; and wherein the resetting the series of digitized signals includes decreasing the output of the ADC circuit a first number of LSB signal values when the series of digitized signals increases to the predetermined upper signal level, and decreasing the output of the ADC circuit a second number of LSB signal values less than the first number of LSB signal values when detecting the X-ray pile-up event.

16. The method of claim 11, including: generating a pulse timing signal in response to a detected X-ray event; and wherein the detecting the X-ray pile-up event includes detecting two pulse timing signals occurring within the predetermined X-ray pile-up event detection time.

17. The method of claim 11, wherein the digitizing the generated analog voltage response signals includes converting the analog voltage response signals using an analog-to-digital converter (ADC) circuit; and wherein the detecting the X-ray pile-up event includes detecting two X-ray events within a time duration to establish an ADC circuit output value.

18. The method of claim 17, wherein the resetting the series of digitized signal values includes resetting the series of digitized signal values using the first signal reset drop when the series of digitized signals increases to the predetermined upper signal level and the time duration to establish the ADC circuit output value has elapsed since a detected X-ray event.

19. The method of claim 11, wherein the second signal reset drop is a fixed predetermined value.

20. The method of claim 19, further including not resetting the series of digitized signal values using the second signal reset drop when detecting the X-ray pile-up event and a current digitized signal value of the series of digitized signal values is less than a predetermined lower level signal value.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0017] FIG. 1 is a schematic of a detector reset control circuit of an X-ray detection system according to the present disclosure.

[0018] FIG. 2A is a schematic of a prior art X-ray detection system.

[0019] FIG. 2B is a graph of ADC output vs time for a prior art X-ray detection system.

[0020] FIG. 3A is a graph of ADC output vs time for an X-ray detection system according to the present disclosure.

[0021] FIG. 3B is a graph of an alternative embodiment of ADC output vs time for an X-ray detection system according to the present disclosure.

[0022] FIG. 4. is a schematic of the detector reset control circuit of the X-ray detection system according to the present disclosure, showing details of the micro-reset decision module.

[0023] FIG. 5 is a graph of signals for pile-up micro-reset according to the present disclosure.

[0024] FIG. 6 is a flow chart of upper level reset logic according to the present disclosure.

[0025] FIG. 7 is a flow chart of pile-up reset logic according to the present disclosure.

[0026] FIG. 8 is a flow chart of backup reset logic according to the present disclosure.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

[0027] Note that in the description below, the term “voltage” is used to designate analog signals, and the term “value” is used to designate digital quantities. Note also that in the description and the drawings a symbol without angle brackets is used to denote an analog quantity, and a symbol with angle brackets is used to denote a digital quantity. For example, the analog value of a charge is Q, and its digitized equivalent is <Q>. In addition, unprimed numerals, such as 6, denote components related to the present disclosure, whereas primed numerals, such as 6′, denote components of existing practice. Numerals preceded by “S”, such as S-16, denote a signal line.

[0028] Referring to FIG. 1, a schematic is shown of a detector reset control circuit for an X-ray detection system according to the present disclosure. The detector control circuit preferably comprises a detector 4, a charge-sensitive pre-amplifier 6, an ADC 10, a fast pulse indicator 12, a micro-reset decision module 16 and a micro-reset circuit 8. In operation, pulses from detector 4 are amplified by pre-amplifier 6 to produce an output voltage S-6 which is digitized by ADC 10, producing an ADC output S-10, from which an energy spectrum is generated by a spectrum generator 14. Pulse indicator 12 produces a fast pulse timing signal S-12, providing an indication of an arrival time of an X-ray at detector 4. Micro-reset decision module 16 receives ADC output S-10, output voltage S-6 and timing signal S-12, and, based on a number of reset logic decisions described below, produces a reset signal S-16 which causes micro-reset circuit 8 to reset output voltage S-6, also as described below.

[0029] Optionally, and not shown in FIG. 1, the detector reset control circuit may further comprise or connect to a second pre-amplifier which is not a charge sensitive pre-amplifier. Such an arrangement is also within the scope of the present disclosure.

[0030] Reference is now made to FIG. 3A. which shows a graph of ADC output S-10 vs time. A top ADC level 43 is the digital equivalent of the top threshold voltage, which is the highest output voltage S-6 allowable as input into ADC 10. Top ADC level 43 is therefore the highest possible value of ADC output S-10, which is 65,536 LSBs in the embodiment of a 16 bit ADC. A bottom ADC level 40 is the digital equivalent of the bottom threshold voltage, which is the lowest possible value of ADC output S-10, in which all the ADC bits are zero. A rising portion 44 of the graph, comprising multiple X-ray signals, begins above bottom ADC level 40 and rises as X-ray signals are received. For the embodiment in which ADC 10 is a 16 bit ADC, there are 65,536 LSBs between bottom ADC level 40 and top ADC level 43.

[0031] It should be noted that unlike systems in existing practice where the gain of pre-amplifier 6 is set such that the average step height response to an incident X-ray corresponds to about 100 to 200 LSBs, the novel design of the present disclosure enables the gain of pre-amplifier 6 to be set at least ten times higher, and preferably 15 to 30 times higher, so that the average step height response to an incident X-ray corresponds to about 1,500 to 6,000 LSBs. Whereas, in existing systems, typically 300-600 incident X-rays will cause ADC output S-10 to rise sufficiently so that reset is required, in the system of the present disclosure reset occurs on average after only 10-100 incident X-rays.

[0032] Note that, in common with existing systems, the RMS noise of ADC 10 is about 3 LSBs RMS (equivalent to about 20 LSBs peak-to-peak noise). However, in the system of the present disclosure the RMS noise typically represents only 0.05%-0.2% of the signal, and is always less than 1% of the signal, compared to existing systems where the ADC RMS noise is several percent of the signal. In existing practice, the contribution from pre-amplifier noise is usually much smaller than the ADC noise. In the system according to the present disclosure, the pre-amplifier gain may be increased until the pre-amplifier noise is equal to or slightly less than the ADC noise.

[0033] In XRF systems the characteristic X-ray emission of iron, having an energy of about 6.4 keV, is often used as a calibration standard. In the present system, the gain of pre-amplifier 6 may be set so that the step height response of ADC output S-10 due to an incident iron X-ray corresponds to at least 1,500 LSBs, so that the RMS noise of ADC 10 at about 3 LSBs typically corresponds to 0.2% or less of the iron X-ray signal, and is always less than 1% of the iron X-ray signal.

[0034] Increasing the gain of pre-amplifier 6 is an important and novel aspect of the present invention, allowing a significant improvement in energy resolution due to reduction in the relative importance of ADC noise. However, increasing the gain of pre-amplifier 6 means that more frequent resets are required and, therefore, it would be unacceptable to lose X-ray counts at each reset in the same manner as existing systems. Loss of X-rays counts is avoided by a further novel and important aspect of the present invention, which is use of a micro-reset decision module providing a logical framework designed to avoid unnecessary loss of X-ray counts. In this context, “micro-reset” implies that, unlike in existing practice, reset may occur over only a part of the full voltage range of pre-amplifier 6, corresponding to only part of the full bit range of ADC 10.

[0035] Referring again to FIG. 3A, an upper ADC level 42 is defined to be below top ADC level 43 by an amount corresponding approximately to the digitized equivalent of the maximum X-ray energy value. In an embodiment, upper level 42 may be about 6,000 LSBs below top level 43. Micro-reset decision module 16 is configured to output reset signal S-16 when rising portion 44 crosses upper level 42. A signal 45 is shown crossing upper level 42 in FIG. 3A. However, yet another significant novel aspect of the reset circuit is that the micro-reset does not occur until a peaking time t.sub.p has elapsed. Peaking time t.sub.p is the time taken to establish a level of ADC output S-10 after signal 45, so that the energy of the corresponding X-ray may be determined by subtraction of the energy before arrival of signal 45 from the energy after arrival of signal 45. If micro-reset occurs before peaking time t.sub.p has elapsed, the X-ray count corresponding to signal 45 would be lost. If another X-ray signal arrives before peaking time t.sub.p has elapsed, a pile-up event would have occurred, and both X-ray counts would be lost. However, in the absence of a pile-up event, signal 45 is counted and its energy measured prior to the micro-reset, and loss of an X-ray count at reset, as occurs in existing practice, is avoided. Note also that, since upper ADC level 42 is below top ADC level 43 by an amount corresponding approximately to the maximum X-ray energy, there is little chance that signal 45 will reach top ADC level 43. Thus, in normal operation, ADC output S-10 does not reach top ADC level 43, thereby avoiding loss of X-ray counts or erroneous energy measurement due to saturation of ADC output S-10 at its maximum value.

[0036] After waiting for peaking time t.sub.p, micro-reset occurs, as shown by a graph falling portion 46, which lasts for a reset time t.sub.R. Reset time t.sub.R has a duration of 20-100 nanoseconds, which is 10 to 50 times shorter than the reset time in existing systems. The duration of reset time t.sub.R is adjusted so that at each micro-reset, a predetermined constant charge amount Q is removed from pre-amplifier 6. A charge reset drop <Q>, the digital equivalent of charge amount Q, is shown in FIG. 3A. Charge reset drop <Q> corresponds to less than the maximum number of LSBs of ADC 10. In an embodiment, where ADC 10 is a 16-bit ADC, charge reset drop <Q> may correspond to 30,000 to 50,000 LSBs. To maintain the constancy of charge reset drop <Q>, reset time t.sub.R is continuously adjusted by a reset time adjustment unit 9 (see FIG. 4), which monitors ADC output S-10 and measures charge reset drop <Q> at each reset event. If a measured actual charge reset drop is less than the desired constant charge reset drop <Q>, then reset time adjustment unit 9 increases the value of reset time t.sub.R and transmits the increased value to micro-reset circuit 8 for use at the next reset event. If a measured actual charge reset drop is greater than the desired constant charge reset drop <Q>, then reset time adjustment unit 9 reduces the value of reset time t.sub.R and transmits the reduced value to micro-reset circuit 8 for use at the next reset event. In this way constancy of charge reset drop <Q> is maintained despite any drift of electronic components which may cause variation of the gain of pre-amplifier 6 and/or ADC 10.

[0037] Note that, as illustrated in FIG. 3A, ADC output S-10 does not remain constant between the step increases corresponding to arrival of each X-ray. Even in the absence of an X-ray, ADC output S-10 rises slowly due to leakage of charge in detector 4. Consequently, a rising portion may cross upper ADC level 42 also in absence of an X-ray pulse. This is illustrated by a rising portion 44a, in which a signal 45a does not cross upper ADC level 42 during an X-ray pulse, but subsequently crosses upper ADC level 42 due to leakage. In this case, as before, in order to ensure that the energy of signal 45a is correctly measured, micro-reset decision module 16 waits until peaking time t.sub.p has elapsed since arrival of signal 45a, and then triggers a micro-reset represented by falling portion 46a.

[0038] A lower ADC level 41 is defined as being above bottom ADC level 40 by the amount of charge reset drop <Q>. Falling portions 46 and 46a result in ADC output S-10 being below lower ADC level 41, but above bottom ADC level 40. Micro-reset in the present system never allows ADC output S-10 to fall to bottom ADC level 40, and therefore there is no dead time after reset due to pre-amplifier output voltage S-6 being out of range. Moreover, because the reset occurs over a small part of the full output range of pre-amplifier 6, there is much less undershoot than in existing systems, and the recovery time is much shorter. On average, undershoot recovery occurs in a time equivalent to one or two times peaking time t.sub.p, and consequently the total dead time after reset is very small.

[0039] The reset condition in which micro-reset decision module 16 performs a reset when ADC output S-10 exceeds upper ADC level 42 is referred to herein as an “upper level reset”, and the associated logic is further described below in connection with FIG. 6. However, there are other conditions in which micro-reset decision module 16 may perform a reset. As another novel aspect of the present disclosure, reset may also occur if a pile-up event is detected, provided that ADC output S-10 is above lower ADC level 41 at the time the pile-up event occurs. Such a reset is referred to herein as a “pile-up reset”, and the associated logic is further described below in connection with FIGS. 5 and 7.

[0040] FIG. 3A illustrates a pile-up event in which a second signal 48 arrives in a time less than peaking time t.sub.p after arrival of a first signal 47. In this situation, the information from both first signal 47 and second signal 48 is lost because the step height of neither signal can be measured. It is therefore advantageous to utilize the peaking time t.sub.p after arrival of second signal 48 to perform an immediate pile-up reset as soon as second signal 48 is detected. The result of the reset is a falling portion 49 of the graph, and as before the magnitude of the fall is equal to charge reset drop <Q>. Note that pile-up reset may only occur if ADC output S-10 is above lower ADC level 41, because if reset were triggered when ADC output S-10 is below lower ADC level 41 the reset would attempt to drive ADC output S-10 below bottom ADC level 40, corresponding to pre-amplifier signal S-6 below its bottom threshold voltage. This is an undesirable situation which would result in increased dead time and consequent loss of X-ray counts.

[0041] Falling portions 46, 46a and 49 have the same duration, which is reset time t.sub.R, and each results in a reduction of ADC output S-10 by an amount <Q>. However, if an X-ray signal corresponding to an X-ray with energy E arrives during reset time t.sub.R, then the reduction of ADC output S-10 would be equal to

<Qx>=<Q>−<E>  (1)

where <Qx> is the measured reduction of ADC output S-10 when an X-ray arrives during the reset, and <E> is the digital representation of X-ray energy E. Thus, because the reduction of ADC output S-10 due to each micro-reset is known and equal to <Q>, X-rays arriving during the reset time are not lost. Their energy may be determined from the relationship

<E>=<Q>−<Qx>  (2)

and such X-ray energies may be added to the X-ray spectrum.

[0042] As shown in FIG. 3A, charge reset drop <Q> is configured to be constant for all micro-resets, such as those depicted by falling portions 46, 46a and 49. However, in a further and novel embodiment of the invention, as illustrated in FIG. 3B, charge reset drops may be different depending on the level of ADC output S-10 at the time of the micro-reset. Basically, a larger charge reset drop is possible during reset when ADC output S-10 is near the top of its range than when it is near the bottom of its range. Many different algorithms for calculating the dependence of charge reset drop on ADC output S-10 may be devised by those skilled in the art, and all are within the scope of the present disclosure. The requirements of any such algorithm are that the charge reset drop should be a known and increasing function of ADC output S-10 at the time the micro-reset is initiated. The advantage of such an algorithm is that the number of available LSBs between lower ADC level 41 and upper ADC level 42 is increased, as can be seen by comparing FIGS. 3A and 3B.

[0043] FIG. 3B illustrates a particular embodiment of a charge reset drop algorithm in which lower ADC level 41 is above bottom ADC level 40 by the amount of a charge reset drop <Q.sub.1>, and the values of ADC output S-10 between lower ADC level 41 and upper ADC level 42 are divided into 4 zones, namely zone 1, zone 2, zone 3 and zone 4, where zones 1, 2 and 3 each cover one of the lowest three quarters, and zone 4 includes the uppermost quarter and the region between upper ADC level 42 and top ADC level 43. There are four corresponding values of charge reset drop during a micro-reset, namely <Q.sub.1>, <Q.sub.2>, <Q.sub.3> and <Q.sub.4>, and four corresponding reset times t.sub.R1, t.sub.R2, t.sub.R3 and t.sub.R4 (only t.sub.R4 is shown) which are implemented by reset time adjustment unit 9 (see FIG. 4). A particular embodiment of a charge reset drop algorithm is a linear dependency on the zone:

<Q.sub.1>=<Q.sub.1>(1+k(i−1))  (3)

where <Q.sub.1> is the charge reset drop when ADC output S-10 is within zone i, and k is a constant.

[0044] As shown in FIG. 3B, for the case of an upper level reset, where rising portion 44 crosses upper ADC level 42, the maximum charge reset drop <Q.sub.4> is applied in the micro-reset. For the case of a pile-up reset due to pile-up between a first signal 47 and a second signal 48 occurring within zone 2, a smaller charge reset drop <Q.sub.2> is applied. For the case of a pile-up reset due to pile-up between a first signal 47a and a second signal 48a occurring within zone 3, a charge reset drop <Q.sub.3> is applied, resulting in a falling portion 49a of ADC output S-10.

[0045] It should be noted that division into four zones as shown in FIG. 3B is a representative embodiment only. Any number of zones may be used, and all are within the scope of the present disclosure. Similarly, the use of a linear relationship as in equation (3) is a representative embodiment only. Any relationship in which the charge reset drop is an increasing function of ADC output S-10 may be employed and all such relationships are within the scope of the present disclosure.

[0046] Referring now to FIG. 4, the same detector reset control circuit depicted in FIG. 1 is shown, but with addition of reset time adjustment unit 9, and including details of an embodiment of micro-reset decision module 16. It should be appreciated that micro-reset decision module 16 as shown in FIG. 4 is an exemplary embodiment only, and other embodiments are all within the scope of the present disclosure. As shown in FIG. 4, micro-reset decision module 16 comprises a fast logic unit 22, an optional comparator 20, an AND gate 24 and an OR gate 26. Fast logic unit 22 is an electronic device capable of making fast logic decisions as described below. Fast logic unit 22 may be a programmable logic device such as a Field-Programmable Gate Array (FPGA), a custom logic device such as an Application-Specific Integrated Circuit (ASIC), or any other kind of digital processor. In addition, it should be noted that fast logic unit 22 may physically reside on a common FPGA or other logic unit handling other general logic processing tasks required by the XRF system. Alternatively, fast logic unit 22 may reside on a separate processor chip. It should be appreciated that all these variations are within the scope of the present disclosure.

[0047] Fast logic unit 22 receives input from ADC output S-10 and pulse timing signal S-12, and produces more than one, such as two logical output signals as shown, namely an upper level reset signal S-22a and a pile-up reset enable signal S-22b. AND gate 24 receives inputs from pulse timing signal S-12 and pile-up reset enable signal S-22b, and produces a pile-up reset signal S-24 only if both input signals are present. OR gate 26 receives inputs from upper level reset signal S-22a and pile-up reset signal S-24, and produces reset signal S-16 if any one of the two input signals is present. Reset signal S-16 instructs micro-reset circuit 8 to reset output voltage S-6.

[0048] Optionally, in the event that fast logic unit 22 is disabled or otherwise unavailable, such as during initial manufacturer testing of detector 4 and pre-amplifier 6, a comparator 20 is available to perform a reset if required. This is referred to herein as a “backup reset” and the details of its usage are described in connection with FIG. 8. Comparator 20 receives input from output voltage S-6, and produces a backup reset signal S-20 when output voltage S-6 reaches the top threshold voltage, which is equivalent to ADC output S-10 reaching top ADC level 43 (see FIG. 3A). In the case when optional comparator 20 is present, OR gate 26 receives inputs from backup reset signal S-20, upper level reset signal S-22a and pile-up reset signal S-24, and produces reset signal S-16 if any one of the three input signals is present.

[0049] FIG. 4 also shows optional reset time adjustment unit 9, receiving input from ADC output S-10 and producing reset time t.sub.R, whose value is input to micro-reset circuit 8. The function and purpose of reset time adjustment unit 9 has been described above in connection with FIG. 3A.

[0050] FIG. 5 shows graphs of signals which enable micro-reset decision module 16 to rapidly detect a pile-up event. FIG. 5 should be referred to in conjunction with FIG. 4. In FIG. 5, a graph 52 plots output voltage S-6 and ADC output S-10 vs time, a graph 54 plots pulse timing signal S-12 vs time, a graph 56 plots pile-up reset enable signal S-22b vs time, and a graph 58 plots pile-up reset signal S-24 vs time. Pulse timing signal S-12 in graph 54 shows arrival of a first pulse 54a at time t.sub.1 and arrival of a second pulse 54b at time t.sub.2. In graph 52, pre-amplifier signal S-6 responds in very short time to arrival of first pulse 54a, but the response of ADC output S-10 is slower. Pulse timing signal S-12 is input directly to fast logic unit 22 within reset decision module 16. Upon detecting arrival of first pulse 54a, fast logic unit 22 outputs reset enable signal S-22b, which remains high (enabled) for peaking time t.sub.p as shown in graph 56. Second pulse 54b arrives before peaking time t.sub.p has elapsed after arrival of first pulse 54a. Consequently both pulse timing signal S-12 and reset enable signal S-22b are high when pulse 54b arrives, thereby causing AND gate 24 (see FIG. 4) to output pile-up reset signal S-24 as shown in graph 58. Pile-up reset signal S-24 is transmitted by OR gate 26 as reset signal S-16, which causes micro-reset circuit 8 to reset pre-amplifier 6. The reset of pre-amplifier output voltage S-6 is shown in graph 52 by a downward arrow 53.

[0051] FIG. 6 is a flow chart of an upper level reset logic process as implemented by fast logic unit 22. The flow chart should be referred to in conjunction with FIGS. 4 and 3A. The process starts at step 600, and at step 602 a measurement is made of ADC output S-10. Step 604 tests whether or not ADC output S-10 is above upper ADC level 42, and if not the process loops back to step 602 and continues to measure ADC output S-10. If the test at step 604 determines that ADC output S-10 is above upper ADC level 42, the process continues to step 606 which tests whether or not the crossing occurred during a pulse caused by an incident X-ray. If not, step 608 tests whether or not the most recent pulse ended less than peaking time t.sub.p ago, and if not, a micro-reset is triggered at step 620 by sending upper level reset signal S-22a via OR gate 26 to micro-reset circuit 8. After the micro-reset at step 620 the process loops back to measuring ADC output S-10 at step 602.

[0052] If, at step 606, it is determined that ADC output S-10 crossed upper ADC level 42 during a pulse caused by an incident X-ray, then in order to properly measure the energy of that pulse it is necessary to wait until peaking time t.sub.p has elapsed. Waiting commences at step 610, and fast logic unit 22 at step 614 checks pulse timing signal S-12 throughout the wait time to determine whether or not a second pulse arrives. If not, and if at step 616 the wait time since the last pulse has reached peaking time t.sub.p, then a micro-reset is triggered at step 620 by sending upper level reset signal S-22a via OR gate 26 to micro-reset circuit 8. After the micro-reset at step 620 the process loops back to measuring ADC output S-10 at step 602.

[0053] Similarly, if at step 608 it is determined that the most recent pulse ended less than peaking time t.sub.p ago, in order to properly measure the energy of that pulse it is necessary to wait until peaking time t.sub.p has elapsed. As before, waiting commences at step 610, and fast logic unit 22 at step 614 checks pulse timing signal S-12 throughout the wait time to determine whether or not a second pulse arrives. If not, and if at step 616 the wait time since the last pulse has reached peaking time t.sub.p, then a micro-reset is triggered at step 620 by sending upper level reset signal S-22a via OR gate 26 to micro-reset circuit 8. After the micro-reset at step 620 the process loops back to measuring ADC output S-10 at step 602.

[0054] If at step 614 it is determined that a second pulse arrives before the wait for peaking time t.sub.p after arrival of the first pulse has elapsed, then a pile-up event has occurred prior to the upper level reset. Since pile-up reset enable signal S-22b will be high since arrival of the first pulse (see FIG. 5), and pulse timing signal S-12 will be high upon arrival of the second pulse, micro-reset is triggered at step 620 by AND gate 24 sending pile-up reset signal S-24 via OR gate 26 to micro-reset circuit 8. After the micro-reset at step 620 the process loops back to measuring ADC output S-10 at step 602.

[0055] It should be noted that the upper level reset logic depicted in FIG. 6 and implemented by micro-reset module 16 is an important and novel aspect of the present disclosure.

[0056] FIG. 7 is a flow chart of a pile-up reset logic process as implemented by fast logic unit 22. The flow chart should be referred to in conjunction with FIGS. 4 and 3A. The process starts at step 700, and at step 702 a measurement is made of pulse timing signal S-12. Step 704 determines whether or not a first pulse has occurred. If not, the process returns to measuring pulse timing signal S-12 at step 702. If a pulse is detected at step 704, then step 706 determines whether or not ADC output S-10 is above lower ADC level 41. If not, then pile-up reset may not occur and the process returns to measuring pulse timing signal S-12 at step 702. However, if ADC output S-10 is above lower ADC level 41, then at step 708 fast logic unit 22 outputs pile-up reset enable signal S-22b. The system now enters a waiting state at step 710, and commences measuring pulse timing signal S-12 at step 711. Step 712 represents the function of AND gate 24, namely if pulse timing signal S-12 indicates that a second pulse has arrived and pile-up reset enable signal S-22b is enabled, then micro-reset is triggered at step 720 by AND gate 24 sending pile-up reset signal S-24 via OR gate 26 to micro-reset circuit 8. At the same time that micro-reset is triggered, pile-up enable signal S-22b is disabled at step 716 and the process returns to measuring pulse timing signal S-12 at step 702.

[0057] If, at step 712, pulse timing signal S-12 does not indicate that a second pulse has arrived, then at step 714 it is determined whether or not the wait time since the first pulse has reached peaking time t.sub.p. If not, waiting continues at step 710. If peaking time t.sub.p has elapsed, then no pile-up event has occurred, pile-up enable signal S-22b is disabled at step 716 and the process returns to measuring pulse timing signal S-12 at step 702.

[0058] It should be noted that the pile-up reset logic depicted in FIG. 7 and implemented by micro-reset module 16 is an important and novel aspect of the present disclosure.

[0059] FIG. 8 is a flow chart of a backup reset logic process as implemented by fast logic unit 22. The flow chart should be referred to in conjunction with FIGS. 4 and 3A. As described previously, backup reset logic is available in the event that fast logic unit 22 is disabled or otherwise unavailable, such as during initial manufacturer testing of detector 4 and pre-amplifier 6. The process starts at step 800 and, at step 802, comparator 20 makes a hardware comparison between pre-amplifier output voltage S-6 and the top threshold voltage of pre-amplifier 6. In step 804 it is determined whether or not output voltage S-6 is above its top threshold voltage. It is to be understood that the top threshold voltage is the maximum possible voltage input to ADC 10, and corresponds to the voltage at which ADC output S-6 is equal to top ADC level 43. If output voltage S-6 is not above its top threshold, measurement of output voltage S-6 continues at step 802. If at step 804 it is determined that output voltage S-6 is above its top threshold, then micro-reset is triggered at step 820 by comparator 20 sending backup reset signal S-20 via OR gate 26 to micro-reset circuit 8.

[0060] Although the present invention has been described in relation to particular embodiments thereof, it can be appreciated that various designs can be conceived based on the teachings of the present disclosure, and all are within the scope of the present disclosure.