MULTIPLE MEMORY STATES DEVICE AND METHOD OF MAKING SAME

Abstract

A phase-change material based resistive memory contains a resistive layer and two electrical contacts. After fabrication the memory is subjected to thermal treatment which initiates a transition toward a crystalline state favoring in this way the subsequent obtaining of a large number of resistive memory states.

Claims

1. A phase-change material based resistive memory, comprising: a phase-change material (PCM) resistive layer, wherein the PCM resistive layer is subjected after fabrication to a thermal treatment in an inert atmosphere, which initiates its transition from an amorphous state toward a crystalline state to enable obtaining different resistive memory states, the obtaining comprising applying respective voltage sweeps with different upper voltage limits to the thermally treated PCM resistive layer based on the different resistive memory states.

2. The phase-change material based resistive memory of claim 1, wherein the resistive memory has a planar structure with the PCM resistive layer and two electrical contacts situated in a same plane on the substrate surface.

3. The phase-change material based resistive memory of claim 1, wherein the resistive memory has a vertical structure with two electrical contacts placed below and above the PCM resistive layer.

4. The phase-change material based resistive memory of claim 1, wherein the PCM resistive layer is a Ge—Te layer and is deposited in the amorphous state.

5. The phase-change material based resistive memory of claim 1, wherein the thermal treatment in the inert atmosphere is at a temperature between 190° C. and 210° C.

6. The phase-change material based resistive memory of claim 1, wherein applying the respective voltage sweeps comprise applying voltage pulses with different amplitudes.

7. The phase-change material based resistive memory of claim 1, wherein the resistive memory is set to a large number of the different resistive states by applying the respective voltage sweeps to the PCM resistive layer with the different upper voltage limits.

8. The phase-change material based resistive memory of claim 1, further comprising a pair of electrical contacts on a same plane as the PCM resistive layer.

9. The phase-change material based resistive memory of claim 1, further comprising a first electrical contact above the PCM resistive layer and a second electrical contact below the PCM resistive layer.

10. The phase-change material based resistive memory of claim 1, wherein the resistive memory exhibits a reversible structural phase change between the amorphous state and the crystalline state by switching between the two states.

11. A method of obtaining a multiple states resistive memory based on phase-change materials, said method comprising: depositing a phase-change material (PCM) resistor; annealing the PCM resistor with a thermal treatment in an inert atmosphere after fabrication to initiate its transition from an amorphous state toward a crystalline state; and obtaining subsequently respective resistive states by applying certain respective voltage sweeps with different upper voltage limits to the thermally treated PCM resistive layer based on desired resistive states.

12. The method of claim 11, wherein the certain voltage sweeps are voltage pulses with different amplitudes.

13. The method of claim 11, wherein the respective voltage sweeps are applied to the PCM resistive layer with the different upper voltage limits based on the respective desired resistance states.

14. The method of claim 11, wherein the resistive memory exhibits a reversible structural phase change between the amorphous state and the crystalline state by switching between the two states.

15. The method of claim 11, wherein the resistive memory has a planar structure with the PCM resistor and two electrical contacts situated in the same plane on a substrate surface.

16. The method of claim 11, wherein the resistive memory has a vertical structure with two electrical contacts placed below and above the PCM resistor.

17. The method of claim 11, wherein the PCM resistor is indicative of a PCM resistive layer which is a Ge—Te layer and is deposited in the amorphous state.

18. The method of claim 11, wherein annealing the PCM resistor comprises: annealing the PCM resistor with the thermal treatment in the inert atmosphere at a temperature between 190° C. and 210° C.

19. The method of claim 11, further comprising: depositing a pair of electrical contacts on a same plane as the PCM resistor.

20. The method of claim 11, further comprising: depositing a first electrical contact above the PCM resistor; and depositing a second electrical contact below the PCM resistor.

Description

DETAILED DESCRIPTION OF THE DRAWINGS

[0006] FIG. 1 illustrates a resistive memory structure in accordance with one example.

[0007] FIG. 2 illustrates a resistive memory structure in accordance with another example.

[0008] FIG. 3 illustrates a multiple states memory element in accordance with one example.

[0009] FIG. 4 illustrates a multiple states memory element in accordance with another example.

DETAILED DESCRIPTION

[0010] As discussed herein, the present disclosure is directed toward a nonvolatile memory with multiple resistive states based on phase-change materials (PCM) such as chalcogenides and a method of making the same.

[0011] FIG. 1 shows a cross-sectional view of a PCM resistive memory 100 in accordance with at least one example. The PCM resistive memory 100 may include a substrate 101, a PCM layer 102 and electrical contacts 103. The substrate 101 can be formed from a dielectric material such as glass, high resistivity silicon, silicon carbide, sapphire, high temperature plastic foils, etc. The resistive layer 102 may be formed from a Ge—Te layer. The electrical contacts 103 may be formed by Ti/Au, Al, Mo, ITO, AZO, or any other metallization schema which may be employed for the realization of electrical contacts of PCM memristors. The device may have a planar structure, with the PCM layer 102 and the electrical contacts 103 situated in the same plane, on the surface of the substrate element 101.

[0012] FIG. 2 shows a cross-sectional view of a PCM resistive memory 100 in accordance with at least one example. The PCM resistive memory 100 may include a substrate 201, a PCM layer 202 and electrical contacts 203. The substrate 201 may be formed from a dielectric material such as glass, high resistivity silicon, silicon carbide, sapphire, high temperature plastic foils, etc. The resistive layer 202 may be formed from a Ge—Te layer. The electrical contacts 203 can be formed by Ti/Au, Al, Mo, ITO, AZO, or any other metallization schema which may be employed for the realization of electrical contacts of PCM memristors. The device may have a vertical structure, with the two contacts 203 placed below and above the PCM layer 202.

[0013] For the fabrication of the resistive memory structures presented in FIG. 1 and FIG. 2, standard procedures employed for PCM memristors may be employed. The PCM layer may be deposited by magnetron sputtering. The electrical contacts may be realized by magnetron sputtering, electron-gun evaporation, thermal evaporation or any other deposition method that are usually used in the field. For defining the resistor and the electrical contacts pattern, standard photolithography, electron-beam lithography, mechanical shadow masks or other techniques that are usually used in the field may be employed.

[0014] The Ge—Te layer may be deposited by magnetron sputtering in an amorphous, high resistive state. The Ge—Te layer may be subjected to a specific thermal treatment which may initiate its transition toward the crystalline state. The degree of the initiated crystallinity depends on the thermal treatment temperature and influence also the electrical resistivity of the Ge—Te layer. This crystalline state initialization process may enable subsequent obtaining of a large number of intermediate resistive states between the initial high resistive state and a final low resistive state. The optimum temperature of the thermal treatment may be between 190-210 C. By employing this treatment, the electrical resistivity of the layer may change from larger than 1*10.sup.4 Ω*cm, for the as deposited layer, to 6*10.sup.−3 Ω*cm.

[0015] After performing this crystalline state initialization process by subjecting the Ge—Te layer to a thermal treatment in inert atmosphere (Ar) at the optimum temperature, the subsequent obtaining of a large number of intermediate resistive states between the high resistive state and a low resistive state may be realized by different methods. For example in one embodiment, the obtaining of a large number of intermediate resistive states may be realized by applying pulses (e.g., voltage pulses, current pulses, etc.) with different amplitudes.

[0016] FIG. 3 shows an example of reading a multiple states PCM planar memory element by measuring the currents flowing through the PCM resistor biased at 0.1V in the initial state and after setting the resistor in different resistance states by applying voltage pulses with different amplitudes.

[0017] As shown in FIG. 3, a large number of various resistance states may be obtained.

[0018] In an embodiment, the obtaining of a large number of intermediate resistive states between the high resistive state and a low resistive state on a previously thermally treated PCM resistor may be realized by performing sweeps (e.g., voltage sweeps) with different upper limits.

[0019] FIG. 4 shows an example of reading a multiple states PCM planar memory element by measuring the currents flowing through the PCM resistor biased at 0.1V in the initial state and after setting the resistor in different resistance states by performing sweeps (e.g., voltage sweeps) with different upper limits.

[0020] As shown in FIG. 4, a large number of various resistance states may be obtained by applying this method.

[0021] In one example, the memory elements described in FIG. 3 and FIG. 4 may be employed as a write once, read many times device. Alternatively, the memory element may change resistive state to increase resistance by applying a short but higher amplitude pulse which may lead to local melting toward more of an amorphous state.