Dual-surface polishing device and dual-surface polishing method

Abstract

An inner-periphery-side cutoff part where a polishing surface of an upper plate inclines upward toward an inner periphery part of the upper plate and an inner-periphery-side cutoff part where a polishing surface of a lower plate inclines downward toward an inner periphery part of the lower plate are respectively formed on the respective inner periphery parts of the upper plate and the lower plate, or an outer-periphery-side cutoff part where the polishing surface of the upper plate inclines upward toward an outer periphery part of the upper plate and an outer-periphery-side cutoff part where the polishing surface of the lower plate inclines downward toward an outer periphery part of the lower plate are respectively formed on the respective outer periphery parts of the upper plate and the lower plate, or all of them are formed thereon.

Claims

1. A dual-surface polishing device comprising: an upper plate and a lower plate in the shape of a doughnut, each having a center hole in the central part thereof, rotates the plates by a sun gear which is installed in the respective center holes in the upper plate and the lower plate and an internal gear which is installed on respective outer peripheral parts of the upper plate and the lower plate while sandwichingly holding carriers which hold a wafer by the upper plate and the lower plate and thereby simultaneously polishes both surfaces of the wafers, wherein: an inner-periphery-side cutoff part X.sub.1 where a polishing surface of the upper plate inclines upward toward an inner periphery part of the upper plate and an inner-periphery-side cutoff part Y.sub.1 where a polishing surface of the lower plate inclines downward toward an inner periphery part of the lower plate are respectively formed on the respective inner periphery parts of the upper plate and the lower plate, and an outer-periphery-side cutoff part X.sub.2 where the polishing surface of the upper plate inclines upward toward the outer periphery part of the upper plate and an outer-periphery-side cutoff part Y.sub.2 where the polishing surface of the lower plate inclines downward toward the outer periphery part of the lower plate are respectively formed on the respective outer periphery parts of the upper plate and the lower plate, the inner-periphery-side cutoff parts X.sub.1, Y.sub.1 and the outer-periphery-side cutoff parts X.sub.2, Y.sub.2 are respectively disposed in the form of a ring along the respective inner periphery parts and the respective outer periphery parts of the upper plate or the lower plate, the dual-surface polishing device is controlled in such a manner that when vertical-direction cutoff amounts of the inner-periphery-side cutoff parts X.sub.1, Y.sub.1 are designated by A.sub.1, B.sub.1 (μm) respectively, the A.sub.1, B.sub.1 (μm) satisfy a range of 10 μm≤A.sub.1+B.sub.1≤70 μm, and the dual-surface polishing device is controlled in such a manner that when vertical-direction cutoff amounts of the outer-periphery-side cutoff parts X.sub.2, Y.sub.2 are designated by A.sub.2, B.sub.2 (μm) respectively, the A.sub.2, B.sub.2 (μm) satisfy a range of 10 μm≤A.sub.2+B.sub.2≤70 μm.

2. The dual-surface polishing device according to claim 1, wherein: the dual-surface polishing device is controlled in such a manner that when a diameter of the wafer is designated by R (mm) and horizontal-direction widths of the inner-periphery-side cutoff parts X.sub.1, Y.sub.1 are designated by C.sub.1, D.sub.1 (mm) respectively, the C.sub.1, D.sub.1 (mm) satisfy a range of 0.15×R≤(C.sub.1, D.sub.1)≤0.25×R, and the dual-surface polishing device is controlled in such a manner that when horizontal-direction widths of the outer-periphery-side cutoff parts X.sub.2, Y.sub.2 are designated by C.sub.2, D.sub.2 (mm) respectively, the C.sub.2, D.sub.2 (mm) satisfy a range of 0.15×R (mm)≤(C.sub.2, D.sub.2)≤0.25×R (mm).

3. The dual-surface polishing device according to claim 1, wherein respective inclined surfaces of the inner-periphery-side cutoff parts X.sub.1, Y.sub.1 and the outer-periphery-side cutoff parts X.sub.2, Y.sub.2 are linear inclined surfaces.

4. A dual-surface polishing method of simultaneously polishing both surfaces of wafers by using the dual-surface polishing device according to claim 1.

Description

BRIEF DESCRIPTION OF DRAWINGS

(1) FIG. 1 Schematic sectional diagrams illustrating one example of a polishing device used in a method of an embodiment of the present invention. FIG. 2 A schematic diagram viewing a lower plate of the embodiment of the present invention from an upper surface. FIG. 3 Sectional diagrams along the A-A line in FIG. 2. FIG. 4 An explanatory diagram in a case where a wafer does not reach the innermost outer periphery part of a polishing cloth during polishing. FIG. 5 Schematic diagrams illustrating examples of a sectional shape of an inclined surface of a cutoff part. FIGS. 6(a) and 6(b) Explanatory diagrams illustrating that an influence due to a difference in circumferential speed of an outer periphery part is reduced in comparison with that by a conventional method. FIG. 6(a) illustrates a conventional example in which a polishing pressure is, a constant polishing pressure is imposed on a wafer in-plane and FIG. 6(b) illustrates the present embodiment in which the polishing pressure is lowered on a wafer outer periphery part. FIG. 7 Diagrams illustrating a state where a wafer shape changes with the passage of a polishing time in a general dual-surface polishing process.

EMBODIMENTS TO CARRY OUT THE INVENTION

(2) Next, embodiments to carry out the present invention will be described on the basis of the drawings.

(3) The present invention is improvement of a dual-surface polishing device, which is equipped with an upper plate and a lower plate in the shape of a doughnut, each having a center hole in the central part thereof and to polishing surfaces of which polishing cloths are stuck, rotates the plates by a sun gear which is installed in the respective center holes in the upper plate and the lower plate and an internal gear which is installed on respective outer peripheral parts of the upper plate and the lower plate while sandwichingly holding carriers which hold wafers by the upper plate and lower plate and thereby simultaneously polishes both surfaces of the wafers.

(4) There are no particular limitations on the dual-surface polishing device of the present invention except configurations of both of the upper and lower plates and the polishing cloths which are stuck thereto which will be described later and a general dual-surface polishing device may be used. For example, FIG. 1 is a schematic diagram illustrating one example of the dual-surface polishing device 10 used in an embodiment of the present invention and in this device 10, configurations are the same as those of the general dual-surface polishing device other than configurations of an upper plate 12, a lower plate 13. Incidentally, in FIG. 1 to FIG. 6, the same symbols denote the same components or members.

(5) As illustrated in FIG. 1, the device 10 is equipped with two plates consisting of an upper plate 12 and a lower plate 13 in the shape of a doughnut each provided with a center hole in the central part thereof. Polishing cloths 22 and 23 are stuck to respective entire surfaces of the upper plate 12 and the lower plate 13. Incidentally, a sun gear 24 is provided between the respective center holes of the upper plate 12 and the lower plate 13 and an internal gear 25 is provided on respective peripheral edge parts thereof. An inner diameter of this internal gear 25 is larger than respective outer diameters of the upper plate 12 and the lower plate 13. Carrier plates 14 are installed on the lower plate 13 to which the polishing cloth 23 is stuck so as to be sandwiched by the upper plate 12 and the lower plate 13, and a wafer 16 which acts as a body to be polished is disposed in a holding hole in each of the carrier plate 14.

(6) On the other hand, a slurry supply hole 18 through which slurry (a polishing solution) 17 will be supplied is provided in the upper plate 12, a supply pipe 19 is provided above the supply hole 18 and the slurry 17 which has been supplied from the supply pipe 19 is supplied to the wafer 16 through the supply hole 18. The upper plate 12 is installed so as to mutually face the lower plate 13 in such a manner that the polishing cloth 22 which is stuck to the upper plate 12 comes into contact with a front-side surface of the wafer 16 and the wafer 16 in the carrier plate 14 is sandwichingly held by the upper plate 12 and the lower plate 13 by pressurizing the upper plate 12.

(7) Outer periphery teeth which engage with the sun gear 24 and the internal gear 25 are provided on an outer periphery part of the carrier plate 14. In addition, a shaft 20 is provided in the respective center holes in the upper plate 12 and the lower plate 13 and the carrier plate 14 revolves around the sun gear 24 while rotating as the upper plate 12 and the lower plate 13 are rotationally driven by a not illustrated power source. At this time, the wafer 16 moves as illustrated in FIG. 1 by rotation of the carrier plate 14.

(8) This embodiment is improvement of such a dual-surface polishing device and a characteristic configuration thereof lies in the point that as illustrated in FIG. 1 and FIG. 2, inner-periphery-side cutoff parts X.sub.1, Y.sub.1 and outer-periphery-side cutoff parts X.sub.2, Y.sub.2 are respectively formed on both of respective outer periphery parts and respective inner periphery parts of the upper plate 12 and the lower plate 13 and the inner-periphery-side cutoff parts X.sub.1, Y.sub.1 and the outer-periphery-side cutoff parts X.sub.2, Y.sub.2 are respectively provided in the form of a ring along the respective inner periphery parts or the respective outer periphery parts of the upper plate 12 or the lower plate 13. As another embodiment, the inner-periphery-side cutoff part X.sub.1 where a polishing surface of the upper plate 12 inclines upward toward the inner periphery part of the upper plate 12 and the inner-periphery-side cutoff part Y.sub.1 where a polishing surface of the lower plate 13 inclines downward toward the inner periphery part of the lower plate 13 may be formed simply on the respective inner periphery parts of the upper plate 12 and the lower plate 13 respectively. As another further embodiment, the outer-periphery-side cutoff part X.sub.2 where the polishing surface of the upper plate 12 inclines upward toward the outer periphery part of the upper plate 12 and the outer-periphery-side cutoff part Y.sub.2 where the polishing surface of the lower plate inclines downward toward the outer periphery part of the lower plate may be formed simply on the respective outer periphery parts of the upper plate 12 and the lower plate 13 respectively. The above-described inner-periphery-side cutoff parts X.sub.1, Y.sub.1 and the above-described outer-periphery-side cutoff parts X.sub.2, Y.sub.2 are provided in the form of a ring along the respective inner periphery parts or the respective outer periphery parts of the upper plate 12 or the lower plate 13 respectively, and the cutoff parts X.sub.1, X.sub.2, Y.sub.1, Y.sub.2 are provided on the respective inner periphery parts or the respective outer periphery parts of the upper plate 12 and the lower plate 13.

(9) As illustrated in FIG. 6(a), in a case where a polishing pressure is constant at a plate in-plane, a circumferential speed is larger relative to the wafer at the outer periphery part of the plate than at the plate in-plane (that is, a travelling amount is larger). Therefore, a roll-off amount of a wafer outer periphery part becomes large caused by acceleration of polishing of the outer periphery part of the wafer 16 and so forth. On the other hand, in the dual-surface polishing device 10 of the present invention, as illustrated in FIG. 6(b), the cutoff parts X.sub.1, X.sub.2, Y.sub.1, Y.sub.2 are provided on the respective inner periphery parts or the respective outer periphery parts of the upper plate 12 and the lower plate 13. Thereby, since the polishing pressures of the respective inner periphery parts or the respective outer periphery parts of the upper plate 12, the lower plate 13 are lowered in comparison with the polishing pressure of the plate in-plane, polishing of the outer periphery part of the wafer 16 is slightly suppressed, the roll-off amount of the wafer outer periphery part is lowered in a part surrounded with a dashed line in FIG. 6(b) and thereby flatness of the outer periphery part and the whole-surface shape of the wafer 16 can be improved. In FIGS. 6(a) and (b), a length of a directional line indicates the magnitude of the polishing pressure. It is preferable to form all the inner-periphery-side cutoff parts X.sub.1, Y.sub.1 and the outer-periphery-side cutoff parts X.sub.2, Y.sub.2 as in this embodiment. In general, GBIR which will be described later is often used as an index which indicates the flatness of the whole-surface shape of the wafer 16 and ESFQR which will be described later is often used as an index which indicates the flatness of the outer periphery part of the wafer 16. That is, in a dual-surface polishing method of the present invention, these GBIR and ESFQR can be simultaneously achieved on the wafer 16 after polished.

(10) Here, as illustrated in FIG. 3(a), it is preferable to be controlled in such a manner that when vertical-direction cutoff amounts of the inner-periphery-side cutoff parts X.sub.1, Y.sub.1 are designated by A.sub.1, B.sub.1 (μm) respectively, A.sub.1, B.sub.1 (μm) satisfy a range of 10 μm≤A.sub.1+B.sub.1≤70 μm and to be controlled in such a manner that when vertical-direction cutoff amounts of the outer-periphery-side cutoff parts X.sub.2, Y.sub.2 are designated by A.sub.2, B.sub.2 (μm) respectively, A.sub.2, B.sub.2 (μm) satisfy a range of 10 μm≤A.sub.2+B.sub.2≤70 μm. When A.sub.1+B.sub.1 or A.sub.2+B.sub.2 is less than 10 μm which is a lower limit value, it is hard to sufficiently obtain the effect of reducing the polishing pressure on the outer periphery part of the wafer 16. On the other hand, when exceeding 70 μm which is an upper limit value, a part where the polishing cloth is in contact with the wafer is reduced and the flatness cannot be sufficiently improved. Among them, it is particularly preferable to control in such a manner that A.sub.1, B.sub.1 (μm) satisfy a range of 30 μm≤A.sub.1+B.sub.1≤50 μm and A.sub.2, B.sub.2 (μm) satisfy a range of 30 μm≤A.sub.2+B.sub.2≤50 μm. In addition, since processing is performed while sandwichingly holding the wafers by the upper and lower plates in a dual-surface polishing device, the above-described ranges may be satisfied by A.sub.1+B.sub.1 and A.sub.2+B.sub.2, and A.sub.1 and B.sub.1, and A.sub.2 and B.sub.2 may not be particularly set to the same value.

(11) In addition, as illustrated in FIG. 3(b), it is preferable to be controlled in such a manner that when a diameter of the wafer 16 is designated by R (mm) and horizontal-direction widths of the inner-periphery-side cutoff parts X.sub.1, Y.sub.1 are designated by C.sub.1, D.sub.1 (mm) respectively, C.sub.1, D.sub.1 (mm) satisfy a range of 0.15×R (mm)≤(C.sub.1, D.sub.1)≤0.25×R(mm) and to be controlled in such a manner that when horizontal-direction widths of the outer-periphery-side cutoff parts X.sub.2, Y.sub.2 are designated by C.sub.2, D.sub.2 (mm) respectively, C.sub.2, D.sub.2 (mm) satisfy a range of 0.15×R (mm)≤(C.sub.2, D.sub.2)≤0.25×R (mm). This is because when C.sub.1, D.sub.1, C.sub.2, D.sub.2 are less than a lower limit value, there are cases where boundaries between flat parts and the cutoff parts of the upper and lower plats become discontinuous. On the other hand, when exceeding an upper limit value, a region where the polishing pressure is lowered reaches a part other than the outer periphery part of the wafer 16. Therefore, there are cases where the flatness of the whole-surface shape of the wafer 16 is impaired and GBIR is worsened. Among them, it is particularly preferable to be controlled in such a manner that C.sub.1, D.sub.1 (mm) satisfy a range of 0.15×R (mm)≤(C.sub.1, D.sub.1)≤0.20×R(mm) and C.sub.2, D.sub.2 (mm) satisfy a range of 0.15×R (mm)≤(C.sub.2, D.sub.2)≤0.20×R (mm). Incidentally, it is more preferable that C.sub.1 and D.sub.1 be the same value or more approximate values, because the polishing pressures by the upper and lower plates can be transmitted uniformly to the outer periphery part of the wafer 16. The same is also true of C.sub.2 and D.sub.2.

(12) Incidentally, as illustrated in FIG. 4, in a case where the wafer 16 does not travel to the innermost outer periphery parts of the polishing cloths 22, 23 during polishing, the vertical-direction cutoff amount B.sub.2, the horizontal-direction width D.sub.1 are measured with the most outer-periphery-side point and the most inner-periphery-side point of a polishing cloth 11 where the wafer 16 reaches during polishing being set as starting points respectively. Although not illustrated, the same is true of all the cutoff parts.

(13) In addition, the inclined surfaces of the inner-periphery-side cutoff parts X.sub.1, Y.sub.1 and the outer-periphery-side cutoff parts X.sub.2, Y.sub.2 may be configured by inclined surfaces and so forth including a curved surface as illustrated in FIG. 5(b), FIG. 5(c) in addition to a linear inclined surface such as that as illustrated in FIG. 5(a). Among them, it is preferable to be the linear inclined surface such as that as illustrated in FIG. 5(a) for easiness in processing onto the plates.

(14) As a method of forming the inner-periphery-side cutoff parts X.sub.1, Y.sub.1 and the outer-periphery-side cutoff parts X.sub.2, Y.sub.2 on the upper plate 12, the lower plate 13, for example, a method of grinding the respective inner periphery parts or the respective outer periphery parts of the upper plate 12, the lower plate 13 which are provided on the general polishing device by using a grinding stone and so forth is given.

(15) As described above, if the dual-surface polishing device of the present invention is used, the roll-off amount of the wafer outer periphery part can be decreased and the flatness of the outer periphery part and the whole-surface shape of the wafers can be improved. Incidentally, in the dual-surface polishing method using the above-described dual-surface polishing device of the present invention, there are no particular limitations on a specific procedure and other conditions when performing polishing other than the above-described configurations of the plates and it can be performed under well-known conditions.

EXAMPLES

(16) Next, examples of the present invention will be described in detail together with comparative examples.

Example 1

(17) Dual-surface polishing of wafers was performed by using the dual-surface polishing device 10 illustrated in FIG. 1 and by changing conditions of the vertical-direction cutoff amounts A.sub.1, B.sub.1 of the inner-periphery-side cutoff parts X.sub.1, Y.sub.1, the vertical-direction cutoff amounts A.sub.2, B.sub.2 of the outer-periphery-side cutoff parts X.sub.2, Y.sub.2, the horizontal-direction widths C.sub.1, D.sub.1 of the inner-periphery-side cutoff parts X.sub.1, Y.sub.1, the horizontal-direction widths C.sub.2, D.sub.2 of the outer-periphery-side cutoff parts X.sub.2, Y.sub.2 for every test example as in the following Table 1. Here, silicon wafers which are 300 mm in diameter were used as the wafers. In the respective test examples, A.sub.1=A.sub.2=B.sub.1=B.sub.2. Here, the horizontal-direction widths C.sub.1, D.sub.1 of the inner-periphery-side cutoff parts X.sub.1, Y.sub.1, the horizontal-direction widths C.sub.2, D.sub.2 of the outer-periphery-side cutoff parts X.sub.2, Y.sub.2 were all set to 51 mm. In addition, the cutoff parts were formed by grinding the respective inner periphery parts and the respective outer periphery parts of the upper plate and the lower plate by a grinding machine.

(18) Incidentally, in a test example 1, dual-surface polishing of the wafers was performed without forming the cutoff parts.

(19) Specifically, the dual-surface polishing was performed by using a polishing solution (manufactured by Nitta Haas Incorporated, the product name: nalco2350), a polishing cloth (manufactured by Nitta Haas Incorporated, the product name: suba800), a wafer (a diameter R: 300 mm, a thickness: 790 mm), a carrier (a thickness: 778 mm), under conditions of a plate rotation number: 20 to 30 rpm, a pressure-machined surface: 300 g/cm.sup.2, a target thickness: 780 mm.

(20) <Evaluation>

(21) (i) GBIR: The flatness of the wafer whole-surface after dual-surface-polishing was evaluated by measuring GBIR using a measurement device (manufactured by KLA Tencor Corporation, the type name: Wafer Sight2). As a measurement condition at that time, a measurement range was set to 296 mm with the exclusion of 2 mm of the outer periphery part of the wafer. GBIR (Global Backside Ideal Range) is a value which is used as an index which indicates the flatness of the whole-surface shape of the wafer. This GBIR is obtained by calculating a difference between a maximum thickness and a minimum thickness of the entire wafer with a back surface of the wafer in a case of supposing that the back surface of the wafer has been perfectly adhered by suction being set as a reference.

(22) (ii) ESFQRmax: The flatness of the wafer outer periphery part after dual-surface-polished was evaluated by measuring ESFQRmax using the above-described measurement device (manufactured by KLA Tencor Corporation, the type name: Wafer Sight2). ESFQRmax is the one which indicates a maximum value in the ESFQRs of all sectors (a plurality of fan-shaped regions formed on the wafer outer periphery part) and ESFQR (Edge flatness metric. Sector based, Front surface referenced, Site Front least sQuares Range) is the one that SFQR in the sector was measured. A measurement condition of ESFQRmax is that a region of the wafer outer periphery part of 30 mm except the region of the outermost periphery part of 2 mm was measured by dividing it into 72 fan-shaped sectors.

(23) TABLE-US-00001 TABLE 1 Outer- Inner- Periphery- Periphery- Wafer Side Side Evaluation Diam- Cutoff Cutoff GBIR ESFQRmax eter Part Part (Mean (Mean (R) A.sub.2 + B.sub.2 A.sub.1 + B.sub.1 Value) Value) [mm] [μm] [μm] [μm] [μm] Test Example 1 300 0 0 221 37 Test Example 2 300 10 10 158 30 Test Example 3 300 20 20 144 29 Test Example 4 300 30 30 122 23 Test Example 5 300 40 40 118 22 Test Example 6 300 50 50 111 20 Test Example 7 300 60 60 143 29 Test Example 8 300 70 70 200 35 Test Example 9 300 80 80 236 41

(24) As apparent from Table 1, in comparison with the test example 1 in which the cutoff part is not formed, in the test examples 2 to 8 in which these are formed, GBIR, ESFQRmax indicate low values and it can be seen that excellent flatness was obtained on both of the wafer outer periphery part and the whole-surface shape. On the other hand, in the test example 9 in which the cutoff amount exceeded 70 μm, it can be seen that GBIR, ESFQRmax are more worsened than those of the test example 1.

(25) In addition, it was confirmed that the effect of improving the flatness is obtained from 10 μm in cutoff amount and the flatness becomes favorable in association with an increase in cutoff amount up to 50 μm. On the other hand, when the cutoff amount exceeds 50 μm, a tendency that the flatness is slightly worsened was observed. It is thought that this is because when the cutoff amount is increased, contact between the polishing cloths stuck to the upper plate and the lower plate and the wafer becomes weak and it has led to worsening of the flatness. Judging from results of numerical values of the test examples 2 to 8, it is thought that a range up to 70 μm is favorable for obtaining the effect of improving the flatness.

Example 2

(26) Dual-surface polishing of wafers was performed by using the dual-surface polishing device 10 illustrated in FIG. 1 and changing the conditions of the horizontal-direction widths C.sub.1, D.sub.1 of the inner-periphery-side cutoff parts X.sub.1, Y.sub.1, the horizontal-direction widths C.sub.2, D.sub.2 of the outer-periphery-side cutoff parts X.sub.2, Y.sub.2 for every test example as indicated in the following Table 2. Here, silicon wafers which are 300 mm in diameter were used as the wafers. In addition, a coefficient α indicated in Table 2 is the coefficient α when the cutoff parts were respectively expressed in terms of lengths relative to the wafer diameter R, that is, as C.sub.1, C.sub.2, D.sub.1, D.sub.2=α×R. In addition, in each example at this time, C.sub.1=C.sub.2=D.sub.1=D.sub.2. In addition, the vertical-direction cutoff amounts A.sub.1, B.sub.1 of the inner-periphery-side cutoff parts X.sub.1, Y.sub.1 and the vertical-direction cutoff amounts A.sub.2, B.sub.2 of the outer-periphery-side cutoff parts X.sub.2, Y.sub.2 were all fixed to 50 μm which was decided as an optimum value in the example 1. Other performance conditions and evaluation conditions are the same as those in the example 1. Incidentally, a test example 10 and a test example 14 indicated in Table 2 are the test examples which are the same as the test example 1, the test example 6 indicated in the above-described Table 1 respectively.

(27) TABLE-US-00002 TABLE 2 Outer- Inner- Periphery- Periphery- Evaluation Side Cutoff Side Cutoff ESFQR Part Part GBIR max Wafer C.sub.2, D.sub.2 C.sub.1, D.sub.2 (Mean (Mean Diameter Width Width Value) Value) (R) [mm] Coefficient α [mm] Coefficient A [mm] [nm] [nm] Test 300 0 0 0 0 221 37 Example 10 Test 300 0.10 30 0.10 30 180 41 Example 11 Test 300 0.15 45 0.15 45 122 26 Example 12 Test 300 0.17 51 0.17 51 111 20 Example 13 Test 300 0.20 60 0.20 60 134 22 Example 14 Test 300 0.25 75 0.25 75 143 25 Example 15 Test 300 0.30 90 0.30 90 232 29 Example 16

(28) As apparent from Table 2, it can be seen that improvement is observed in GBIR in the test examples 11 to 15 in comparison with the test example 10 in which the cutoff part is not formed. In addition, ESFQRmax indicates low values in the test examples 12 to 16. From this result, it can be said that the excellent flatness was obtained on both of the outer periphery parts and the whole-surface shapes of the wafers, in particular, in the test examples 12 to 15.

INDUSTRIAL APPLICABILITY

(29) The present invention can be utilized for dual-surface polishing of the wafers for obtaining the flatness of the wafers, for example, in a manufacturing process of semiconductor wafers which are represented by the silicon wafers.