Abstract
A method of producing a light emitting diode (LED) array comprises: forming a plurality of layers (100, 101, 103) of semiconductor material; forming a dielectric mask layer (104) over the plurality of layers, the dielectric mask layer having an array of holes (106) through it each exposing an area of one of the layers of semiconductor material, and growing an LED structure (110, 112, 114) in each of the holes arranged to emit light over a range of wavelengths. At least some of the plurality layers (101) form a distributed Bragg reflector (DBR) arranged to reflect light of at least some of said range of wavelengths.
Claims
1. A method of producing a light emitting diode (LED) array, the method comprising: forming a plurality of layers of semiconductor material; forming a dielectric mask layer over the plurality of layers, the dielectric mask layer having an array of holes through it each exposing an area of one of the layers of semiconductor material, and growing an LED structure in each of the holes arranged to emit light over a range of wavelengths, wherein at least some of the plurality layers form a distributed Bragg reflector (DBR) arranged to reflect light of at least some of said range of wavelengths.
2. A method according to claim 1 wherein at least one of said plurality of layers forms an electrical contact connecting together at least some of the LED structures.
3. A method according to claim 2 wherein said electrical contact is formed between the DBR and the dielectric layer.
4. A method according to any preceding claim wherein the electrical contact is formed of a doped semiconductor material.
5. A method according to any preceding claim wherein forming the DBR comprises forming at least two pairs of layers, each pair comprising a first layer of a first material and a second layer of a second material.
6. A method according to claim 5 wherein one of each pair of layers is formed of a doped semiconductor material and is electrochemically etched to increase its porosity.
7. A method according to claim 6 wherein the other of each pair of layers is formed of un-doped semiconductor material.
8. An LED array comprising a plurality of semiconductor layers, a dielectric layer extending over the semiconductor layer and having an array of LED structures extending through it and arranged to emit light over a range of wavelengths, wherein at least some of the plurality layers form a distributed Bragg reflector (DBR) arranged to reflect light of at least some of said range of wavelengths.
9. An LED array according to claim 8 wherein at least one of said plurality of layers forms an electrical contact layer connecting together at least some of the LED structures.
10. An LED array according to claim 9 wherein said electrical contact layer is between the DBR and the dielectric layer.
11. An LED array according to claim 9 or claim 10 further comprising an electrode formed on the contact layer.
12. An LED array according to any one of claims 8 to 11 wherein the electrical contact comprises a doped semiconductor material.
13. An LED array according to any one of claims 8 to 12 wherein the DBR comprises at least two pairs of layers, each pair comprising a first layer of a first material and a second layer of a second material.
14. An LED array according to claim 13 wherein one of each pair of layers is formed of a doped semiconductor material which has been electrochemically etched to increase its porosity.
15. An LED array according to claim 14 wherein the other of each pair of layers is formed of un-doped semiconductor material.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
[0021] FIG. 1a shows an as-grown template formed in a process according to a first embodiment of the invention;
[0022] FIG. 1b shows the template of FIG. 1a with a masking pattern formed in its mask layer;
[0023] FIG. 1c shows the template of FIG. 1a with micro-LEDs grown in holes in the mask layer to form an LED array;
[0024] FIG. 1d shows the LED array of FIG. 1c with electrical contacts formed on it;
[0025] FIG. 2 is a section through an LED structure of the template of the LED array of FIG. 1d;
[0026] FIG. 3 is schematic cross section through a DBR forming part of the LED array of FIG. 1d; and
[0027] FIG. 4 is a reflectivity curve of the DBR of FIG. 3.
DETAILED DESCRIPTION
[0028] Referring to FIG. 1a, a lower semiconductor layer 100 of group III nitride or other suitable semiconductor, for example a standard un-doped GaN (u-GaN) layer, is initially grown on a substrate 102. The substrate 102 may be a GaN substrate, or may be any foreign substrate such as sapphire, silicon (Si), silicon carbide (SiC) or even glass. The lower semiconductor layer 100 may be grown by means of any standard GaN growth method using either metal-organic vapour phase epitaxy (MOVPE) or molecular beam epitaxy (MBE), or any other suitable growth technique. A plurality of further layers 101 are grown over the lower layer 100. These layers are arranged to form a distributed Bragg reflector (DBR) in which there are alternating layers of two different materials, as will be described in more detail below. An upper semiconductor layer 103 is grown over the DBR layers 101. This layer 103 is arranged to form an electrical contact layer for the LED devices and may for example be of n-type GaN (n-GaN). The contact layer may have a thickness from 50 nm to 10 μm. A dielectric layer 104, such as silicon dioxide (SiO.sub.2) or silicon nitride (SiN), or any other suitable dielectric material, is deposited on the upper semiconductor layer 103 by PECDV or any other suitable deposition technique. The thickness of the dielectric layer may be in the range from 20 nm to 500 μm.
[0029] Referring to FIG. 1b, an array of holes 106 is then formed in the dielectric layer 104. The holes 106 are typically on the micrometer scale and therefore referred to as micro-holes. This may be done by means a photolithography technique and then etching processes (which can be dry-etching or wet-etching). In forming the micro-holes 106, the dielectric layer 104 is etched through its entire thickness down to the upper surface of the upper semiconductor layer 103. If the holes 106 are round, they may have diameters from 1 μm to 500 μm, and the pitch distance, i.e. the distance between the centres of adjacent micro-holes, may be, for example, from 5 μm to 500 μm. Further etching, of the upper semiconductor layer 103, only within the micro-hole areas, may be performed using the remained dielectric layer 104 as a mask. The n-GaN etching depth can be from zero (meaning there is no GaN etching) to 10 μm, depending on the n-GaN layer thickness. Typically the optimum etching method or conditions will be different for the upper semiconductor layer 103 than for the dielectric layer 104. For example, SF.sub.6 etchant can be used to etch the dielectric layer 104, but will not etch the n-GaN layer 100. Therefore etching all of the way through the dielectric layer 104 and stopping at the top surface of the upper semiconductor layer 103 is simple to achieve. This also has advantages for the quality of the LED structures grown in the holes 106.
[0030] The holes 106 are of a round cross section in the embodiment shown, but other cross sections may be used, for example oval or square.
[0031] Next, referring to FIG. 1c, a standard III-nitride LED structure is grown on the exposed areas of the upper semiconductor layer 103. However, because only discrete areas of the upper semiconductor layer 103 are exposed by the micro-holes 106 in the dielectric layer or mask, the LED structures are formed as an array of discrete LEDs 108, separated by the remaining parts of the dielectric layer 104 between the micro-holes 106. The LED structures 108 are grown by either MOVPE or MBE techniques, or any other suitable growth technique. The growth occurs upwards from the exposed areas of the GaN (or other semiconductor) of the upper layer 103, and not from the side walls of the holes 106. Therefore the layered LED structure can be built up inside each of the holes 106 with each of the layers being substantially flat or planar. The LED structures may comprise an n-GaN layer 110, an InGaN prelayer, an active region 112, a thin p-type AlGaN layer as a blocking layer (not shown), and then a final p-doped GaN layer 114. The active region 112 may comprise InGaN based multiple quantum wells (MQWs). A prelayer can be, for example, either an InGaN layer with low indium content and a typical thickness of <100 nm or an InGaN/GaN superlattice with low indium content (the total thickness of the superlattice is typically below 300 nm). An example of an LED structure is described in more detail below with reference to FIG. 2. As mentioned above, due to the dielectric mask 104, the LED structures can be grown only within the micro-holes 106, as shown in FIG. 1c, forming a μLED array.
[0032] It is important that the uppermost layer of the InGaN MQWs 112 should not extend above the upper surface of the dielectric layer 104, which could result in a short-circuit effect after the template is fabricated into a final μLED array. It is also important that the overgrown n-GaN 110 within each of the micro-hole areas directly contact the upper semiconductor layer 103 within the un-etched parts of the template below the dielectric mask 104 so that all the individual μLEDs are electrically connected to each other through the upper semiconductor layer 103 of the un-etched parts below the dielectric mask 104.
[0033] Referring to FIG. 1d, once the LED array structure is completed, further device fabrication is carried out, including the formation of electrical contacts for the array. For example an upper contact layer 116 may be formed over the dielectric mask layer 104 and over the upper p-GaN layer of the individual micro-LED devices 108. The upper contact layer 116 therefore forms a p-contact for all of the LED devices 108. This may be a common p-contact layer for all of the LED devices 108, or may be formed as a plurality of separate areas, each contacting a respective group of one or more of the LED devices, and having a separate contact formed on it. This allows the LED devices 108 to be switched in groups therefore forming an addressable array. The upper contact layer 116 may be formed of ITO or Ni/Au alloys. An anode 118 may then be formed on the p-contact layer 116. For example, a part of the dielectric layer 104 may be etched away and then the part of the LED structure on the etched dielectric layer section may be also etched down to the upper semiconductor layer 103, exposing an area 122 of the n-GaN upper semiconductor layer 103, and a cathode 120 formed on that exposed area 122 of n-GaN.
[0034] In the finished structure as shown in FIG. 1d, light is emitted from each of the LEDs 108 in all directions, but the DBR will reflect light emitted downwards and thereby greatly increase the proportion of light emitted upwards. Generally, a DBR structure shows a very high reflectivity, typically above 90%. Therefore, it will significantly enhance extraction efficiency, meaning that a major part of the emission from individual micro-LEDs will be extracted from the surface, while both the portion of emission emitting from the sidewalls of micro-LEDs and the portion of the emission confined in the GaN as a waveguide under the active region will be reduced or even eliminated in an ideal case. With a proper design (such as by properly designing the layer thickness of the micro-LEDs and the pitch of the micro-LEDs), an extraction efficiency approaching 100% can be obtained due to the photonic crystal effect (refer to Photonic Crystals: Molding the Flow of Light, by J. D. Joannopoulos, R. D. Meade, J. N. Winn, S. G. Johnson, Princeton University Press, 1995) and micro-cavity effect. Cross-talk can therefore be significantly reduced or substantially eliminated.
[0035] It will be appreciated that various modifications to the embodiments described above can be made. For example, in one modification the structure is inverted, with a p-GaN layer being grown on the substrate and covered by the dielectric layer, and then the p-GaN layer of the LED devices 108 being formed first, followed by the multiple quantum well layers, and then the n-GaN layer. An n-contact layer is then formed over the top of the dielectric layer in place of the p-contact layer, and the positions of the anode and cathode are reversed.
[0036] In the configuration of FIGS. 1a to 1d, the overgrown n-GaN 110 within the micro-holes 106 has to match the n-GaN of the un-etched parts of the n-GaN upper semiconductor layer 103 below the dielectric mask 104 so that all the individual μLEDs 108 are electrically connected to each other through the n-GaN layer 103. Instead of using the n-GaN of the un-etched n-GaN parts below the dielectric mask 104 as an electrically connected channel, in a further embodiment, a Group III nitride heterostructure with a two dimensional electron gas (2DEG) at the heterojunction is used as the semiconductor layer, instead of the n-GaN layer. In this embodiment a standard AlGaN/GaN HEMT structure is used. The electron gas (2DEG) with a high sheet carried density and high electron mobility formed at the interface between the AlGaN barrier and the GaN buffer of a high electron mobility transistor (HEMT) structure is used as an electrically connected channel.
[0037] In order to produce such a device, a standard AlGaN/GaN HEMT structure is grown over the DBR layers. For example a GaN layer forming a buffer layer may be grown over the DBR layers then an AlGaN layer forming a barrier layer is grown on the GaN layer. This structure is referred to herein as an “as-grown HEMT template”. Subsequently, a dielectric layer such as SiO.sub.2 or SiN or any other dielectric material, for example with a thickness in the range from 2 nm to 500 μm, is deposited on the as-grown HEMT template by using PECVD or any other suitable deposition technique. The resulting structure will be the same as that shown in FIG. 1a, but with the HEMT structure in place of the upper semiconductor layer 103. After that, by means of a photolithography technique and then etching processes (which can be dry-etching or wet-etching) the dielectric layer is etched down to the surface of the HEMT structure to form a micro-hole array in the dielectric layer, where the micro-hole diameter can be from 1 μm to 500 μm, and the pitch distance between adjacent hole centres may be in the range from 5 μm to 500 μm. Further etching the as-grown HEMT within the micro-hole areas can be performed using the remained regions of the dielectric layer as a mask. The as-grown HEMT etching depth can be from zero (meaning there is no any etching) to 10 μm, depending on the AlGaN barrier position of the as-grown HEMT template. However, generally the etching will extend downwards at least as far as the hetero-interface between the two layers of the as-grown HEMT structure, so as to provide good electrical contact between each of the LED structures and the 2DEG.
[0038] Next, a standard III-nitride LED structure is grown on the dielectric mask patterned HEMT template featured with micro-holes by either MOVPE or MBE technique, or any other epitaxy technique, for example as described above with reference to FIGS. 1c, and contacts provided, for example as described above with reference to FIG. 1d. As with the embodiment of FIG. 1a to 1d, an important point is that the upper surface of the InGaN MQWs 212 should be below the upper surface of the dielectric layer 204 so as to avoid a short-circuit effect after being fabricated into final μLED arrays.
[0039] Referring to FIG. 2, the LED structures in the LED arrays of FIGS. 1a to 1d may have any suitable structure, but in one example they may include the n-GaN layer 210, an InGaN prelayer 216 formed over the n-GaN layer 210, a number of InGaN quantum well layers 212 formed over the prelayer 216, a p-doped blocking layer 218, for example of p-AlGaN, and then the p-GaN layer 214. It will be appreciated that this structure can be varied in a number of ways. As indicated above, it is preferable that the top of the uppermost one of the quantum well layers 212 is below the top of the dielectric layer. It is also preferable that the top of the blocking layer 218 is also below the top of the dielectric layer.
[0040] Referring to FIG. 3, as described above, the DBR layers 101 comprise alternating layers 101a, 101b, of two different materials having different refractive indices, so that light from the LEDs is reflected at the interfaces between the layers 101. The principles of DBRs are well known so will not be described in detail, but the layers 101a, 101b are of approximately equal thickness, and the thickness is approximately one quarter of the wavelength of the light (in the material of the DBR layers) that is to be reflected so as to produce constructive interference of reflected light and destructive interference of transmitted light.
[0041] The DBR structure 101 may be based on an Al(Ga)N/GaN system, meaning a number of pairs of alternating Al(Ga)N and GaN layers grown by MOVPE or MBE or any other growth techniques. The DBR structure may alternatively comprise a number of pairs of alternating GaN and nanoporous GaN layers. In order to produce this structure, a number of pairs of alternating n-doped GaN and un-doped GaN layers can be prepared by MOVPE or MBE or any other growth techniques, and a standard electrochemical (EC) etching is then conducted. The mechanism of EC etching is based on a combination of an oxidation process and then a dissolution process in acidic solution under an anodic bias as described in Y. Hou, Z. Ahmed Syed, L. Jiu, J. Bai, and T. Wang, Appl. Phys. Lett. 111, 203901 (2017). Under a positive anodic bias, the injection current will flow through the n-doped GaN part which is conductive leading to the oxidation of n-doped GaN, and the oxidized layer is then chemically dissolved in an acidic electrolyte, converting the n-doped GaN into nanoporous GaN. Therefore, EC etching can be performed on n-type GaN only, due to its good conductivity, while un-doped GaN which is not conductive remains un-etched.
[0042] Referring to FIG. 4, the reflectivity of a DBR is a function of wavelength, but typically a DBR can be arranged to have a relatively broad range of wavelengths, the stopband 400, over which almost total reflection is achieved. For either the Al(Ga)N/GaN DBR or the GaN and nanoporous GaN DBR, the stopband can be tuned to cover a wide spectral range, from infra-red, through the whole visible, to ultra-violet. The reflectivity is also a function of the angle of incidence of the light on the DBR, but in the LED arrays described above, the main function of the DBR is to reflect light emitted downwards through 180° back in an upward direction so the DBR can be designed to achieve that.
[0043] The reflectivity of a DBR increases with the number of pairs of layers 101a, 101b. Therefore, the DBR structure may have at least 5 pairs of layers, and more preferably at least 10 pairs of layers.
[0044] The LEDs 108 will each emit light over a range of wavelengths. That range of wavelengths can be selected by selecting, among other things, the cross sectional area of the LEDs 108. For example, it has been shown that LEDs grown as described above have a peak wavelength in the red part of the spectrum if their diameter is about 30 μm, in the green part of the spectrum if their diameter is about 20 μm, and in the blue part of the spectrum if their diameter is about 10 μm. If the LEDs all have the same electro-luminescence spectrum, then the DBR can be arranged to have a stopband centred on, or at least including, the peak wavelength of the LEDs. If the LEDs are designed to have different electro-luminescence spectra, with different peak wavelengths, then the DBR can be optimised to provide the best overall reflectivity for the different LEDs.
