Method for the production of a light-to-electricity converter made entirely from silicon for a giant photoconversion

Abstract

The production process according to the invention consists of a nanometric scale transformation of the crystalline silicon in a hybrid arrangement buried within the crystal lattice of a silicon wafer, to improve the efficiency of the conversion of light into electricity, by means of hot electrons. All the parameters, procedures and steps involved in manufacturing giant photoconversion cells have been tested and validated separately, by producing twenty series of test devices. An example of the technology consists of manufacturing a conventional crystalline silicon photovoltaic cell with a single collection junction and completing the device thus obtained by an amorphizing ion implantation followed by a post-implantation thermal treatment. The modulation of the crystal, specific to the giant photoconversion, is then carried out on a nanometric scale in a controlled manner to obtain SEGTONs and SEG-MATTER which are active both optically and electronically, together with the primary conversion of the host converter.

Claims

1. A production process of an all-silicon light-to-electricity giant photoconversion device having nanoscopic subsystems conditioned in specific arrangements within crystalline silicon, comprising: performing localized nanoscale transformation of a crystalline silicon material, the performing of the transformation including: performing ion implantation in a crystalline silicon mat trial, followed by performing at least one sequence of thermal treatment resulting in solid phase epitaxy, wherein the ion implantation is performed at a predetermined density and depth by directing a wide defocused beam of an ion implanter through an implantation mask at a density of below 10.sup.15 cm.sup.−2 and an energy in a range of from 30 to 200 keV, so as to obtain an amorphized nanolayer having a thickness of about 5 to about 10 nm located at a depth adapted for absorption of photons and generation of secondary electrons, wherein the nanolayer contains an ordered super-lattice of homogeneously distributed divacancies, and wherein the at least one sequence of thermal treatment resulting in solid phase epitaxy is performed so as to stabilize the divacancies by generating an increased mechanical stress resulting from dilatation during the solid phase epitaxy, so that the divacancies do not recombine at a temperature greater than 250° C., wherein the performing of the transformation creates an arrangement of a metamaterial nanolayer forming a crystalline superlattice system around amorphizations buried within a crystalline mass of the silicon material, according to the distribution and the depth determined by the ion implantation, the metamaterial nanolayer being delimited by nanomembranes, so as to improve the efficiency of the light-to-electricity conversion, by secondary generation by hot electrons.

2. The production process according to claim 1, wherein the performing of the localized nanoscale transformation comprises: a) selecting the crystalline silicon material; b) cleaning the crystalline silicon material; c) performing thermal oxidation of the crystalline silicon material; d) forming a back surface field (BSF) on a rear face of the crystalline silicon material; e) forming a PN junction and an emitter by performing n-type doping diffusion on a front surface of the crystalline silicon material; f) performing the ion implantation by performing implantation of phosphorus ions into a front face of the crystalline silicon material; g) performing the at least one sequence of thermal treatment; h) preparing the crystalline silicon material for an additional ion implantation by reactive ion etching (RIE) or chemical etching; i) optionally, protecting some parts of the crystalline silicon material from the additional ion implantation by photolithography, so that all or part of the material as unprotected surfaces; j) performing the additional ion implantation by performing implantation of phosphorus and/or silicon ions on the unprotected surfaces of the crystalline silicon material; k) subjecting the crystalline silicon material to annealing; l) performing metallization of the rear face of the crystalline silicon material; and m) performing metallization of the front face of the crystalline silicon material.

3. The production process according to claim 1, wherein the performing of the ion implantation is carried out by stabilizing and controlling the wide defocused beam so as to produce an extended defocused ion spot.

4. The production process according to claim 2, comprising: before the performing of the thermal oxidation c), subjecting surfaces of the crystalline silicon material to cold polishing to free it from any native oxide; in the forming of the PN junction e), performing diffusion from a nanosource of P.sub.2O.sub.5, according to a P profile, to form a P.sub.2O.sub.5 surface nanolayer; in the performing of the additional ion implantation j), performing implantation of ions through the surface nanolayer; and in the performing; of the annealing k), performing the annealing resulting in solid phase epitaxy so as to release and further stabilize the divacancies.

5. The production process according to claim 2, wherein: in the selecting of the crystalline silicon material a) the crystalline silicon material is a CZ or FZ silicon wafer having a <100> crystallographic orientation, a thickness in a range of from 150 to 500 micrometers, and a diameter of 4 inches or more, wherein the performing of the ion implantation f) is preceded by the following: performing a p-type rear face pre-doping comprising a homogeneous density of boron, with a density of about N.sub.a˜1-5.10.sup.15 per square centimeter, performing sacrificial oxidation of front face of 50 nanometers at a temperature below 100 degrees Celsius,. performing a first implantation (BSF) on the rear face of the silicon wafer with boron, with a maximum density profile at a surface/interface, except in an alignment zone, performing etching of SiO.sub.2 from the front face of the silicon wafer, HF buffer, except in the alignment zone performing pre-deposition on the front face of the silicon wafer of a phosphorus source to carry out n-type doping by diffusion, performing a second and implantation of phosphorus on the front face of the silicon wafer, except on the alignment zone, performing partial etching by chemical stripping of SiO.sub.2 on the rear face of the silicon wafer, respecting an alignment pattern of contact fingers, wherein the performing of the metallization the rear face with of the crystalline silicon material ) is carried out so as to form an aluminum layer, followed by etching of the alignment pattern on the rear face, and wherein the performing of the metallization of the front face of the crystalline silicon material m) is preceded by performing slow etching on the front surface of the crystalline silicon material so as to remove any SiO.sub.2 layer, and is performed so as to obtain a tri-layer metallized layer of a front face grid with Ti/Pd/Ag, followed by etching of the tri-layer metallized layer in the alignment zone, infrared alignment, and etching of the tri-layer metallized layer.

6. The production process according to wherein the performing of the ion implantation comprises: 1) performing RCA cleaning, 2) performing thermal oxidation to obtain a thermal oxide layer to a depth of 1000 Å, 3) performing a first implantation of boron through the rear face of the crystalline silicon material and the thermal oxide layer, 4) depositing resin on the rear face, 5) performing photolithography of the rear face to obtain a calibration figure, 2 6) performing thinning of the front face of the crystalline silicon material, 50 Å, 7) removing the resin on the rear face, 8) applying a polysilicon layer having a thickness of 0.2 micrometers on the crystalline silicon material, and applying the implantation mask on the polysilicon layer, 9) performing photolithography of different fingers with different spacings on the polysilicon laver, all the fingers having an identical width of 500 micrometer. 10) performing a second ion implantation of amorphizing phosphorus, 180 keV, 7.10.sup.14 At/cm.sup.2, 11) removing all of the polysilicon layer, and 12) performing a third implantation of phosphorus with an overdoping profile, 0.25 keV, 7.10.sup.1At/cm.sup.2, and wherein the method additionally comprises, after the performing of the at least one sequence of thermal treatment: 13) providing a first protective resin for protection of the front face of the crystalline silicon material, 14) performing photolithographic etching of a grid comprising contact fingers on the rear face, 15) performing photolithographic etching of contact fingers having a thickness of 1000 Å, 16) removing the first protective resin from the front face, 17) depositing an aluminum layer on the rear face having a depth of 2 mircometers, 18) providing a second protective resin for protection of the rear face, 19) performing photolithography of a grid on the front face, 20) performing photolithogrpahy etching of the comb by etching 50 Å of SiO.sub.2, 21) removing the second protective resin from the rear face, 22) etching contacts for removal, 23) depositing a double layer Ti/Au-150 microns/1 micron, 24) performing lifting (lift off), 25) depositing a layer of SiO.sub.2 by CVD or cathode sputtering on the front face, 26) providing a third protective resin of protection of the rear face, 27) performing photolithographic etching of the front face contacts, 28) performing oxide-assisted photolithographic etching of the front face contact, 29) removing the third protective resin on the rear face, and 30) performing annealing of the contacts under N.sub.2H.sub.2 .

7. The production process according to claim 2, wherein the performing of the thermal oxidation c, is carried out in an oxidation oven, designed for microelectronics, reaching 1000° C. under N.sub.2, O.sub.2, H.sub.2, HCl in gaseous form and an oxide layer having a thickness ranging from 0.5 to 1.6 microns.

8. The production process according to claim 2, wherein the forming of the back surface field (BSF) d) comprises performing boron ion implantation by a boron ion implanter.

9. The production process according to claim 2, wherein the performing of the ion implantation f) is performed using a beam current of 3 microamperes or more, an acceleration voltage ranging from 5 to 200 keV, up to 125 atomic mass, with a capacity to process silicon wafer samples having diameters of 1 cm.sup.2 or more.

10. The production process according to claim 3, comprising forming a front surface field (FSF) by performing ion implantation comprising performing phosphorus ion implantation by a phosphorus ion implanter.

11. The production process according to claim 2, wherein the performing of the additional ion implantation j) is carried out by reactive ion etching (RIE) with an inductively coupled plasma, an RF induction power of 600W at 13.56 MHz, an RF clamping power of 600 W, a processing temperature of 10 to 20 degrees Celsius, and a gas selected from the group consisting of SF.sub.6, CF.sub.4, O.sub.2, CHF.sub.3, Ar, and mixtures of two or more thereof, with cooling of the rear face of the crystalline silicon material by helium.

12. The production process according to claim 6, comprising performing an additional ion implantation after the performing of the ion implantation, wherein the performing of the ion implantation and the performing of the additional ion implantation are carried out by the same ion implanter.

13. The production process according to claim 2, herein the performing of the metallization of the rear face of the crystalline silicon material l) is performed by a cathode sputtering machine.

14. The production process according to claim 2, comprising forming a protective layer having a thickness of at least 100 nanometer, made of SiO.sub.2 for electrical passivation, using an LPCVD oven with a gas selected from the group consisting of Na, NH.sub.3, SiH.sub.4, SiH.sub.2Cl.sub.2, N.sub.2O, and mixtures of two or more thereof.

15. The production process according to claim 2, comprising performing a final cleaning with a class 100 cleaner, designed for atmospheric control, and drying by a nitrogen dryer with ion-free water.

16. The production process according to claim 3, wherein the performing of the at least one sequence of thermal treatment g) is carried out at about 500° C., and the performing of the annealing k) comprises heating and cooling steps, wherein the performing of the at least one sequence of thermal treatment g) and the performing of the annealing k) are carried out in a same oven.

17. The production process according to claim 2, wherein the performing of the at least one sequence of thermal treatment g) includes at least one thermal treatment at a temperature range up to of 700° C.

18. The production process according to claim 2, comprising depositing a 100-nanometer protective SiO.sub.2 layer for electronic passivation of the giant photoconversion device, the layer being deposited by LPCVD at a temperature below 350° C., wherein a gas of the LPCVD is selected from the group consisting of N.sub.2, NH.sub.3, SiH.sub.2Cl.sub.2, N.sub.2O, and mixtures of two or more thereof.

19. A light-to-electricity converter, comprising an all-silicon light-to-electricity giant photoconversion device as resulting from the process according to claim 1.

20. A giant photoconversion photovoltaic cell, comprising at least one light-to-electricity converter according to claim 19 and a collection junction.

21. The production process according to claim, wherein the performing of the ion implantation comprises: 1) performing RCA cleaning, 2) performing thermal oxidation to form a thermal oxide layer having a thickness of 1000 Å, 2 3) performing a first implantation of boron on the rear face of the crystalline silicon material through the thermal oxide layer, 2 4) providing the first protective resin for protection of the front face. 5) performing lithographic etching of an active zone and of calibration figure of the front face, 6) removing any SiO.sub.2 from the front face, 7) removing the first protective resin on the front face, 8) depositing P.sub.2O.sub.5 oxide on the front face from a diffusion source through a passivation layer, 9) performing P diffusion, 10) thinning of P.sub.2O.sub.5 oxide on the front face, 11) performing annealing of the P diffused in the performing of the P diffusion 9), 12) providing the implantation mask, by deposition of a layer of polysilicon having a thickness of 0.2 micrometers, 13) performing photolithographic etching of the layer of polysilicon, providing several spacings between fingers, the spacings being selected from the group consisting of 100, 200, and 500 micrometers, the fingers have a width of 500 nanometers, 14) performing a second implantation of phosphorus on the front face, with 180 keV and 7.10.sup.14 At/cm.sup.2, and 2 15) removing entirely the layer of polysilicon.

Description

8. BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1: represents a general flowchart of all the important manufacturing steps of a giant photoconversion device.

(2) FIG. 2: is a table showing the process step by step.

(3) FIG. 3: a schematic view in cross-section of a light-to-electricity converter, as resulting from an implementation of a process according of the invention.

(4) FIG. 4: a schematic front view of a giant photoconversion photovoltaic cell including a light-to-electricity converter and a collection junction, as resulting from an implementation of a process according to the invention.

9. FULL DESCRIPTION OF THE MANUFACTURING PROCESS

(5) The invention encompasses and contains the bases and the general process, which are exposed below in accordance with the succession of the main steps. The following is a short but complete descriptive list, presented as an example of the main manufacturing specifications adapted to a complete industrial manufacturing process.

(6) Generally, the production process in small series of giant photoconversion devices is based on a multi-step treatment of silicon wafers. The number of these steps depends, among other things, on the initial state of the silicon wafers, which are supplied in a more or less preconditioned state.

(7) Examples of a few main process steps are mentioned below:

(8) Choice of the silicon wafer thickness: the thickness must be adapted to all the technological operations from a mechanical standpoint.

(9) Surface: The first manufacturing steps concern the surface quality of the silicon wafer (RCA, microelectronic purification), cold polishing of the silicon wafer surface to free it from native oxide.

(10) Sacrificial oxidation: so-called deep oxidation (at 100 nanometers) followed by etching of the initial oxidation (95 nanometers), with preservation of a SiO.sub.2 nanolayer (thickness of about 5 nanometers) as electronic passivation of the surface. or total etching of the initial oxidation followed by 70 nm deposition serving as a nanolayer source of P.sub.2O.sub.5 diffusion, followed in turn by etching to a thickness of 5 nm.

(11) Electronic passivation during manufacturing: preservation of a nanolayer (thickness of about 5 nanometers) of SiO.sub.2 or P.sub.2O.sub.5 after oxidation and diffusion, to protect the silicon surface during implantation.

(12) Diffusion of donors: diffusion of phosphorus from the nanolayer source of P.sub.2O.sub.5 to establish a P profile and create an interface of the PN junction.

(13) Protective masks: intermittent protection of the front and rear surfaces between successive technological operations.

(14) Implantation: amorphizing implantation of ions through protective surface nanolayers (thickness of about 5 nanometers), with a requirement of excellent geometric planarity characteristics.

(15) Implantation masks: for discontinuous amorphization operations, corresponding to patterns of buried substructures.

(16) Thermal treatment: annealing adapted to the regime of admissible temperatures corresponding to the deposition of the thermal energy required to modulate the transformed material through a solid phase epitaxy.

(17) Conditioning of SEGTONs and SEG-MATTER: slowed-down solid phase epitaxy ensuring the calibration of active subsystems.

(18) Underground substructures: Active subsystems inserted in the emitter according to the confirmed converter architecture.

(19) Electronic passivations: passivation and electronic protection layers deposited after the conditioning processes of the SEGTONs and SEG-MATTER.

(20) Rear surface: creating an acceptor profile (B) by diffusion or by implantation to form a BSF (English acronym for Back Surface Field); electronic passivation; rear mirror; contact grid.

(21) Rear mirror: system of SiO.sub.2/Al layers on the rear face for optical trapping.

(22) Annealing and contact conditioning.

(23) In the following, a few selected examples of the entire manufacturing process are described in correctly arranged sequences of operations, which are already known individually, especially in microelectronics, but must be parameterized according to the specificities of a production cycle of a giant photoconversion device.

Examples of Sequence of Operations of a Manufacturing Cycle

(24) 9.1 Pre-Doped Silicon Wafer, Preferentially with Boron

(25) *Monocrystalline silicon wafer CZOCHRALSKI-CZ-Si or with FZ-Si float zone.

(26) *Phosphorus (P) doping, preferentially in the order of 10.sup.18 per cubic centimeter, with boron (B) pre-doping at usual concentration in the order of 10.sup.15 per cubic centimeter.

(27) *Front and rear face cleaned, but not necessarily polished.

(28) *Crystalline orientation <100>.

(29) 9.2 Cleaning

(30) *RCA bath in a chemical cleaning station.

(31) *Cleaning by sacrificial thermal oxidation at a temperature of 850° C. for approximately 2 hours leading to a sacrificial SiO.sub.2 layer having a thickness of from 50 to 100 nanometers.

(32) 9.3 Thermal Oxidation

(33) In an oxygen ion diffusion oven.

(34) 9.4 Formation of a Field at the Rear Face

(35) *By implantations of boron ions with a relatively low energy at a few degrees of offset angle with respect to the vertical, to avoid ion channeling.

(36) *The penetration depth comes from the implantation energy, which is precisely determined by simulations using software like SRIM/TRIM; for example, 25 keV through a SiO.sub.2 passivation layer having a thickness of 100 nanometers, with the dose: 5−10×10.sup.14 per square centimeter.

(37) 9.5 Front Face Formation, n-Type Doping Diffusion

(38) *Etching of the protective SiO.sub.2 passivation layer.

(39) *Deposition of the surface source of phosphorus diffusion, for example, a nanolayer of P.sub.2O.sub.5.

(40) *Diffusion at so-called low temperature (<1000° C.) of phosphorus from the surface source.

(41) *Formation of the PN junction and of the emitter.

(42) 9.6 Front Face Operations—Ion Implantation

(43) *Etching of the P.sub.2O.sub.5 diffusion source layer to 5 nanometers thick to form a protective nanolayer.

(44) *Implantation of phosphorus ions through the protective P.sub.2O.sub.5 nanolayer, with an offset angle of a few degrees relative to the vertical, to avoid ion channeling.

(45) *The implantation depth depends on the implantation energy, determined by simulation, using a numerical code, for example SRIM/TRIM.

(46) *Amorphizing implantation energy: 30-200 keV.

(47) *The implantation dose is established below 10.sup.15 ions per square centimeter.

(48) 9.7 Thermal Treatment

(49) *First thermal treatment applied to reduce the thickness of the amorphized nanolayers and reciprocally dilute amorphized inclusions in the crystalline phase and crystalline inclusions in the amorphized phase within the amorphized-crystalline phase transition zone.

(50) *Annealing thermal cycle—formation and conditioning of buried substructures composed of amorphizations and of systems of transformed and specifically structured crystalline Si nanolayers.

(51) Note: The post-implantation thermal treatment that follows a so-called direct amorphization is significantly simplified and has an improved thermal budget particularly suitable for serial mass production.

(52) According to this thermal treatment, the annealing temperatures are up to 700° C., which proves particularly favorable for the neutralization or heal of practically all extensive post-implantation structural defects, in order to obtain a more efficient material.

(53) For example, the process is carried out in the same way by adjusting the annealing temperature and the thermal cycle to the quality of amorphization.

(54) 9.8 Reactive Ion Etching (RIE) or Chemical Etching

(55) *Objective: remove the protective SiO.sub.2 passivation layer (100 nanometers) according to a pattern to allow metallization by inductively coupled plasma etching (RIE).

(56) *Chemical etching.

(57) *A 5-nanometer thin layer is always preserved to protect the surface of the semiconductor; instead of SiO.sub.2, it is possible to use the P.sub.2O.sub.5 that remains after the phosphorus diffusion process.

(58) 9.9 Implantation Masks—Photolithography Example

(59) *Objective: embed discontinuous amorphized substructures by amorphizing implantations through an implantation mask with different patterns and geometries according to the requirements imposed by the electronic transport.

(60) *Conventional realization with a photolithographic mask and illumination by a mercury vapor lamp.

(61) *The operation has many intermediate steps using masks with different patterns.

(62) *Covering with photoresist to protect the lower and upper faces in an intermediate manner.

(63) *Exposure to light: all the reactions mentioned above are induced by light.

(64) *Chemical processes: removal of fragments according to the selected patterns.

(65) 9.10 Ion Implantation for Wide Defocused Beam Amorphization, So-Called Direct Amorphization

(66) The conventional amorphization using a focused ion beam scanning the surface of the Si wafer inevitably introduces numerous structural defects. As such, this operation is not usable for the industrial manufacture of converters with secondary generation. The disqualifying aspects can be summarized as follows: poor control of the modulation of the material during the local impact of the ion beam and, consequently, of its post-implantation annealing; exaggerated requirements regarding the thickness of the initial amorphization to keep sufficient room for performing the healing recrystallization; severe limitations on the design and architecture of the converter because of the location of sub-structures buried within the crystal lattice; obstructions to electron transport around the nanostructures buried within damaged material; complications concerning the collection of both secondary and primary charge carriers.

(67) It is known to persons skilled in the art that a post-implantation thermal treatment heals a few types of structural defects. For reasons imposed by the conditions of manufacture and the packaging of the SEG-MATTER, this treatment is performed in a well-delimited range of suitable temperatures and with a reasonable thermal budget from the manufacturing standpoint.

(68) There are various combinations that lead to the emitter structure of the GPC converter using diffusion and/or implantations of doping impurities.

(69) In the first case (phosphorus implantations), both the dopant profile and the front surface electric field (FSF), as well as the modification of the crystalline structure, are the result of ion implantations (preferably phosphorus with regard to amorphization).

(70) In the second case (diffusion of doping impurities), the profile of the dopant is made by diffusion (preferably phosphorus), while the modification of the crystalline structure is the result of ion implantation (preferably phosphorus or silicon).

(71) The modification of the crystalline structure compliant with industrial requirements should be:

(72) *Made by an ion implanter with wide defocused beam, securely stable and homogeneous, ensuring industrially useful amorphization (direct amorphization).

(73) *Implantation of phosphorus or silicon made with energies of 80-180 keV and with a density of 6 to 10×10.sup.14 ions per square centimeter.

(74) *In the case where the phosphorus diffusion has been made beforehand, in order to obtain buried amorphization, silicon ions can be implanted instead of phosphorus ions.

(75) 9.11 Post-Implantation Thermal Treatment Cycle

(76) The low thermal budget treatment is substantially shorter than 30 minutes at a temperature of about 500° C. in a tray oven, followed by progressive cooling. In some special cases, a short-sequence thermal cycle is possible.

(77) 9.12 Metallization of Rear Contacts

(78) A superposition of the effects of optical confinement (Si0.sub.2/Al mirror) and of collection at the rear face by a comb combined with a full-surface contact in aluminum.

(79) 9.13 Metallization of the Front Contacts

(80) This concerns, for example, multilayer grid metallization: titanium/palladium/silver.

(81) 9.14 LPCVD or SiO.sub.2 Deposition by Cathode Sputtering

(82) Objective of the LPCVD: complement the basic SiO.sub.2 layer having a thickness of 5 nanometers by a complete protection SiO.sub.2 layer of about 100 nanometers (to ensure an efficacious electronic passivation). It is made, for example, in a tube of a suitable material, brought to and stabilized at 420° C. for 20 minutes; the deposition process lasts 5 minutes.

(83) Objective of the cathode sputtering: complement the SiO.sub.2 protection layer of about 5 nanometers by a layer of SiO.sub.2 of 100 nanometers (to ensure an efficacious electronic passivation):

(84) *The operation is performed at room temperature

(85) *The pressure is 2×10.sup.−3 mb

(86) *The power is 200 W

(87) *The distance to the targeted silicon wafer is 100 nanometers

(88) *The duration of the operation is in the order of 13 minutes

(89) 10. Production Process in Small Series of Giant Photoconversion Devices—Multi-Stage Treatment of Silicon Wafers

(90) The number of processing steps depends inter alia on the initial state of the purchased silicon wafers. The main manufacturing steps concern:

(91) Surface: the required surface quality of the silicon wafer can be obtained by RCA treatment, microelectronic purification, cold polishing to free it from native oxide.

(92) Thickness of the silicon wafer: must be adapted to all the subsequent technological operations.

(93) Sacrificial oxidation: deep oxidation (at 100 nanometers), etching of the initial oxidation (95 nanometers), preservation of a nanolayer as protective nanolayer (thickness of about 5 nanometers) or of the pure silicon surface itself, ready for a P.sub.2O.sub.5 deposit as the nanolayer source of P diffusion.

(94) Protective masks: protected surface between successive operations, as well as amorphizing implantation masks corresponding to substructure patterns.

(95) Back surface: p-type profile, B acceptor profile by diffusion or implantation, BSF, passivation, rear mirror, contact grid. Front surface: n-type profile, P donor profile by diffusion from the source in the form of a P.sub.2O.sub.5 nanolayer, PN junction interface.

(96) Buried substructures: active substructures inserted into the emitter and having excellent geometric planarity characteristics, concept of the particular converter architecture.

(97) Implantation: implantation of ions through the protective nanolayer (thickness of about 5 nanometers).

(98) Thermal treatment: adapted deposition of thermal energy to modulate and condition the transformed material.

(99) Conditioning of SEGTON and SEG-MATTER: solid phase epitaxy with calibration of the active subsystems in their environment.

(100) Rear mirror: Rear mirror of SiO.sub.2/Al on the rear face for optical trapping. Contacts activation annealing.

(101) 11. Production Process in Small Series of Giant Photoconversion Devices—Insertion of the Nanoscopic Systems into Silicon Wafers—Example of a Cycle with Non-Mutually Exclusive Sequences

(102) Example of operations leading to the insertion of nanoscopic systems in an all-silicon light-to-electricity giant photoconversion device; main steps and their characteristics:

(103) *silicon used: CZ or FZ silicon wafer having a <100> crystallographic orientation,

(104) *thickness of the silicon wafer used: approximately 150-500 micrometers,

(105) *diameter of the silicon wafer used: 4, 6 or 12 inches,

(106) *p-type pre-doping: homogeneous density of boron with a density of about N.sub.a˜1-5.10.sup.15 cm.sup.−2—the operation must leave the maximum useful lifetime of minority carriers in the base of the converter (avoiding activation of unintentional impurities and defects),

(107) *sacrificial oxidation of 50 nanometers at a temperature below 100° C.,

(108) *first implantation (BSF) on the rear face with boron, at a density of 10.sup.15 cm.sup.−2, with a maximum density profile at the surface/interface, except in the alignment zone (using the mask of the metal rear grid),

(109) *etching of the SiO.sub.2 from the front face, using HF buffer, except in the alignment zone,

(110) *pre-deposition on the front face of a phosphorus source to carry out n-type doping by diffusion,

(111) *the low-temperature diffusion profile is determined in a predictive manner by a simulation software, for example, ATHENA (registered trademark),

(112) *second implantation of phosphorus on the front face, energy: 50-180 keV, dose 8.10.sup.14 cm.sup.−2, except on the alignment zone (using the implantation masks),

(113) *thermal treatment cycle determined predictively by a simulation code,

(114) *partial etching by chemical stripping of the SiO.sub.2 on the rear face, respecting the pattern of the contact fingers using a mask,

(115) *metallization of the rear face with a 1-micron aluminum layer,

(116) *etching of the alignment pattern on the rear face (one mask for the alignment),

(117) *slow etching of the SiO.sub.2 layer on the front face using HF:H.sub.2O,

(118) *three-layer metallization of the front face grid: Ti/Pd/Ag,

(119) *etching of the metallized layer of the upper face in the alignment zone (two masks for the alignment),

(120) *infrared alignment,

(121) *etching of the metallized layer of the front face (mask of the front face grid).

(122) 12. Production Process in Small Series of Giant Photoconversion Devices—Example

(123) A: Implantation, Amorphization and n-Type Doping Using Phosphorus Ions—Example of a Cycle with Non-Mutually Exclusive Sequences

(124) A. Implantation Only

(125) An exemplary solution of the process based solely on ion implantations, characterized by the following steps:

(126) 1) RCA cleaning.

(127) 2) Thermal oxidation 1000 Å.

(128) 3) Implantation No. 1: boron through the rear face and the thermal oxide 1000 Å.

(129) 4) Resin deposition on the rear face.

(130) 5) Photolithography of the rear face and calibration figure (mask 1).

(131) 6) Thinning of the front panel, to 50 Å.

(132) 7) Removal of the resin protection on the rear face.

(133) 8) Implantation mask applied onto a layer of polysilicon having a thickness of 0.2 micrometers.

(134) 9) Photolithography of different fingers with different spacings on polysilicon (100, 200 micrometers, all having an identical width of 500 micrometers (mask 6).

(135) 10) Implantation No. 2: implantation of amorphizing phosphorus in channel 0. 180 keV, 7.10.sup.14 At/cm.sup.2.

(136) 11) Total removal of the polysilicon.

(137) 12) Implantation No. 3 with an overdoping profile; phosphorus is used for the channel of the front face, with the following characteristics: 0.25 keV, 7.10.sup.14 At/cm.sup.2.

(138) 13) Post-implantation thermal treatment.

(139) 14) Treatment of two sets of silicon wafers in a “perfect” parallel diffusion mode.

(140) 15) Intermediate protection of the front face.

(141) 16) Photolithographic etching of the grid finger on the rear face.

(142) 17) Photolithographic etching of the 1000-Å SiO.sub.2 contact finger.

(143) 18) Removal of the protective resin from the front face.

(144) 19) Total treatment of the rear face of the silicon wafer with a 2-micrometer aluminum deposit.

(145) 20) Resin protection of the rear face.

(146) 21) Photolithography of the front face comb (mask 3).

(147) 22) Lithography of the comb by etching 50 Å of SiO.sub.2.

(148) 23) Removing the resin protection from the rear face.

(149) 24) Etching the contacts (mask 4) for removal.

(150) 25) Deposition of a double layer Ti/Au—150 microns/1 micron.

(151) 26) Removal by lifting (lift-off).

(152) 27) Deposition of SiO.sub.2 by CVD or cathode sputtering on the front face.

(153) 28) Protection of the rear face with resin.

(154) 29) Photolithographic etching of the front face contact (mask 5).

(155) 30) Oxide-assisted photolithographic etching of the front face contact.

(156) 31) Removal of the protective resin on the rear face.

(157) 32) Annealing of the contacts under N.sub.2H.sub.2 atmosphere for characterization during treatment.

(158) 33) Protection with resin on the front face for cutting.

(159) 34) Cutting the cell on the silicon wafer by sticking it on blue adhesive tape.

(160) 13. Production Process in Small Series of Giant Photoconversion Devices—Example

(161) B: n-Type Doping Using Phosphorus Diffusion, Amorphizing Implantation Using Phosphorus Ions—Example of a Cycle with Non-Mutually Exclusive Sequences

(162) B. Diffusion and Implantation

(163) An exemplary solution of the process based on diffusion and implantation of ions, characterized by the following steps:

(164) 1) RCA cleaning.

(165) 2) Thermal oxidation 1000 Å.

(166) 3) Implantation No. 1: boron on the rear face through the 1000-Å thermal oxide layer.

(167) 4) Protection of the rear face with resin.

(168) 5) Lithographic etching of the active zone and of the calibration figure of the front face (mask 1).

(169) 6) Total removal of SiO.sub.2.

(170) 7) Removal of the protective resin on the front face.

(171) 8) Deposition of the P.sub.2O.sub.5 oxide by diffusion source and use of a passivation layer.

(172) 9) P diffusion.

(173) 10) Thinning of the P oxide on the front face.

(174) 11) Annealing of the diffused P.

(175) 12) Implantation mask, deposition of a layer of polysilicon having a thickness of 0.2 micrometers.

(176) 13) Photolithographic etching of the polysilicon: several spacings between fingers 100, 200, 500 micrometers. They all have the same width of 500 nanometers (mask 6).

(177) 14) Amorphizing implantation with phosphorus on the front face in a channel at 0 degree angle with 180 keV and 7.10.sup.14 At/cm.sup.2.

(178) 15) Total removal of the polysilicon.

(179) 16) Annealing after implantation.

(180) 14. Production Process in Small Series of Giant Photoconversion Devices—Example of Thermal Oxidation

(181) The thermal oxidation of the GPC cell can be carried out in an oxidation oven, exploited in microelectronics, reaching 1000° C. under N.sub.2, O.sub.2, H.sub.2, HCl and forming an oxide layer having a thickness of 0.5 to 1.6 μm.

(182) 15. Production Process in Small Series of Giant Photoconversion Devices—Example of Ion Beam Current

(183) Implantation characteristics with focused beam require a beam current of from 3 microamperes to 2 milliamperes, the acceleration voltage ranging from 5 to 200 kV, up to 125 atomic mass, with the ability to process silicon wafer samples having diameters ranging from 1 cm.sup.2 to 6 inches.

(184) 16. Production Process in Small Series of Giant Photoconversion Devices—Example of Creation of a Front Surface Field

(185) The creation of an intrinsic electrostatic field on the front face of the silicon wafer to manufacture a GPC cell can be performed using shallow implantation of phosphorus ions (depth <1.0 μm). This second implantation of the GPC cell can be done with the same ion implanter operating in the lower energy range forming the shallow impurity profile.

(186) 17. Production Process in Small Series of Giant Photoconversion Devices—Example of a Thermal Treatment Based on Thermodynamic Effects of Crystallization

(187) The first annealing of the GPC cell at about 500° C. should generally be followed by the second annealing operation which is cyclical with heating and cooling steps. The cycle can be performed in the same oven as that used for the first annealing step.

(188) 18. Production Process in Small Series of Giant Photoconversion Devices—Example of Values to Start the Procedure by Iterative Adjustment of the GPC Cell Manufacturing Machine by a Specific Characterization Process

(189) TABLE-US-00001 Table of starting values Selected manufacturing machine Implemented functions Values of parameters High temperature oven Thermal oxidation Oxygen ion diffusion at a temperature <1000° C. (tolerance 3%) Oxide thickness 600 Å Ion implanter for wide Implantation of boron ions Dose 5 × 10.sup.14 per square defocused beam (rear face) centimeter (tolerance 3%) implantation Power 25 keV (tolerance 1%) Off-axis by a few degrees (tolerance 0.5 degrees) Ion implanter for wide Implantation of phosphorus Dose <10.sup.15 ions per defocused beam ions (front face) square centimeter implantation (tolerance 3%) Power 20 keV (tolerance 1%) Passivation of the SiO.sub.2 substrate, P.sub.2O.sub.5 thickness 5 nanometer Off-axis by a few degrees to avoid ion channeling for improved precision (tolerance 1 degree) Oxidation oven Front surface field Temperature 850° C. Formation of P profile by (tolerance 3%) diffusion Duration 2 hours (tolerance 1%) Microphotolithography Covers certain portions of Covering with a photoresist the sample to protect them agent to protect the from the implantation, untreated zones against the optionally creating different on-going procedure, for geometries and shapes of example, against the effects amorphized layers of the chemical wet micro- etching Ion implanter for wide Implantation of Power 180 keV (tolerance 10%) defocused beam phosphorus, boron or Phosphorus ion density amorphization silicon ions 10.sup.4 by square centimeter (tolerance 10%) Annealing with a cycling Annealing Duration 30 minutes oven (tolerance 10%) Temperature ≤500° C. (tolerance 10%) Rapid exposition to heat with cooling in 1/10 second (tolerance 5%) Reactive ion etching RIE-treated zones selected a thin 5-nanometer layer machine for removal of SiO.sub.2 is preserved 80 nanometers are removed (tolerance 1%), HF solution that processes 80-nanometer per minute (tolerance 1%) 15 nanometers are removed by a mixture of water and buffer (1 milliliter) LPCVD oven Deposition of a 100-nm Thickness 10 nm (tolerance 3%) protective layer Cathode sputtering machine Deposition of 100 nm of Ambient temperature, SiO.sub.2 operating as pressure 2 .Math. 10.sup.−3 torr protective layer (tolerance 3%) Power 200 W (tolerance 10%), distance to the target 100 nanometer (tolerance 3%) Duration 10 minutes (tolerance 3%)

(190) The initial values for the equipment selected for manufacturing were obtained with the CAD software CAM, which provides adjustment data at the beginning of the iterative process for the micro-manufacturing machine with a margin of error reduced by specificities of the metamaterial manufacturing and by adequate machinery.

(191) 19. Production Process in Small Series of Giant Photoconversion Devices—Examples of Nanoscopic Transformations of Crystalline Silicon into an Optimal Arrangement to Form Buried Active Subsystems

(192) The manufacturing process according to this invention constitutes a nanoscopic transformation of crystalline silicon into an optimal arrangement to form subsystems buried in the crystal lattice that make it possible to improve the efficiency of light-to-electricity conversion. All parameters, procedures and manufacturing steps of the GPC have been tested and validated separately and in combination during the manufacture of many test series.

(193) To be useful in terms of light-to-electricity conversion, silicon must undergo a complex transformation that will shift from the structural defects being normally distributed in a rare, random and scattered manner to a structure composed of elementary units called SEGTONS of the ordered super-lattice, thus forming a metamaterial called SEG-MATTER. The most important aspects concern the nature, density and number of point defects properly positioned within the converter space.

(194) To perform its functions, the nanolayer of metamaterial is integrated into a material (preferably crystalline silicon, c-Si), properly doped by n-type doping. This layer is bounded by two planar interfaces (nanomembranes) delimiting it according to an earlier invention.

(195) The thickness of the metamaterial nanolayer (<c-Si>nanolayer) and the density of the grafted SEGTONs are self-controlled during manufacturing by the local mechanical stress (coming from dilatations between a-Si and c-Si), which are induced by, and result from, recrystallization cycles (solid phase epitaxy) occurring at suitable temperatures. Experiments (X-rays, LEED) show that on the side of the crystalline phase (well visible by available techniques), the final thickness of the nanolayer SEG-MATTER is in the order of 5 to 10 nanometers.

(196) Keeping in mind all the individual steps, they are integrated into a single and complete industrial-type manufacturing process. As a result, the main features related to the SEG-MATTER concern: a deep local transformation of the semiconductors (preferably c-Si), possible on a nanometric scale, which leads to a crystalline silicon metamaterial called SEG-MATTER, a high density (10.sup.20 cm.sup.−3) of the SEGTONs in the metamaterial, with a homogeneous distribution, uniform and stabilized composition of the SEG-MATTER nanolayers, sufficient quantities of all metamaterial nanolayers corresponding to the intensity of the incident photon flux, adapted spatial position of the SEG-MATTER system, which must be close to the place where there is the absorption of energetic photons (spatial optimization):

(197) *proximity and/or unity of the absorption zone and secondary generation zones;

(198) *maximum and optimized exposure surface (shapes and arrangements) for collision interactions with hot electrons.

(199) The metamaterial nanolayer is designed to withstand and remain after treatments carried out at unusually relatively high temperatures (450-550° C. and 250-450° C.) for the divacancies, because of the maintenance of the local mechanical stress. This characteristic differs from the fact, well-known to persons skilled in the art that the divacancies recombine at temperatures below 250° C.

(200) The most specific problems concern the concatenation of operations that follow each other consecutively, since some are mutually exclusive. For example, in the present invention, the temperatures of the successive procedures in the production cycle necessarily range stepwise from the highest toward the lowest, while respecting each of the steps described above.

(201) Light-to-electricity converters containing the substructures (continuous or discontinuous) in the emitter have been described previously. One of the most important elements of the dedicated subregion, sub-system and substructure is a component that is artificial on a nanometric scale and that should be able to complement the conventional conversion with an improvement due to the new mechanisms.

(202) This is ensured by an artificial material (SEG-MATTER), formed inter alia from well-defined building units, having a well-defined density and localized in a well-defined manner in the well-determined volume of the converter. To ensure the complete functionality of the conversion of the SEGTONs and of the SEG-MATTER, a number of strict conditions must be met.

(203) Generally, the solution requires specific sequences of known operations, which must be parameterized according to the physical and technological features of the process.

(204) The manufacture of a GPC device requires the integration of a series of operations that are, on the one hand, well known in the photovoltaic and microelectronic technologies (operations, procedures, machines), but on the other hand, cannot to be applied as they are, because of their specific conditions related to the large active surfaces of the devices.

(205) Manufacturing can be carried out using existing equipment with a few minor adaptations. Virtually all necessary machinery and tools have been tested and are normally available in the industry. The future large-scale manufacturing will be operational on dedicated, simpler, and significantly less expensive production machines.

(206) For example, the structure of a test device contains an electronic passivation SiO.sub.2 carried out by a low pressure vapor deposition method. The passivation layer has a thickness of 100 nanometers. The crystalline silicon doped with phosphorus has a thickness equal or lower than 170 nanometers, the layer strongly doped with amorphized silicon has a thickness of 20 nanometers, the PN junction is 1 micron below the surface (this value is not highly constraining). The amorphized layer is swollen, causing mechanical stress due to the discrepancy between the crystalline lattice and the amorphization.

(207) The rear face contact can be made of aluminum and the front face electrodes can be made of silver or metal tri-layer.

(208) The main originality of the invented manufacturing technology lies in the range of specific operations, as compared to the usual technology of crystalline Si cells, and in the organization of the manufacturing steps. The main constraints come from the fact that GPC sub-structures cannot be heated above 500° C.

(209) Once the metamaterial layer has been manufactured, to create the passivation layer without heating too much, one must use chemical vapor deposition, which can be carried out at low temperature (which is not the case for thermal oxidation). Thus, the best way to proceed is to use a compromise: firstly, perform a first thermal oxidation, then, thin the Sift layer by etching to 5 nanometers, create the nanostructured layer by wide defocused beam ion implantation, adjust the nanolayer system by annealing cycles, return to electronic passivation to increase its thickness by chemical deposition.

EXAMPLE

(210) *material: CZ or FZ silicon in the form of wafers with a <100> crystallographic orientation,

(211) *homogeneous density p-type pre-doping with boron of 1 to 5.10.sup.15 At per cubic centimeter,

(212) *the useful lifetime of the minority carriers must be as long as possible (it depends on quality),

(213) *diameter and thickness of the silicon wafer: 4, 6 or 12 inches, thickness 150-500 micrometers,

(214) *thickness of the initial sacrificial oxidation layer expanded at a temperature below 1000° C.,

(215) *first implantation at the rear face, with boron: 10.sup.15 At/cm.sup.2, leading to a profile having its maximum on the surface except on the alignment zone,

(216) *etching of the SiO.sub.2 from the front face with HF buffer, except on the alignment zone,

(217) *pre-deposition of a source of phosphorus diffusion on the front face,

(218) *diffusion according to a profile determined by the prior simulation performed with the software, for example, ATHENA,

(219) *second implantation of phosphorus on the front face, energy 180 keV, dose 8×10.sup.14 At/cm2, except on the alignment zone; “direct” amorphization.

(220) Thermal Treatment Cycle

(221) *Partial etching of SiO.sub.2 of the rear face, respecting the pattern of the contact fingers,

(222) *metallization of the rear face; deposition of a 1-nm Al layer,

(223) *etching of the rear face according to the alignment patterns (possibly with mask),

(224) *Slow etching of the SiO.sub.2 of the front face with HF:H.sub.2O,

(225) *Tri-layer metallization of the front face: Ti/Pd/Ag,

(226) *etching of the metal of the face according to the pattern of the contact zone.

(227) 20. Machines that can be Used as References to Implement the Production Process According to the Present Invention

(228) The following list is a non-exhaustive example. Machine for the reactive ion etching of the silicon wafer: inductively coupled plasma etching machines, for example the machine AVI21 TEC OMEGA 201 with RF inductive power of 600 W (13.56 MHz), RF clamping power of 600 W (13.56 MHZ), treatment temperature of from 10 to 20 degrees Celsius, and the possibility of using the following gases: SF.sub.6, CF.sub.4, O.sub.2, CHF.sub.3, AR, with cooling of the rear face of the GPC by helium; Standard production photolithography equipment (standard workshop mask as instruments), which is only necessary in the case of a GPC with discontinuous substructures. The alignment mask is an example of the necessary instruments; Ion implanter for the second treatment of the GPC cell; Second annealing step for the GPC cell: oven identical to that used for the first annealing step with rapid temperature variation controllable by computer; Cathode sputtering machine for the metallization of the rear contacts of the GPC cell, such as, for example, UNIVEX 450C, where the metal can be aluminum, the RF or DC power and the required vacuum limit being 1.10.sup.−7 torr; VARIAN 3 6 16 machine for the metallization of the front contacts of the GPC cell with titanium, palladium or silver using an electron gun for evaporation, with a power of 6 kW, a cryogenic pump, and a minimum pressure of 5.10.sup.−7 bar; Instrument for the creation of a 100-nanometer protective SiO.sub.2 layer for the passivation of the GPC cell by an LPCVD oven, such as LPCVD6, whose characteristics are: maximum temperature 580° C., length of the tray area 50 cm, gas: N.sub.2, NH.sub.3, SiH.sub.4, SiH.sub.2Cl.sub.2, N.sub.2O; Cathode sputtering machine for sputtering SiO.sub.2 or ITO on the GPC cell, such as the ALCATEL 600, with a cryogenic pump, an RF or DC power source, and a pressure of 10.sup.−7 ton; Machine for the final cleaning of the GPC cell for microelectronic circuits with class 100 atmospheric control, nitrogen dryers using ion-free water, a resistivity measurement function to measure the quality of the drying and cleaning between the different baths, the vapors being extracted from the bottom at the top of the device.

(229) The present invention is naturally not limited to the embodiments described and shown but covers all variants, alternatives or changes that can be made or their equivalents used without departing from the spirit and scope of the invention.