ELECTRICAL CONVERTER

Abstract

A converter for conversion between three-phase AC and a DC signal may include three phase terminals, a first and second DC terminal, conversion circuitry for conversion between three phase voltages of the three-phase AC signal and a first and second intermediate voltage at first and second intermediate nodes, and first and second buck circuits. The buck circuits each have three devices that are actively switchable for connecting switch-node terminals to any one of the three phase terminals. The first buck circuit includes a second switching device connected between the first intermediate node and the first switch-node terminal, and a first filter inductor connected between the first switch-node terminal and the first DC terminal. The second buck circuit has another second switching device connected between the second intermediate node and the second switch-node terminal, and a second filter inductor connected between the second switch-node terminal and the second DC terminal.

Claims

1. An electrical converter for conversion between a three-phase AC signal and a DC signal, the electrical converter comprising: three phase terminals (A, B, C), a first DC terminal (P) and a second DC terminal (N), a conversion circuitry for conversion between three phase voltages of the three-phase AC signal provided at the three phase terminals (A, B, C) and a first and second intermediate voltage at a first and second intermediate node (x, y) of the electrical converter, a first buck circuit comprising at least one first switch-node terminal that is operably connected to the first DC terminal (P) and a second buck circuit comprising at least one second switch-node terminal that is operably connected to the second DC terminal (N), wherein the first and the second buck circuits are connected between the first intermediate node (x) and the second intermediate node (y) for conversion between the first and second intermediate voltage and the three phase voltages, on one hand, and the DC signal between the first and second DC terminals (P, N), on the other hand, wherein the first buck circuit comprises three first devices that are actively switchable for connecting the at least one first switch-node terminal to any one of the three phase terminals (A, B, C), and in that the second buck circuit comprises three further first devices that are actively switchable for connecting the at least one second switch-node terminal to any one of the three phase terminals (A, B, C), wherein the first buck circuit comprises at least one second device that is switchable and connected between the first intermediate node (x) and the at least one first switch-node terminal, and at least one first filter inductor connected between the at least one first switch-node terminal and the first DC terminal (P) and wherein the second buck circuit comprises at least one further second device that is switchable and connected between the second intermediate node (y) and the at least one second switch-node terminal, and at least one second filter inductor connected between the at least one second switch-node terminal and the second DC terminal (N), wherein the first and the second buck circuits are connected in series between the first intermediate node (x) and the second intermediate node (y) such that there is a common node (m) of the first and second buck circuit; wherein the first buck circuit comprises at least one third device connected between the common node (m) and the at least one first switch-node terminal; wherein the second buck circuit comprises at least one further third device connected between the common node (m) and the at least one second switch-node terminal.

2. The electrical converter of claim 1, wherein the at least one second device and the at least one further second device are actively switchable.

3. (canceled)

4. The electrical converter of claim 1, wherein the at least one third device and the at least one further third device are actively switchable.

5. The electrical converter of claim 1, wherein the first buck circuit is configured to control connections between the at least one first switch-node terminal and the first intermediate node (x), the three phase terminals (A, B, C), and the common node (m); and wherein the second buck circuit is configured to control connections between the at least one second switch-node terminal and the second intermediate node (y), the three phase terminals (A, B, C), and the common node (m).

6. The electrical converter of claim 1, further comprising a controller configured to control at least one of the conversion circuitry and the first and second buck circuit.

7. The electrical converter of claim 1, further comprising at least two filter capacitors connected between the first and second DC terminals (P, N).

8. The electrical converter of claim 7, wherein the common node (m) is connected to a midpoint of a series connection of the at least two filter capacitors.

9. The electrical converter of claim 1, further comprising a filter comprising capacitors which interconnect the first intermediate node (x), the second intermediate node (y) and the three phase terminals (A, B, C).

10. The electrical converter of claim 9, wherein the capacitors are connected to the common node (m).

11. The electrical converter of claim 6, comprising measurement means configured to measure at least one of the DC signal, an electrical signal influencing the DC signal, an electrical signal influenced by the DC signal, and wherein the controller comprises a control loop configured to adapt at least one pulse width modulation control signal for controlling at least one of the first and second buck circuit based on measurements of the measurement means.

12. (canceled)

13. The electrical converter of claim 1, wherein the conversion circuitry comprises three phase legs configured to interconnect one of the three phase terminals (A, B, C) to any one of the first intermediate node (x) and the second intermediate node (y), wherein each of the three phase legs comprises a half bridge comprising semiconductor devices.

14. The electrical converter of claim 13, wherein the semiconductor devices of the three phase legs are actively switchable.

15. A battery charging system, comprising a power supply unit, the power supply unit comprising the electrical converter of claim 1.

16. An electric motor drive system, comprising a power supply unit, the power supply unit comprising the electrical converter of claim 1.

17. A gradient amplifier comprising the electrical converter of claim 1.

18. A method of converting between a three-phase AC signal and a DC signal, comprising: converting between a first, second and third phase voltage of the three-phase AC signal and a first and a second intermediate voltage, wherein the first intermediate voltage is applied on a first intermediate node (x) and the second intermediate voltage is applied on a second intermediate node (y), wherein a phase signal of the three-phase AC signal having a highest voltage is continuously applied to the first intermediate node (x) and a phase signal of the three-phase AC signal having a lowest voltage is continuously applied to the second intermediate node (y), and converting between the first and second intermediate voltages and the first, second and third phase voltages, on one hand, and the DC signal, on the other hand, using a first and a second buck circuit, comprising using at least one first filter inductor connected between at least one first switch-node terminal and a first DC terminal (P) and at least one second filter inductor connected between at least one second switch-node terminal and a second DC terminal (N), respectively, wherein the respective first and second intermediate voltage and the respective first, second and third phase voltage are intermittently connected to the at least one first switch-node terminal of the first buck circuit during respective time intervals and to the at least one second switch-node terminal of the second buck circuit during further respective time intervals.

19. The method of claim 18, wherein the first and second buck circuits are controlled such that the respective time intervals and the further respective time intervals are periodic time intervals, said respective time intervals and further respective time intervals covering together a period of the three-phase AC signal.

20. The method of claim 18, wherein the first and the second buck circuits are connected in series between the first intermediate node (x) and the second intermediate node (y) such that there is a common node (m) of the first and second buck circuit.

21. The method of the preceding claim 20, wherein during each respective time interval, the at least one first switch-node terminal of the first buck circuit is alternately connected to the first intermediate node, the respective first, second, and third phase voltage, and the common node (m), while the at least one second switch-node terminal of the second buck circuit is alternately connected to the second intermediate node and the common node; and wherein during each further respective time interval, the at least one second switch-node terminal of the second buck circuit is alternately connected to the second intermediate node, the respective first, second, and third phase voltage, and the common node (m), while the at least one first switch-node terminal of the first buck circuit is alternately connected to the first intermediate node and the common node.

22. The method of claim 18, wherein the converting between the intermediate signal and the DC signal using a first and a second buck circuit comprises controlling at least one of a duty cycle, a switching frequency, and a conduction sequence of control signals to control the first and second buck circuit.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0052] The accompanying drawings are used to illustrate presently preferred non-limiting exemplary embodiments of devices of the present disclosure. The above and other advantages of the features and objects of the disclosure will become more apparent and the present disclosure will be better understood from the following detailed description when read in conjunction with the accompanying drawings, in which:

[0053] FIG. 1 is a circuit diagram of an exemplary embodiment of an electrical converter;

[0054] FIGS. 2A-2L illustrate various charts plotting various voltages, currents and control signals in function of cot)(° for the exemplary embodiment of FIG. 1;

[0055] FIG. 3 illustrates various charts plotting various control signals, voltages, currents and control signals in function of time (microseconds), when ωt=40°, see reference numeral III in FIGS. 2A-2L;

[0056] FIG. 4 illustrates various charts plotting various control signals, voltages, currents and control signals in function of time (microseconds), when ωt=60°, see reference numeral IV in FIGS. 2A-2L;

[0057] FIG. 5 illustrates various charts plotting various control signals, voltages, currents and control signals in function of time (microseconds), when ωt=80°, see reference numeral V in FIGS. 2A-2L;

[0058] FIGS. 6 and 7 illustrate various charts plotting various currents in function of cot)(° for the exemplary embodiment of FIG. 1;

[0059] FIGS. 8-11 are circuit diagrams of other exemplary embodiments of an electrical converter;

[0060] FIG. 12 illustrates schematically an exemplary embodiment of a control unit;

[0061] FIG. 13 is a circuit diagram of another exemplary embodiment of an electrical converter wherein the first circuit and the second buck circuit are connected in parallel.

DETAILED DESCRIPTION

[0062] FIG. 1 shows an electrical converter 10, referred to as the ‘PRODRIVE-DIRECT RECTIFIER’, comprising two power stages 11, 12 in the form of a three-phase passive rectifier 11 and an active output power stage 12. Electrical converter 10 further comprises an input filter 13 placed between the passive rectifier 11 and the output power stage 12, and an output filter 14.

[0063] The electrical converter 10 is an AC-to-DC converter that has three phase terminals A, B, C which are connected to a three-phase voltage of a three-phase AC grid 20, and a first and second output DC terminal P, N, here an upper output terminal P and a lower output terminal N, which for example may be connected to a DC load 21 such as, for example, a high voltage (e.g. 200-400 V) battery of an electric car. The three-phase rectifier 11 comprises three phase connections a, b, c that are connected to the three phase terminals A, B, C, and two outputs x, y. These outputs x, y correspond with a first intermediate node x, here an upper intermediate voltage node x, and a second intermediate node y, here a lower intermediate voltage node y.

[0064] The three-phase passive rectifier 11 comprises, or consists of, three bridge legs 15, 16, 17 which each comprise two passive semiconductor devices (diodes D.sub.ax and D.sub.ya for leg 15, D.sub.bx and D.sub.yb for leg 16, D.sub.cx and D.sub.yc for leg 17) connected in the form of a half bridge configuration.

[0065] The output power stage 12 comprises, or consists of, two stacked (i.e. series connected) buck bridge legs 18, 19 of first and second stacked buck circuits. The first upper buck bridge leg 18 comprises three first semiconductor devices 1pa, 1pb, 1pc, a second semiconductor device 2p and a third semiconductor device 3p. The second lower buck bridge leg 19 comprises a three further first semiconductor devices 1na, 1nb, 1nc, a further second semiconductor device 2n and a further third semiconductor device 3n. The second and further second semiconductor device 2p, 2n is a buck switch (S.sub.xp for the upper buck bridge leg 18 and S.sub.ny for the lower buck bridge leg 19). The switches S.sub.xp and S.sub.ny of the buck bridge legs 18, 19 are actively switchable semiconductor devices, for example MOSFETs. The third and further third semiconductor device 3p, 3n is a buck diode (D.sub.mp for the upper buck bridge leg 18 and D.sub.nm for the lower buck bridge leg 19). The second and third semiconductor devices 2p, 3p and the further second and further third semiconductor devices 2n, 3n are connected in a half-bridge configuration. The switched middle node of the upper buck bridge leg 18 forms an upper switch-node terminal p which is connected to output P via a first buck inductor, here an upper buck inductor L.sub.p, and the switched middle node of the lower buck bridge leg 19 forms a lower switch-node terminal n which is connected to output N via a second buck inductor, here a lower buck inductor L.sub.n.

[0066] The common node m of both, stacked, buck bridge legs 18, 19 is connected to the midpoint of the output filter 14 which comprises two output filter capacitors C.sub.Pm, C.sub.mN that are connected in series between the upper output terminal P and the lower output terminal N.

[0067] The three first and further first semiconductor devices 1pa, 1pb, 1pc and 1na, 1nb, 1nc are interconnection switches S.sub.zapD.sub.zap, S.sub.zbpD.sub.zbp, S.sub.zcpD.sub.zcp for the first upper buck bridge leg 18 and S.sub.nzaD.sub.nza, S.sub.nzbD.sub.nzb, S.sub.nzcD.sub.nzc, for the second lower buck bridge leg 19, with bi-directional voltage blocking capability, which allow for connecting the switched middle node of the respective bridge, i.e., the upper switch-node terminal p for the upper buck bridge leg 18 and the lower switch-node terminal n for the lower buck bridge leg 19, with each of the three phase connections a, b, c. Each interconnection switch S.sub.zapD.sub.zap, S.sub.zbpD.sub.zbp, S.sub.zcpD.sub.zcp of the upper buck bridge leg 18 comprises an actively switchable semiconductor device S.sub.zap, S.sub.zbp, S.sub.zcp connected in anti-series with a diode D.sub.zap, D.sub.zbp, D.sub.zbp, creating a voltage bi-directional interconnection switch. Each interconnection switch S.sub.nzaD.sub.nza, S.sub.nzbD.sub.nzb, S.sub.nzcD.sub.nzc, of the lower buck bridge leg 19 comprises an actively switchable semiconductor device S.sub.nza, S.sub.nzb, S.sub.nzc connected in anti-series with a diode D.sub.nza, D.sub.nzb, D.sub.nzc, creating a voltage bi-directional, interconnection switch. Each switchable semiconductor device is advantageously complemented by an anti-parallel diode. In this example, Metal Oxide Field Effect Transistors (MOSFETs) are used for the actively switchable semiconductor devices, each including an internal anti-parallel body diode that may replace an external anti-parallel diode.

[0068] The upper buck bridge leg 18 is connected between the upper intermediate voltage node x and the common node m, and is arranged in a way that current can flow from the upper intermediate voltage node x to the upper output terminal P via the switch S.sub.xp when the switch S.sub.xp is closed (conducting, on state), current can flow from a phase connection a, b, c to the upper output terminal P via the corresponding interconnection switch S.sub.zapD.sub.zap, S.sub.zbpD.sub.zbp, S.sub.zcpD.sub.zcp when the corresponding switch S.sub.zap, S.sub.zbp, S.sub.zcp is closed (conducting, on state) and the two remaining (non-corresponding) switches S.sub.zap, S.sub.zbp, S.sub.zcp are open (non-conducting, off state) and the switch S.sub.xp is open (not conducting, off state), and current can flow from the common node m to the upper output terminal P via the diode D.sub.mp when the switches S.sub.xp and S.sub.zap, S.sub.zbp, S.sub.zcp are open (not conducting, off state). The switches S.sub.xp and S.sub.zap, S.sub.zbp, S.sub.zcp of the buck bridge leg 18 are actively switchable semiconductor devices, for example MOSFETs.

[0069] The lower buck bridge leg 19 is connected between the common node m and the lower intermediate voltage node y, and is arranged in a way that current can flow from the lower output terminal N to the lower intermediate voltage node y via the switch S.sub.ny, when the switch S.sub.ny is closed (conducting, on state), current can flow from the lower output terminal N to a phase connection a, b, c via the corresponding interconnection switch S.sub.nzaD.sub.nza, S.sub.nzbD.sub.nzb, S.sub.nzcD.sub.nzc when the corresponding switch S.sub.nza, S.sub.nzb, S.sub.nzc is closed (conducting, on state) and the two remaining (non-corresponding) switches S.sub.nza, S.sub.nzb, S.sub.nzc are open (not conducting, off state) and the switch S.sub.ny is open (not conducting, off state), and current can flow from the lower output terminal N to the common node m via the diode D.sub.nm when the switches S.sub.ny and S.sub.nza, S.sub.nzb, S.sub.nzc are open (not conducting, off state). The switches S.sub.ny and S.sub.nza, S.sub.nzb, S.sub.nzc of the buck bridge leg 19 are actively switchable semiconductor devices, for example MOSFETs.

[0070] Advantageously, five high-frequency (HF) filter capacitors C.sub.x, C.sub.y, C.sub.za, C.sub.zb, C.sub.zc, which are part of the input filter 13, are interconnecting the intermediate voltage nodes x and y and the three phase connections a, b, and c in the form of a “star”-connection. Advantageously, the star point of the five high-frequency (HF) filter capacitors C.sub.x, C.sub.y, C.sub.za, C.sub.zb, C.sub.zc is connected to the common node m of both buck bridge legs 18, 19, and to the midpoint of the output filter 14.

[0071] The bridge leg of the passive rectifier 11 that is connected with the phase terminal A, B, or C that has the highest voltage of the three-phase AC input voltage is switched in a way that the corresponding phase terminal A, B, or C is connected to the upper intermediate voltage node x. To achieve this, the bridge leg connects the corresponding phase connection a, b, or c with the upper intermediate voltage node x via the upper diode (D.sub.ax, D.sub.bx, D.sub.cx) of the bridge leg. The bridge leg of the passive rectifier 11 that is connected with the phase terminal A, B, or C that has the lowest voltage of the three-phase AC input voltage is switched in a way that the corresponding phase terminal A, B, or C is connected to the lower intermediate voltage node y. To achieve this, the bridge leg connects the corresponding phase connection a, b, or c with the lower intermediate voltage node y via the lower diode (D.sub.ya, D.sub.yb, D.sub.yc) of the bridge leg.

[0072] In a three-phase AC grid with substantially balanced phase voltages v.sub.a, v.sub.b, v.sub.c, for example as shown in FIG. 2A, the three-phase AC input voltage (mains voltage) is converted into an intermediate DC voltage v.sub.xy which is shown in FIG. 2B and which is provided between the upper intermediate voltage node x and the lower intermediate voltage node y. This DC voltage is thus a line-rectified voltage showing piece-wise sinusoidal shapes. The conversion of the three-phase AC input voltage into an intermediate DC voltage is the result of the operation of the passive rectifier 11, as explained above. The diodes of the passive rectifier 11 are ‘conducting’ or ‘not conducting’ during whole particular sectors within the period (360°) of the AC mains voltage (360° corresponds with a time period of 20 ms for a 50 Hz grid frequency; also called a line cycle). Referring to FIG. 2A: [0073] diode D.sub.ax conducts within 30°≤ωt<150°, [0074] diode D.sub.bx conducts within 150°≤ωt<270°, [0075] diode D.sub.cx conducts within 270°≤ωt<360° and 0°≤ωt<30°, [0076] diode D.sub.ya conducts within 210°≤ωt<330°, [0077] diode D.sub.yb conducts within 330°≤ωt<360° and 0°≤ωt<90°, [0078] diode D.sub.yc conducts within 90°≤ωt<210°,

[0079] The combination of states (conducting/not conducting) of the diodes is unique for every 60° sector of the three-phase AC input voltage and depends on the voltage value of the phase terminals A, B, C. The sequence of the 6 unique states of the switches and diodes repeats itself every period (360°) of the AC mains voltage.

[0080] Seen from the viewpoint of the intermediate voltage nodes x and y towards the output terminals P, N, a DC-DC buck circuit (upper buck circuit) can be identified, having five input ports x, a, b, c, m and two output ports P, m, and comprising the HF filter capacitors C.sub.x, C.sub.za, C.sub.zb, C.sub.zc, the upper buck bridge leg 18, the upper buck inductor L.sub.p, and the upper output capacitor C.sub.Pm. The voltage between input ports x and m of this upper buck circuit is the voltage v.sub.Cx=v.sub.x−v.sub.m (v.sub.x and v.sub.m are shown in FIG. 2E) across capacitor C.sub.x, the voltage between each of the input ports a, b, c and input port m of this upper buck circuit are the voltages (in vector notation) [v.sub.Cza, v.sub.Czb, v.sub.Czc]=[v.sub.a, v.sub.b, v.sub.c]-[v.sub.m, v.sub.m, v.sub.m] (v.sub.a, v.sub.b, v.sub.c are shown in FIG. 2A and v.sub.m is shown in FIG. 2E) across capacitors C.sub.za, C.sub.zb, C.sub.zc, and the voltage between output ports P and m of this upper buck circuit is the voltage V.sub.Pm=v.sub.p−v.sub.m (v.sub.p and v.sub.m are shown in FIG. 2E) across the upper output capacitor C.sub.Pm. V.sub.Pm has a voltage value that is substantially equal to half the total DC bus voltage (V.sub.Pm≈V.sub.DC/2).

[0081] Seen from the viewpoint of the intermediate voltage nodes x and y towards the output terminals P, N, an ‘inversed’ (negative input voltage and negative output voltage) DC-DC buck circuit (lower buck circuit) can be identified, having five input ports y, a, b, c, m and two output ports N, m, and comprising the HF filter capacitors C.sub.y, C.sub.za, C.sub.zb, C.sub.zc, the lower buck bridge leg 19, the lower buck inductor L.sub.i and the lower output capacitor C.sub.mN. The voltage between input ports y and m of this lower buck circuit is the voltage v.sub.Cy=v.sub.y−v.sub.m (v.sub.y and v.sub.m are shown in FIG. 2E) across capacitor C.sub.y, the voltage between each of the input ports a, b, c and node m of this lower buck circuit are the voltages (in vector notation) [v.sub.Cza, v.sub.Czb, v.sub.Czc]=[v.sub.a, v.sub.b, v.sub.c]−[v.sub.m, v.sub.m, v.sub.m] (v.sub.a, v.sub.b, v.sub.c are shown in FIG. 2A and v.sub.m is shown in FIG. 2E) across capacitors C.sub.za, C.sub.zb, C.sub.zc, and the voltage between output ports N and m of this lower buck circuit is the voltage V.sub.Nm=v.sub.N−v.sub.m (v.sub.N and v.sub.m are shown in FIG. 2E) across the lower output capacitor C.sub.mN. V.sub.Nm has a voltage value that is substantially equal to minus half the total DC bus voltage (V.sub.Nm≈−V.sub.DC/2).

[0082] By PWM modulation (pulse-width-modulation) of the control signals of switches S.sub.xp, and S.sub.zap, S.sub.zbp, S.sub.zcp of the upper buck circuit at a specified, possibly variable, switching frequency f.sub.s, the upper switch-node terminal p of the upper buck bridge leg 18 can be alternately connected to the upper intermediate voltage node x, to one or more of the three phase connections (in practice one out of the three at a time as otherwise the phases are short-circuited) a, b, c, or to the common node m. This results in a switched voltage v.sub.pm between nodes p and m, the switched voltage v.sub.pm which may thus have multiple voltage levels. The duty cycles (i.e. the relative on-time within a switching period T.sub.s=1/f.sub.s) of the PWM-modulated control signals of the switches S.sub.xp and S.sub.zap, S.sub.zbp, S.sub.zcp define the average value (v.sub.pm) of voltage v.sub.pm within a switching period. Control of these duty cycles, and thus also control of the switching-cycle-averaged value v.sub.pm, allows to control the switching-cycle-averaged value i.sub.Lp of the current i.sub.Lp in the upper buck inductor L.sub.p, e.g. using a closed-loop PI (Proportional-Integrating) control structure. Additionally, control of these duty cycles allows to control the switching-cycle-averaged values i.sub.x and/or i.sub.zap, i.sub.zbp, i.sub.zcp of input currents i.sub.x and i.sub.zap, i.sub.zbp, i.sub.zcp, of the upper buck bridge leg 18 by directing the inductor current i.sub.Lp to flow through S.sub.xp (=i.sub.x) for a certain amount of time (i.e. during the on-interval of S.sub.xp), and/or through S.sub.zapD.sub.zap (=i.sub.zap) for a certain amount of time (i.e. during the on-interval of S.sub.zap), and/or through S.sub.zbpD.sub.zbp (=i.sub.zbp) for a certain amount of time (i.e. during the on-interval of S.sub.zbp), and/or through S.sub.zcpD.sub.zcp (=i.sub.zcp) for a certain amount of time (i.e. during the on-interval of S.sub.zcp).

[0083] By PWM modulation (pulse-width-modulation) of the control signals of switches S.sub.ny and S.sub.nza, S.sub.nzb, S.sub.nzc of the lower buck circuit at a specified, possibly variable, switching frequency f.sub.s, the lower switch-node terminal node n of the lower buck bridge leg 19 can be alternately connected to the lower intermediate voltage node y, to one or more of the three-phase input voltage nodes (in practice one out of the three at a time as otherwise the phases are short-circuited) a, b, c, or to the common node m. This results in a switched voltage v.sub.nm, between nodes m and n, the switched voltage v.sub.nm which may thus have multiple voltage levels. The duty cycles (i.e. the relative on-time within a switching period T.sub.s=1/f.sub.s) of the PWM-modulated control signals of the switches S.sub.ny and S.sub.nza, S.sub.nzb, S.sub.nzc define the average value (v.sub.nm) of voltage v.sub.nm, within a switching period. Control of these duty cycles, and thus also control of the switching-cycle-averaged value v.sub.nm, allows to control the switching-cycle-averaged value i.sub.Ln of the current i.sub.Ln in the lower buck inductor L.sub.N, e.g. using a closed-loop PI (Proportional-Integrating) control structure. Additionally, control of these duty cycles allows to control the switching-cycle-averaged values i.sub.y and/or i.sub.zan, i.sub.zbn, i.sub.zcn of input currents i.sub.y and i.sub.zan, i.sub.zbn, i.sub.zcn of the lower buck bridge leg 19 by directing the inductor current i.sub.Ln to flow through S.sub.ny (=i.sub.y) for a certain amount of time (i.e. during the on-interval of S.sub.ny), and/or through D.sub.nzaS.sub.nza (=i.sub.zan) for a certain amount of time (i.e. during the on-interval of S.sub.nza), and/or through D.sub.nzbS.sub.nzb (=i.sub.zbn) for a certain amount of time (i.e. during the on-interval of S.sub.nzb), and/or through D.sub.nzcS.sub.nzc (=i.sub.zcn) for a certain amount of time (i.e. during the on-interval of S.sub.nzc).

[0084] The current i.sub.za is equal to the sum of the current i.sub.zap of the upper buck circuit and the current i.sub.zan of the lower buck circuit (i.sub.za=i.sub.zap+i.sub.zan), which is also true for the switching-cycle-averaged values of these currents (i.sub.za=i.sub.zap i.sub.zan). The current i.sub.zb is equal to the sum of the current i.sub.zbp of the upper buck circuit and the current i.sub.zbn of the lower buck circuit (i.sub.zb=i.sub.zbp+i.sub.zbn), which is also true for the switching-cycle-averaged values of these currents (i.sub.zb=i.sub.zbp+i.sub.zbn). The current i.sub.zc is equal to the sum of the current i.sub.zcp of the upper buck circuit and the current i.sub.zcn of the lower buck circuit (i.sub.zc=i.sub.zcp+i.sub.zcn), which is also true for the switching-cycle-averaged values of these currents (i.sub.zc=i.sub.zcp+i.sub.zcn).

[0085] The internal current i.sub.zp of the upper buck circuit is equal to the sum of the internal currents i.sub.zap, i.sub.zbp, i.sub.zcp of the upper buck circuit (i.sub.zn=i.sub.zan+i.sub.zbn+i.sub.zcn), which is also true for the switching-cycle-averaged values of these currents (i.sub.zp=i.sub.zap+i.sub.zbp+i.sub.zcp). The internal current i.sub.zn of the lower buck circuit is equal to the sum of the internal currents i.sub.zan, i.sub.zbn, i.sub.zcn of the lower buck circuit (i.sub.zn=i.sub.zan+i.sub.zbn+i.sub.zcn), which is also true for the switching-cycle-averaged values of these currents (i.sub.zn=i.sub.zan+i.sub.zbn+i.sub.zcn).

[0086] Generally, it can be said that the HF components of currents i.sub.x, i.sub.y, i.sub.za, i.sub.zb, i.sub.zc at the input of the output power stage 12 are largely filtered by HF filter capacitors C.sub.x, C.sub.y, C.sub.za, C.sub.zb, C.sub.zc. As a result, the currents i′.sub.x, i′.sub.y, i′.sub.za, i′.sub.zb, i′.sub.zc at the output of the three-phase rectifier 11 are largely equal to the switching-cycle-averaged values i.sub.x, i.sub.y, i.sub.za, i.sub.zb, i.sub.zc of currents i.sub.x, i.sub.y, i.sub.za, i.sub.zb, i.sub.zc, i.e., i′.sub.x≈i.sub.x, i′.sub.y≈i.sub.y, i′.sub.za≈i.sub.za, i′.sub.zb≈i.sub.zb, i′.sub.zc≈i.sub.zc.

[0087] The duty cycles of the PWM control signals of the switches S.sub.xp and S.sub.zap, S.sub.zbp, S.sub.zcp are such that the switching-cycle-averaged value v.sub.pm is substantially equal to half the total DC bus voltage (v.sub.pm=V.sub.Pm≈V.sub.DC/2; see FIG. 2E), while the duty cycles of the PWM control signals of the switches S.sub.ny and S.sub.nza, S.sub.nzb, S.sub.nzc, are such that the switching-cycle-averaged value v.sub.nm is substantially equal to minus half the total DC bus voltage (v.sub.nm=V.sub.Nm≈−V.sub.DC/2; see FIG. 2E). This means that the switching-cycle-averaged voltages (i.e. the volt-seconds products) of both the upper buck inductor L.sub.p and the lower buck inductor L.sub.n are substantially equal to zero.

[0088] An example of the switching-cycle-averaged values i.sub.Lp, i.sub.Ln of currents i.sub.Lp, i.sub.Ln in the inductors L.sub.p, L.sub.n is shown in FIG. 2C. As can be seen, current i.sub.Lp may be controlled to have a switching-cycle-averaged value equal to a requested DC output current (i.sub.Lp=I.sub.DC) while current i.sub.Ln may be controlled to have a switching-cycle-averaged value equal to minus the requested DC output current (i.sub.Ln=−I.sub.DC).

[0089] Also shown in FIG. 2C is an example of the switching-cycle-averaged values i.sub.x, i.sub.y, i.sub.za, i.sub.zb, i.sub.zc of currents i.sub.x, i.sub.y, i.sub.za, i.sub.zb, i.sub.zc As can be seen, these currents may be controlled to have piece-wise sinusoidal shapes. Current i′.sub.x=i.sub.x at the output of the passive rectifier 11 is controlled to be in phase with the phase voltage (v.sub.a, or v.sub.b, or v.sub.c) that has the highest value of the three-phase AC input voltage (v.sub.a, v.sub.b, v.sub.c) and thus has the same piece-wise sinusoidal shape as the highest phase voltage of the three-phase AC input voltage present at phase terminals A, B and C. Current i′.sub.y=i.sub.y at the output of the passive rectifier 11 is controlled to be in phase with the phase voltage (v.sub.a, or v.sub.b, or v.sub.c) that has the lowest value of the three phase AC input voltages (v.sub.a, v.sub.b, v.sub.c) and thus has the same piece-wise sinusoidal shape as the lowest phase voltage of the three-phase AC input voltage present at phase terminals A, B and C. Currents i′.sub.za=i.sub.za, i′.sub.zb=i.sub.zb, i′.sub.zc=i.sub.zc at the output of the passive rectifier 11 are controlled to be in phase with the corresponding phase voltage (respectively v.sub.a, v.sub.b, v.sub.c) when the corresponding phase voltage (respectively v.sub.a, v.sub.b, v.sub.c) has a voltage value between the highest voltage and the lowest voltage of the three-phase AC input voltage (v.sub.a, v.sub.b, v.sub.c) and are controlled to be zero when the corresponding phase voltage (respectively v.sub.a, v.sub.b, v.sub.c) has the highest or lowest voltage value of the three phase AC input voltage (v.sub.a, v.sub.b, v.sub.c). Currents i′.sub.za=i.sub.za, i′.sub.zb=i.sub.zb, i′.sub.zc=i.sub.zc thus have the same piece-wise sinusoidal shape as the voltage of their corresponding phase voltage (respectively v.sub.a, v.sub.b, v.sub.c) when that phase voltage is between the highest voltage and the lowest voltage of the three-phase AC input voltage (v.sub.a, v.sub.b, v.sub.c). The currents i′.sub.x, i′.sub.y, i′.sub.za, i′.sub.zb, i′.sub.zc are transformed, i.e., as a result of the operation of the passive rectifier 11, into three sinusoidal AC phase currents i.sub.a, i.sub.b, i.sub.c which are shown in FIG. 2D, realizing Power Factor Correction (PFC) operation of the electrical converter 10.

[0090] FIG. 2I shows examples of the duty cycles (with duty cycle Dut: 0≤Dut≤1, where Dut=0 means continuously ‘off’ within a switching period T.sub.s and Dut=1 means continuously ‘on’ within a switching period T.sub.s) of the switches and diodes (S.sub.xp, S.sub.zap, S.sub.zbp, S.sub.zcp, D.sub.mp) of the upper buck bridge leg 18 and FIG. 2J shows the duty cycles of the switches and diodes (S.sub.ny, S.sub.nza, S.sub.nzb, S.sub.nzc, D.sub.nm) of the lower buck bridge leg 19. These duty cycles correspond with the examples of FIGS. 2A-2H.

[0091] As can be seen from FIG. 2J, the duty cycle of the control signal of switch S.sub.nza equals zero during certain intervals within the line cycle of the mains voltage, i.e., in these intervals the switch S.sub.nza is continuously open (not conducting). Conform FIG. 2A this is the case for the intervals where v.sub.a>[v.sub.b, v.sub.c] or v.sub.a<[v.sub.b, v.sub.c] or v.sub.a>[0]. This means that the current i.sub.zan (and its switching-cycle-averaged value (i.sub.zan)) is zero during these intervals, resulting in i′.sub.za=i.sub.za=i.sub.zap during these intervals, as can also be seen from FIGS. 2C, 2F. Similarly, and as can be seen from FIG. 2I, the duty cycle of the control signal of switch S.sub.zap equals zero during certain intervals within the line cycle of the mains voltage, i.e., in these intervals the switch S.sub.zap is continuously open (not conducting). Conform FIG. 2A this is the case for the intervals where v.sub.a>[v.sub.b, v.sub.c] or v.sub.a<[v.sub.b, v.sub.c] or v.sub.a<[0]. This means that the current i.sub.zap (and its switching-cycle-averaged value (i.sub.zap)) is zero during these intervals, resulting in i′.sub.za=i.sub.za=i.sub.zan during these intervals, as can also be seen from FIGS. 2C, 2F. Following the same reasoning for switches S.sub.nzb, S.sub.zbp and for switches S.sub.ncz, S.sub.zcp, and conform FIGS. 2A, 2I, 2J, the intervals within the line cycle of the mains voltage where the respective interconnection switches are continuously open (not conducting; duty cycle equal to zero) are: [0092] Dut.sub.Szap=0 for v.sub.a>[v.sub.b, v.sub.c] or v.sub.a<[v.sub.b, v.sub.c] or v.sub.a<[0], [0093] Dut.sub.Snza=0 for v.sub.a>[v.sub.b, v.sub.c] or v.sub.a<[v.sub.b, v.sub.c] or v.sub.a>[0], [0094] Dut.sub.Szbp=0 for v.sub.b>[v.sub.a, v.sub.c] or v.sub.b<[v.sub.a, v.sub.c] or v.sub.b<[0], [0095] Dut.sub.Spzb=0 for v.sub.b>[v.sub.a, v.sub.c] or v.sub.b<[v.sub.a, v.sub.c] or v.sub.b>[0], [0096] Dut.sub.Szcp=0 for v.sub.c>[v.sub.a, v.sub.b] or v.sub.c<[v.sub.a, v.sub.b] or v.sub.c<[0], [0097] Dut.sub.Snzc=0 for v.sub.c>[v.sub.a, v.sub.b] or v.sub.c<[v.sub.a, v.sub.b] or v.sub.c>[0].

[0098] FIG. 2K shows the states of the switches S.sub.xp, S.sub.zap, S.sub.zbp, S.sub.zcp of the upper buck bridge leg 18, and FIG. 2L shows the states of the switches S.sub.ny, S.sub.nza, S.sub.nzb, S.sub.nzc of the lower buck bridge leg 19, within a line cycle of the mains voltage. The switches S.sub.xp, S.sub.zap, S.sub.zbp, S.sub.zcp, S.sub.ny, S.sub.nza, S.sub.nzb, S.sub.nzc are all PWM modulated at a frequency (i.e. the switching frequency f.sub.s; e.g. 100 kHz) that is substantially higher than the mains frequency (e.g. 50 Hz), as can be seen from the black-colored bars, indicating PWM modulation of the corresponding switch. Conform FIGS. 2I, 2J, switches S.sub.zap, S.sub.zbp, S.sub.zcp, S.sub.nza, S.sub.nzb, S.sub.nzc are continuously open (not conducting) during certain intervals of the line cycle as described above.

[0099] The control signals shown in FIGS. 2K and 2L allow to intermittently connect the first, second and third phase voltage v.sub.a, v.sub.b, v.sub.c to the first switch-node terminal p of the first buck circuit during time intervals T1ra, T1fa, T1rb, T1fb, T1rc, T1fc, and to the second switch-node terminal n of the second buck circuit during further time intervals T2ra, T2fa, T2rb, T2fb, T2rc, T2fc. The time intervals T1ra, T1fa, T1rb, T1fb, T1rc, T1fc and the further time intervals T2ra, T2fa, T2rb, T2fb, T2rc, T2fc may be arranged in any order and may be adjacent, partially overlapping, or fully overlapping.

[0100] As illustrated the respective time intervals may comprise: [0101] a first time interval T1ra during which the first phase voltage v.sub.a is intermittently connected to the first switch-node terminal p through a first one S.sub.zap of the three first switches, whilst an average current i.sub.zap through said first one S.sub.zap of the three first switches rises (which corresponds with the phase current i.sub.a which is rising), [0102] a second time interval T1fc during which the third phase voltage v.sub.c is intermittently connected to the first switch-node terminal p through a third one S.sub.zcp of the three first switches, whilst an average current i.sub.zcp through said third one S.sub.zcp of the three first switches falls (which corresponds with the phase current i.sub.c which is falling). [0103] a third time interval T1rb during which the second phase voltage v.sub.b is intermittently connected to the first switch-node terminal p through a second one S.sub.zbp of the three first switches, whilst an average current i.sub.zbp through said second one S.sub.zbp of the three first switches rises (which corresponds with the phase current i.sub.b which is rising), [0104] a fourth time interval T1fa during which the first phase voltage v.sub.a is intermittently connected to the first switch-node terminal p through said first one S.sub.zap of the three first switches, whilst an average current i.sub.zap through said first one S.sub.zap of the three first switches falls (which corresponds with the phase current i.sub.b which is falling), [0105] a fifth time interval T1rc during which the third phase voltage v.sub.c is intermittently connected to the first switch-node terminal p through said third one S.sub.zcp of the three first switches, whilst an average current i.sub.zcp through said third one S.sub.zcp of the three first switches rises (which corresponds with the phase current i.sub.c which is rising), and [0106] a sixth time interval T1fb during which the second phase voltage v.sub.b is intermittently connected to the first switch-node terminal p through said second one S.sub.zbp of the three first switches, whilst an average current i.sub.zbp through said second one S.sub.zbp of the three first switches falls (which corresponds with the phase current i.sub.b which is falling).

[0107] Similarly, the further respective time intervals may comprise: [0108] a further first time interval T2fc during which the third phase voltage v.sub.c is intermittently connected to the second switch-node terminal n through a third one S.sub.nzc of the three further first switches, whilst an average current i.sub.zcn through said third one S.sub.nzc of the three further first switches falls (which corresponds with the phase current i.sub.c which is falling), [0109] a further second time interval T2rb during which the second phase voltage v.sub.b is intermittently connected to the second switch-node terminal n through a second one S.sub.nzb of the three further first switches, whilst an average current i.sub.zbn through said second one S.sub.nzb of the three further first switches rises (which corresponds with the phase current i.sub.b which is rising), [0110] a further third time interval T2fa during which the first phase voltage v.sub.a is intermittently connected to the second switch-node terminal n through a first one S.sub.nza of the three further first switches, whilst an average current i.sub.zan through said first one S.sub.nza of the three further first switches falls (which corresponds with the phase current i.sub.a which is falling), [0111] a further fourth time T2rc interval during which the third phase voltage v.sub.c is intermittently connected to the second switch-node terminal n through said third one S.sub.nzc of the three further first switches, whilst an average current i.sub.zcn through said third one S.sub.nzc of the three further first switches rises (which corresponds with the phase current i.sub.c which is rising), [0112] a further fifth time interval T2fb during which the second phase voltage v.sub.b is intermittently connected to the second switch-node terminal n through said second one S.sub.nzb of the three further first switches, whilst an average current i.sub.zbn through said second one S.sub.nzb of the three further first switches falls (which corresponds with the phase current i.sub.b which is falling), [0113] a further sixth time interval T2ra during which the first phase voltage v.sub.a is intermittently connected to the at second switch-node terminal n through said first one S.sub.nza of the three further first switches, whilst an average current i.sub.zan through said first one S.sub.nza of the three further first switches rises (which corresponds with the phase current i.sub.s which is rising).

[0114] The first, second, third, fourth, fifth, and sixth time intervals T1ra, T1fc, T1rb, T1fa, T1rc, T1fb and the further first, second, third, fourth, fifth, and sixth time intervals T2fc, T2rb, T2fa, T2rc, T2fb, T2ra may be consecutive time intervals, arranged in any order and may be adjacent, partially overlapping or fully overlapping. For example, the order may be as illustrated: the first time interval T1ra, the second time interval T1fc, the further first time interval T2fc, the further second time interval T2rb, the third time interval T1rb, the fourth time interval T1fa, the further third time interval T2fa, the further fourth time interval T2rc, the fifth time interval T1rc, the sixth time interval T1fb, the further fifth time interval T2fb, the further sixth time interval T2ra. Together, the first, second, third, fourth, fifth, and sixth time intervals T1ra, T1fc, T1rb, T1fa, T1rc, T1fb and the further first, second, third, fourth, fifth, and sixth time intervals T2fc, T2rb, T2fa, T2rc, T2fb, T2ra cover a period of the three-phase AC signal.

[0115] FIGS. 3 and 5, see the detailed discussion below, show that during a respective time interval (in the example of FIG. 3 during T11fc and during T1rc), the upper switch-node terminal p of the first buck circuit may be alternately connected to the upper intermediate node x, the respective phase connection c, and the common node m; and that during a further respective time interval (in the example of FIG. 5 during T2fc and during T2rc), the lower switch-node terminal n of the second buck circuit may be alternately connected to the lower intermediate node y, the respective phase voltage c, and the common node m. In other non-illustrated embodiments where the time intervals fully overlap, one of the first switches S.sub.zap, S.sub.zbp, S.sub.zcp may be switched synchronously with the second switch S.sub.xp. Similarly, one of the further first switches S.sub.nza, S.sub.nzb, S.sub.nzc may be switched synchronously with the second switch S.sub.ny.

[0116] FIGS. 3-5 show diagrams of currents, voltages, and switching signals on a milliseconds time axis, i.e. regarding three consecutive switching cycles of the bridge legs of the output power stage 12 of the electrical converter 10. Each switching cycle has a switching period T.sub.s equal to 1/f.sub.s, with f.sub.s the switching frequency. FIG. 3 corresponds with a time interval around ωt=40° within the line cycle of the mains voltage (see reference numeral III in FIGS. 2A-2L), FIG. 4 corresponds with a time interval around ωt=60° within the line cycle of the mains voltage (see reference numeral IV in FIGS. 2A-2L), and FIG. 5 corresponds with a time interval around ωt=80° within the line cycle of the mains voltage (see reference numeral V in FIGS. 2A-2L). For all FIGS. 3-5, the diodes of the passive rectifier 11 are in the following switching states: [0117] Diode D.sub.ax=1 (conducting), diode D.sub.ya=0 (blocking); phase connection a is connected with node x; and i.sub.a=i′.sub.x; [0118] Diode D.sub.bx=0 (blocking), diode D.sub.yb=1 (conducting); phase connection b is connected with node y; and i.sub.b=i′.sub.y; [0119] Diode D.sub.cx=0 (blocking), diode D.sub.yc=0 (blocking); and i.sub.c=i′.sub.zc.

[0120] The left columns (‘upper buck circuit’) of FIGS. 3-5 correspond with the operation of the upper buck circuit, while the right columns (‘lower buck circuit’) of FIGS. 3-5 correspond with the operation of the lower buck circuit. Each of FIGS. 3-5 shows: [0121] the control signals of the switches and diodes (S.sub.xp, S.sub.zap, S.sub.zbp, S.sub.zcp, D.sub.mp) of the PWM-modulated upper buck bridge leg 18, and the control signals of the switches and diodes (S.sub.ny, S.sub.nza, S.sub.nzb, S.sub.nzc, D.sub.nm) of the PWM-modulated lower buck bridge leg 19; ‘1’ means ‘on’ and conducting, and ‘0’ means ‘off’ and not conducting; see first rows of FIGS. 3-5, [0122] the voltage v.sub.Lp across the upper buck inductor L.sub.p and the voltage v.sub.Ln across the lower buck inductor L.sub.n; see second rows of FIGS. 3-5, [0123] the current i.sub.Lp in the upper buck inductor L.sub.p (and the switching-cycle-averaged value, i.sub.Lp=I.sub.DC, of this current), and the current i.sub.Ln in the lower buck inductor L.sub.n (and the switching-cycle-averaged value, i.sub.Ln=−I.sub.DC, of this current); see third rows of FIGS. 3-5, [0124] the input current i.sub.x of the upper buck bridge leg 18 (and the switching-cycle-averaged value i.sub.x of this current) and the input current i.sub.y of the lower buck bridge leg 19 (and the switching-cycle-averaged value i.sub.y of this current); see fourth rows of FIGS. 3-5, [0125] the input currents i.sub.zap, i.sub.zbp, i.sub.zcp, i.sub.zp of the upper buck bridge leg 18 (and the switching-cycle-averaged values i.sub.zap, i.sub.zbp, i.sub.zcp, i.sub.zp of these currents) and the input currents i.sub.nza, i.sub.nzb, i.sub.nzc, i.sub.nz of the lower buck bridge leg 19 (and the switching-cycle-averaged values i.sub.nza, i.sub.nzb, i.sub.nzc, i.sub.nz of these currents); see fifth rows of FIGS. 3-5.

[0126] It is noted that FIG. 3 illustrates a situation where the third phase voltage v.sub.c is intermittently connected to the first switch node terminal p by operating the first switch S.sub.zcp with a PWM signal, wherein S.sub.zap, S.sub.zbp=0. The skilled person understands that the operation is similar when the first switch S.sub.lap or the first switch S.sub.zbp is operated with a PWM signal. Similarly, it is noted that FIG. 5 illustrates a situation where the third phase voltage v.sub.c is intermittently connected to the second switch node terminal n by operating the first switch S.sub.nzc with a PWM signal, wherein S.sub.nza, S.sub.nzb=0. The skilled person understands that the operation is similar when the first switch S.sub.nza or the first switch S.sub.nzb is operated with a PWM signal.

[0127] In the regarded time interval of FIG. 3, i.e., around ωt=40° within the line cycle of the mains voltage (see reference numeral III in FIGS. 2A-2L), v.sub.b<v.sub.c<v.sub.a, v.sub.c>0, i′.sub.zc=i.sub.zc=i.sub.zcp, i′.sub.za=i.sub.zap=i.sub.zan=0, i′.sub.zb=i.sub.zbp=i.sub.zbn=0) (i.sub.zcn)=0 and i.sub.zn=0, i.e., the duty cycle of the control signal of switches S.sub.nza, S.sub.nzb, S.sub.nzc, S.sub.zap, S.sub.zbp equals zero (continuously open; not conducting).

[0128] In the regarded time interval of FIG. 4, i.e., around ωt=60° within the line cycle of the mains voltage (see reference numeral IV in FIGS. 2A-2L), v.sub.b<v.sub.c<v.sub.a, v.sub.c=0, i.sub.zp=i.sub.zp=0, i.sub.zn=i.sub.zn=0, i′.sub.za=i.sub.zap=i.sub.zan=0, i′.sub.zb=i.sub.zbp=i.sub.zbn=0, and i′.sub.zc=i.sub.zcp=i.sub.zcn=0 i.e., the duty cycle of the control signals of switches S.sub.nza, S.sub.nzb, S.sub.nzc, S.sub.zap, S.sub.zbp, S.sub.zcp equals zero (continuously open; not conducting).

[0129] In the regarded time interval of FIG. 5, i.e., around ωt=80° within the line cycle of the mains voltage (see reference numeral V in FIGS. 2A-2L), v.sub.b<v.sub.c<v.sub.a, v.sub.c<0, and i′.sub.zc=i.sub.zc=i.sub.zcn, i′.sub.za=i.sub.zap=i.sub.zan=0, i′.sub.zb=i.sub.zbp=i.sub.zbn=0, i.sub.zcp=0 and i.sub.zn=0, i.e., the duty cycle of the control signal of switches S.sub.nzb, S.sub.nzc, S.sub.zap, S.sub.zbp, S.sub.zcp equals zero (continuously open; not conducting).

[0130] In FIGS. 3-5, the semiconductor devices (switches and diodes) of the buck bridge legs 18, 19 of the output power stage 12 are sequentially conducting. For example, in FIG. 3 the conduction sequence of the switches and diodes of the PWM-modulated upper buck bridge leg 18 within a switching period T.sub.s (=1/L) is as follows: [0131] Interval 1 (int1; see left upper figure inset of FIG. 3): S.sub.xp conducts while S.sub.zcp D.sub.zcp and D.sub.mp do not conduct, [0132] Interval 2 (int2; see left upper figure inset of FIG. 3): S.sub.zcp D.sub.zcp conducts while S.sub.xp and D.sub.mp do not conduct, [0133] Interval 3 (int1; see left upper figure inset of FIG. 3): D.sub.mp conducts while S.sub.xp and S.sub.zcp D.sub.zcp do not conduct.

[0134] This sequence repeats itself in the following switching period.

[0135] Although not illustrated, the operation of the first and second buck circuit may be interleaved in order to reduce the current stress of the in- and output filter capacitors, enabling a size reduction of the in- and output filters.

[0136] Different conduction sequences, possibly including more intervals, may also be used for the buck bridge legs. For example, in FIG. 3 a fourth conduction interval may be added to the conduction sequence of the switches and diodes of the PWM-modulated upper buck bridge leg 18 within a switching period T.sub.s (=1/L), which may result in: [0137] Interval 1 (int1′): S.sub.xp conducts while S.sub.zcp, D.sub.zcp and D.sub.pm do not conduct, [0138] Interval 2 (int2′): S.sub.zcp, D.sub.zcp conducts while S.sub.xp and D.sub.pm do not conduct, [0139] Interval 3 (int3′): D.sub.pm conducts while S.sub.xp and S.sub.zcp, D.sub.zpc do not conduct, [0140] Interval 4 (int4′): S.sub.zcp, D.sub.zcp conducts while S.sub.xp and D.sub.pm do not conduct.

[0141] The same holds for the switches and diodes of the PWM-modulated lower buck bridge leg 19.

[0142] FIG. 6 shows the currents i.sub.Lp, i.sub.Ln, i.sub.x, i.sub.y, i.sub.zap, i.sub.zbp, i.sub.zcp, i.sub.zan, i.sub.zbn, i.sub.zcn within a whole line cycle (360°) of the mains voltage. Also shown are the switching-cycle-averaged values i.sub.Lp, i.sub.Ln, i.sub.x, i.sub.y, i.sub.zap, i.sub.zbp, i.sub.zcp, i.sub.zan, i.sub.zbn, i.sub.zcn of these currents which correspond with the currents shown in FIG. 2C.

[0143] An advantage of the electrical converter 10 that is provided by the present disclosure is the integration of the input voltage selector from [REFERENCE 1] into the power stage 12. This allows a reduction of conduction losses as the third-harmonic injection current has less semiconductor devices in the power path. In order to minimize the Total Harmonic Distortion (THD) of the AC input current of the electrical converter, the high-frequency ripple of phase currents i.sub.a, i.sub.b, i.sub.c is advantageously minimized, which is taken care of by the input filter 13.

[0144] In FIG. 8, an electrical converter 200 is shown which differs from converter 10 in that the diodes D.sub.mp, D.sub.nm of the output power stage 12 of the converter shown in FIG. 1 have been replaced with controllable semiconductor switches (S.sub.pm, S.sub.nip), in this case MOSFETs, in the output power stage 212. This allows for the inductor current (i.sub.Lp) to also become negative within the conduction interval of S.sub.pm and for the inductor current (i.sub.Ln) to also become positive within the conduction interval of S.sub.mn, which was not possible for the implementation of the output power stage 12 with diodes (D.sub.mp, D.sub.nm). As a result, quasi-lossless zero-voltage switching (ZVS) or zero-current switching (ZCS) of all the semiconductor switches S.sub.xp, S.sub.zap, S.sub.zbp, S.sub.zcp, S.sub.pm, S.sub.ny, S.sub.nza, S.sub.nzb, S.sub.nzc, S.sub.mn of the output power stage 212 is possible. This allows for power conversion at lower switching losses and thus higher energy efficiency. Also, higher switching frequencies may be used in order to increase the power density (reduced size) and reduce the cost of the electrical converter 200. FIG. 7 shows the currents i.sub.Lp, i.sub.Ln, i.sub.x, i.sub.y, i.sub.zap, i.sub.zbp, i.sub.zcp, i.sub.nza, i.sub.nzb, i.sub.nzc within a whole line cycle (360°) of the mains voltage in case of ZVS operation of output power stage 212. Also shown are the switching-cycle-averaged values i.sub.Lp, i.sub.Ln, i.sub.x, i.sub.y, i.sub.zap, i.sub.zbp, i.sub.zcp, i.sub.zan, i.sub.zbn, i.sub.zcn of these currents which correspond with the currents shown in FIG. 2C.

[0145] The electrical converters 10 (shown in FIG. 1) and 200 (shown in FIG. 8) are unidirectional since the passive rectifier 11 and the output power stages 12, 212 contain diodes, only allowing power to be drawn from the electrical AC grid 20 and provide this power at the output to a load 21. FIG. 9, on the other hand, shows an electrical converter 300 that is bidirectional. Electrical converter 300 differs from converters 10, 200 in that the diodes D.sub.ax, D.sub.bx, D.sub.cx, D.sub.ya, D.sub.yb, D.sub.yc of the passive rectifier 11 and the diodes D.sub.zap, D.sub.zbp, D.sub.zcp, D.sub.mp, D.sub.nza, D.sub.nzb, D.sub.nzc, D.sub.nm of the output power stages 12, 212 have been replaced with controllable semiconductor switches S.sub.xa, S.sub.xb, S.sub.xc, S.sub.ay, S.sub.by, S.sub.cy in the synchronous rectifier 311 and S.sub.pza, S.sub.pzb, S.sub.pzc, S.sub.pm, S.sub.zan, S.sub.zbn, S.sub.zcn, S.sub.mn in the output power stage 312 respectively. It is noted that the electrical converter 300 may be used as a DC-to-AC converter with A, B, C being the output terminals and P, N the input terminals, as will be clear to a person skilled in the art. This may be useful e.g. in applications using solar cells.

[0146] In FIG. 11 another electrical converter 500 is shown which differs from converter 10 in that the stacked buck bridge legs 518, 519 of the output power stage 512 are implemented using a different configuration (parallel configuration) of the diodes and switches. Converter 500 can be used in higher power applications as it provides dedicated buck circuits for each phase leg and the possibility for triple interleaving of the output stage 512. In conjunction, the output filter 514 differs from output filter 14 by the fact that it contains three upper buck inductors Lpa, Lpb, Lpc for connecting the upper buck circuit 518 to upper output terminal P and three lower buck inductors Lna, Lnb, Lnc for connecting the lower buck circuit 519 to the lower output terminal N, for a total of six buck inductors.

[0147] The first buck circuit comprises three first devices 1pa, 1pb, 1pc that are actively switchable for connecting three first switch-node terminals pa, pb, pc to any one of the three phase terminals A, B, C. The second buck circuit comprises three further first devices 1na, 1nb, 1nc that are actively switchable for connecting three second switch-node terminals na, nb, nc to any one of the three phase terminals A, B, C. The first buck circuit further comprises three second device 2pa, 2pb, 2pc connected between the first intermediate node x and the three first switch-node terminals pa, pb, pc, and the second buck circuit comprises three further second devices 2na, 2nb, 2nc connected between the second intermediate node y and the three second switch-node terminals na, nb, nc. The first and the second buck circuits are connected in series between the first intermediate node x and the second intermediate node y such that there is a common node m of the first and second buck circuit. The first buck circuit comprises three third devices 3pa, 3pb, 3pc connected between the common node m and the three first switch-node terminals pa, pb, pc, and the second buck circuit comprises three further third devices 3na, 3nb, 3nc connected between the common node m and the three second switch-node terminals na, nb, nc. The three second devices 2pa, 2pb, 2pc and the three further second device 2na, 2nb, 2nc are actively switchable, such that AC-to-DC conversion is possible. In addition or alternatively, the three third devices and the three further third devices may be actively switchable (not shown), to allow for DC-to-AC conversion.

[0148] The first buck circuit is configured for controlling connections between the three first switch-node terminals pa, pb, pc and the first intermediate node x, the three phase terminals A, B, C, and the common node m; and the second buck circuit is configured for controlling connections between the three second switch-node terminals na, nb, nc and the second intermediate node y, the three phase terminals A, B, C, and the common node m.

[0149] In either electrical converter 10, 200, and 500, diodes may be replaced by current-bidirectional actively switchable semiconductor devices to allow for bidirectional power flow of the electrical converter.

[0150] In FIG. 10 another electrical converter 400 is shown which differs from converter 200 in that the output filter 14 is replaced by an active output filter 414 that includes a boost stage. An active output filter may be used in the electrical converters of either FIG. 1, FIG. 8, FIG. 9, FIG. 11. Also, in the electrical converter 400, the HF capacitors C.sub.xza, C.sub.zcy, C.sub.zbzc, C.sub.zazb, C.sub.xy which interconnect the voltage nodes x, y, a, b, c are connected in a delta configuration instead of a star configuration.

[0151] In either electrical converters 10, 200, 300, and 400, the HF capacitors (C.sub.r, C.sub.za, C.sub.zb, C.sub.zc, C.sub.y, C.sub.xza, C.sub.zcy, C.sub.zbzc, C.sub.zazb, C.sub.xy) may be placed between the phase terminals A, B, C and the rectifier 11, 311, and interconnect the phase terminals A, B, C in the form of a star or delta configuration. A combination of a set of HF capacitors which interconnect the intermediate voltage nodes x, y (as in electrical converters 10, 200, 300, 400) and a set of HF capacitors which interconnect the phase input terminals A, B, C, either in the form of a star or delta configuration, or a combination, may also be used.

[0152] In either electrical converter 10, 200, 300 and 500, the HF capacitors C.sub.x, C.sub.za, C.sub.zb, C.sub.zc, C.sub.y are connected in a star configuration. Alternatively, a delta configuration of these capacitors may be used in either of these electrical converters. In electrical converter 400, the HF capacitors C.sub.xza, C.sub.zcy, C.sub.zbzc, C.sub.zazb, C.sub.xy are connected in a delta configuration. Alternatively, a star configuration of these capacitors may be used.

[0153] As shown in FIG. 1, in order to accomplish the piece-wise sinusoidal shapes of intermediate currents i′.sub.x, i′.sub.y, i′.sub.za, i′.sub.zb, i′.sub.zc which results in three sinusoidal AC phase currents i.sub.a, i.sub.b, i.sub.c, a central control unit 40 may be used which controls all the controllable semiconductor devices (switches) of the electrical converter 10, sending control signals to each switch via a communication interface 50. In particular, semiconductor devices S.sub.zap, S.sub.zbp, S.sub.zcp, S.sub.nza, S.sub.nzb, S.sub.nzc, S.sub.xp, S.sub.ny are controlled by controller 40. Furthermore, the control unit has measurement input ports 42, 43, 44, 45, 46, for receiving measurements of: [0154] 42: the AC-grid phase voltages v.sub.a, v.sub.b, v.sub.c; [0155] 43: the intermediate currents i′.sub.x, i′.sub.y, i′.sub.za, i′.sub.zb, i′.sub.zc, [0156] 44: the inductor currents i.sub.Lp, i.sub.Ln: [0157] 45: the DC bus voltage V.sub.DC; [0158] 46: the DC bus mid-point voltage V.sub.mN,
and an input port 41 to receive a set-value, which may be a requested DC output voltage V*.sub.DC.

[0159] FIG. 12 shows a block diagram of an advantageous implementation of the central control unit 40 which is shown in a schematically way in FIG. 1. The electrical converter 10 is represented in FIG. 12 as a ‘single-wire’ equivalent circuit, wherein the annotations of the elements correspond with those given in FIG. 1. Three slashes in a signal line indicate the bundling of multiple signals, and may represent the transition to a vector representation.

[0160] The goal of the control unit 40 is to control the output voltage V.sub.DC to a requested set-value V*.sub.DC that is received from an external unit via input port 41, and to balance the voltage across the two output capacitors C.sub.Pm and C.sub.mN, for example by controlling the voltage across the lower output capacitor C.sub.mN to be substantially equal to half the DC bus voltage. Additionally, the current drawn from the phase inputs a, b, c may need to be shaped substantially sinusoidal and controlled substantially in phase with the corresponding phase voltage. As explained previously, this can also be achieved by controlling the intermediate currents i′.sub.x, i′.sub.y, i′.sub.za, i′.sub.zb, i′.sub.zc, i.e., instead of directly controlling the phase currents i.sub.a, i.sub.b, i.sub.c, to have piece-wise sinusoidal shapes.

[0161] The control of the output voltage V.sub.DC is advantageously done using a cascaded control structure, comprising an outer voltage control loop 60 and inner current control loop 70. The set-value of the output voltage is input to a comparator 61 via input port 41, and is compared with the measured output voltage obtained from a measurement means 95 (for example comprising a low-pass filter). The output of comparator 61 is the control-error signal of the output voltage, which is further input to a control element 62 (for example comprising a proportional-integral control block) that outputs instantaneous set-values related to the phase currents and/or set-values related to the DC component of the inductor currents. These set-values are input to multiplier 63, and multiplied with signals that are obtained from calculation element 64 that outputs normalized instantaneous values of the phase voltages. The inputs of calculation element 64 are the measured phase voltages obtained from a measurement means 93 (for example comprising a low-pass filter). The output of the multiplier 63 are set-values i*.sub.a, i*.sub.b, i*.sub.c, i*.sub.Lp, i*.sub.Ln for the instantaneous, for example low-pass filtered, phase currents i.sub.a, i.sub.b, i.sub.c, and the instantaneous, for example low-pass filtered, DC component of inductor currents i.sub.Lp, i.sub.Ln. Set-values i*.sub.a, i*.sub.b, i*.sub.c are shaped substantially sinusoidal and positioned substantially in phase with the corresponding phase voltages. Set-values are substantially constant and, as explained above, may represent the DC output current to a load 21 as i.sub.Lp=i.sub.Lp=I.sub.DC and i*.sub.Ln=i.sub.Ln=−I.sub.DC. The set-values i*.sub.a, i*.sub.b, i*.sub.c, i*.sub.Lp, i*.sub.Ln are input to the current controller 70 after passing an addition element 67 and a selection element 81 whose functions are further detailed in the following text.

[0162] The current controller 70 is split into five individual current controllers 71, 72, 73, 74, 75, wherein: [0163] Individual current controller 71 is used for controlling the middle intermediate currents i′.sub.za, i′.sub.zb, i′.sub.zc. This control is done by PWM modulation of the controllable switches of output power stage 12. As a result of the operation of the passive rectifier 11, therewith, controller 71 controls the current of the phase terminal A, B, C, that has a voltage between the highest voltage and the lowest voltage of the three-phase AC voltage; [0164] Individual current controller 72 is used for controlling the upper intermediate current G. This control is done by PWM modulation of the controllable switches of output power stage 12. As a result of the operation of the passive rectifier 11, therewith, controller 72 controls the current of the phase terminal A, B, C, that has the highest voltage of the three-phase AC voltage; [0165] Individual current controller 73 is used for controlling the lower intermediate current i′.sub.y. This control is done by PWM modulation of the controllable switches of output power stage 12. As a result of the operation of the passive rectifier 11, therewith, controller 73 controls the current of the phase terminal A, B, C, that has the lowest voltage of the three-phase AC voltage. [0166] Individual current controller 74 is used for controlling the current in the upper inductor L.sub.p of output filter 14, connected to upper buck bridge leg 18. This control is done by PWM modulation of the controllable switches of output power stage 12. [0167] Individual current controller 75 is used for controlling the current in the lower inductor L.sub.n of output filter 14, connected to lower buck bridge leg 19. This control is done by PWM modulation of the controllable switches of output power stage 12. [0168] Current controllers 74 and 75 jointly control the current supplied to a load 21.

[0169] The skilled person understands that not all current controllers 71, 72, 73, 74, 75 are required. Embodiments of the present disclosure may use any combination of one or more current controllers as defined above, e.g. depending on the application requirements of the electrical converter.

[0170] Selector element 81 is used to send the set-values i*.sub.a, i*.sub.b, i*.sub.c, i*.sub.Lp, i*.sub.Ln, for the instantaneous phase currents and inductor currents to the correct individual current controller 71, 72, 73, 74, 75 depending on the voltage value of the phase terminal A, B, C, resulting in intermediate current set-values i′*.sub.x, i′*.sub.y, i′*.sub.z and inductor current set-values i*.sub.Lp, i*.sub.Ln for each individual current controller, wherein: [0171] the set-value of the phase current of the phase input A,B,C, that has the highest voltage of the three-phase AC voltage is sent to individual current controller 72, resulting in set-value i*′.sub.x; [0172] the set-value of the phase current of the phase input A,B,C, that has the lowest voltage of the three-phase AC voltage is sent to individual current controller 73, resulting in set-value i′*.sub.y; [0173] the set-value of the phase current of the phase input A,B,C, that has a voltage between the highest voltage and the lowest voltage of the three-phase AC voltage is sent to individual current controller 71, resulting in set-value i′*.sub.z=[i′*.sub.za, i′*.sup.zb, i′*.sub.zc]. [0174] the set-value of the inductor current of upper inductor L.sub.p of the output filter 14 is sent to individual current controller 74, resulting in set-value i*.sub.Lp. [0175] the set-value of the inductor current of lower inductor L.sub.n of the output filter 14 is sent to individual current controller 75, resulting in set-value i*.sub.Ln.

[0176] In each individual current controller the received set-value i′*.sub.x, i′*.sub.y, i′*.sub.Z, i′*.sub.Lp, i′*.sub.Ln for the instantaneous current is input to a comparator, for example comparator 76 of individual current controller 71, and compared with the measured current i′.sub.x,measured, i′.sub.y,measured, i′.sub.Z,measured, i.sub.Lp,measured, i.sub.Ln,measured obtained from a measurement means 94 (for example comprising a low-pass filter) and from a measurement means 97. The measured current i′.sub.Z,measured denotes a vector representation of i′.sub.za,measured, i.sub.zb,measured, i.sub.zc,measured The output of the comparator is the control-error signal of the current, which is further input to a control element, for example control element 77 (for example a proportional-integral controller) of individual current controller 71. The output of current controller 70, which is for example a bundled combination of outputs of individual current controllers 71, 72, 73, 74, 75 is input to a PWM generation element, for example PWM generation element 54. The PWM generation element generates the PWM-modulated control signals for the controllable semiconductor switches of the PWM-controlled bridge legs, i.e. the upper buck bridge leg 18 of the upper buck circuit and the lower buck bridge leg 19 of the lower buck circuit. These PWM-modulated control signals are sent to the appropriate bridge legs via communication interface 50.

[0177] DC bus mid-point balancing is done by adding an offset value, by addition element 67, to the set-values i*.sub.a, i*.sub.b, i*.sub.c, i*.sub.Lp, i*.sub.Ln, for the instantaneous, for example low-pass filtered, phase currents i.sub.a, i.sub.b, i.sub.c, and/or instantaneous, for example low-pass filtered, inductor currents i.sub.Lp, i.sub.Ln which are output by multiplier 63. The offset value is obtained by comparing the measured DC bus midpoint voltage obtained from a measurement means 96 (for example comprising a low-pass filter) with a set-value (for example V.sub.DC/2) using comparator 65 and feeding the error signal (output of comparator 65) into a control element 66.

[0178] The phase currents i.sub.a, i.sub.b, i.sub.c shown in FIG. 2D are obtained by controlling the electrical converter 10 using such control unit 40 and control method detailed in the foregoing text. As explained above, the phase currents i.sub.a, i.sub.b, i.sub.c are indirectly controlled, i.e., they are the result of the controlling of the intermediate currents i′.sub.x, i′.sub.y, i′.sub.za, i′.sub.zb, i′.sub.zc (shown in FIG. 2C) and/or the inductor currents i.sub.Lp, i.sub.Ln and of the operation of the passive rectifier 11. The set-points for the intermediate currents (i′*.sub.x, i′*.sub.y, i′*.sub.z) are derived from set-values i*.sub.a, i*.sub.b, i*.sub.c by selector element 81 based on the measured phase voltages.

[0179] FIG. 13 illustrates yet another exemplary embodiment of an electrical converter 600. The electrical converter comprises a parallel connection of bridge legs 618, 619. More in particular, the first and the second buck circuits are connected in parallel between the first intermediate node and the second intermediate node. The first buck circuit comprises three first devices 1pa, 1pb, 1pc, a second device 2p, and a third device 3p connected between the second intermediate node y and a first switch-node terminal p. The second buck circuit comprises three further first devices 1na, 1nb, 1nc, a further second device 2n, and a further third device 3n connected between the first intermediate node x and a second switch-node terminal n. The third device 3p is connected in series with the three first devices 1pa, 1pb, 1pc between the second intermediate terminal y and the respective phase terminal A, B, C, and the further third device 3n is connected in series with the three further first devices 1na, 1nb, 1nc between the first intermediate terminal x and the respective phase terminal A, B, C.

[0180] Also, in the electrical converter 600, diodes of the rectifier 11 may be replaced by actively switchable semiconductor devices to allow for bidirectional power flow of the electrical converter (as in the embodiment of FIG. 9). In electrical converter 600, the HF capacitors are connected in a star configuration. Alternatively, a delta configuration of these capacitors may be used. Also, instead of a passive output filter 14, an active output filter may be used in electrical converter 600 as FIG. 11.

[0181] The functions of the functional block labelled as “controller”, may be provided through the use of dedicated hardware as well as hardware capable of executing software in association with appropriate software. When provided by a processor, the functions may be provided by a single dedicated processor, by a single shared processor, or by a plurality of individual processors, some of which may be shared. Moreover, explicit use of the term “controller” should not be construed to refer exclusively to hardware capable of executing software, and may implicitly include, without limitation, digital signal processor (DSP) hardware, network processor, application specific integrated circuit (ASIC), field programmable gate array (FPGA), read only memory (ROM) for storing software, random access memory (RAM), and non volatile storage. Other hardware, conventional and/or custom, may also be included.

[0182] Whilst the principles of the present disclosure have been set out above in connection with specific embodiments, it is to be understood that this description is merely made by way of example and not as a limitation of the scope of protection which is determined by the appended claims.