SNAPSHOT INFRARED SENSOR

Abstract

An infrared sensor includes an assembly of pixels juxtaposed in rows and in columns, each pixel integrating an imaging microbolometer and an integrator assembly. The integrator assembly includes a transistor assembled as an amplifier, and a capacitor assembled in feedback on the transistor between an output node and an integration node. The integration node is connected to a skimming transistor operating as a current mirror with a skimming control transistor offset outside of the pixel. A skimming current flowing through the skimming control transistor is controlled according to the temperature of at least one thermalized microbolometer. The current mirror assembly enables to transmit the skimming current flowing through said skimming control transistor onto the integration node so that the capacitor integrates the difference between a current flowing through the imaging microbolometer and the skimming current.

Claims

1. An infrared sensor comprising an assembly of pixels juxtaposed in rows and in columns, each pixel integrating an imaging microbolometer connected between a reference voltage and an integration node via an injection transistor having a gate voltage enabling to set a voltage across the imaging microbolometer, so that the resistance variations of the imaging microbolometer, due to infrared radiations, cause a variation of a current flowing through said imaging microbolometer, wherein the infrared sensor comprises, under the surface of each pixel, an integrator assembly comprising: a transistor assembled as an amplifier between said integration node and an output node; and a capacitor assembled in feedback on said transistor between said output node and said integration node; said integration node being connected to a skimming transistor operating as a current mirror with a skimming control transistor offset outside of said pixel, a skimming current flowing through said skimming control transistor being controlled according to the temperature of at least one thermalized microbolometer, said current mirror assembly enabling to transmit the skimming current flowing through the skimming control transistor onto the integration node so that said capacitor integrates the difference between said current flowing through said imaging microbolometer and said skimming current.

2. An infrared sensor according to claim 1, wherein the gate voltage of the injection transistor is controlled according to a bias control transistor, offset outside of pixel, according to the temperature of at least one thermalized microbolometer.

3. An infrared sensor according to claim 1, wherein the skimming current is in the range from 50 to 200 nanoamperes.

4. An infrared sensor according to claim 1, wherein said infrared sensor comprises transistors having a leakage current smaller than 1 nA.

5. An infrared sensor according to claim 1, wherein the imaging microbolometer has a resistance in the range from 40 to 60 MΩ for a 30° C. temperature.

6. An infrared sensor according to claim 1, wherein a biasing of the amplifier-assembled transistor is performed by the application of a reference voltage at the level of a terminal of said amplifier-assembled transistor, opposite to the terminal coupled to said output node.

7. An infrared sensor according to claim 6, wherein the reference voltage is applied by a diode-assembled transistor.

8. An infrared sensor according to claim 1, wherein the output node is biased by the application of a bias current in the range from 0.5 to 2 microamperes.

9. An infrared sensor according to claim 1, wherein the output node is coupled to a switched-capacitor filter formed of a switch and of a capacitor.

10. An infrared sensor according to claim 9, wherein the switched-capacitor filter is coupled to a readout capacitor intended to be charged, after the integration, to allow a reading of a voltage while performing another integration.

11. An infrared sensor according to claim 1, wherein the output node is coupled to a transistor assembled as a voltage follower.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0070] The present invention will be better understood on reading of the following description provided as an example only in relation with the accompanying drawings, where the same reference numerals designate the same or similar elements, in which:

[0071] FIG. 1 illustrates an infrared sensor of the state of the art with a readout and skimming circuit arranged at the column foot;

[0072] FIG. 2 illustrates the equivalent electric diagram of the reading from an imaging microbolometer of FIG. 1;

[0073] FIG. 3 illustrates a readout circuit integrated under a pixel of an infrared sensor according to an embodiment of the invention;

[0074] FIG. 4 illustrates an offset skimming control circuit intended to be connected to the readout circuit of FIG. 3 according to an embodiment of the invention; and

[0075] FIG. 5 illustrates an offset bias control circuit intended to be connected to the readout circuit of FIG. 3 according to an embodiment of the invention.

DETAILED DESCRIPTION

[0076] FIG. 3 illustrates a readout circuit 11 of an imaging microbolometer integrated under the surface of each pixel of an infrared sensor. The structure of the imaging microbolometer is similar to that described in the state of the art, that is, it integrates a membrane sensitive to the infrared radiation having a resistivity varying according to the infrared radiation captured by this membrane. This membrane is coupled by at least two pads to the readout circuit 11 illustrated in FIG. 3.

[0077] Within this readout circuit 11, the assembled formed by the pads and the membrane is schematized by bolometric resistor R.sub.ac, which corresponds to the variable resistance of the imaging microbolometer of each pixel. Unlike membranes of the state of the art, the membrane of the imaging microbolometer is formed in such a way that the resistance of the imaging microbolometer is in the range from 40 to 60 MO at ambient temperature. Typically, for a 30° C. temperature, the membrane may be formed to have a 50 MΩ resistance. This specific resistance may be conventionally reached by adapting the thickness of the material forming the membrane and/or the design of the membrane, for example, the length of the support and heat dissipation arms.

[0078] Under the imaging microbolometer, the substrate integrates a CMOS stage comprising all the other components illustrated in the readout circuit 11 of FIG. 3. This readout circuit 11 is preferably formed with transistors exhibiting a leakage current smaller than 1 nA.

[0079] As illustrated in FIG. 3, readout circuit 11 comprises an injection transistor N2 enabling to set the voltage V.sub.ac across the imaging microbolometer by means of its gate voltage GAC. Thus, the voltage V.sub.ac across the imaging microbolometer is fixed and imposed via gate voltage GAC by the assembly of FIG. 5. Further, the imaging microbolometer is also connected to a voltage source VDET, preferably the ground of readout circuit 11. In the example of FIG. 3, the imaging microbolometer is connected to the bottom of readout circuit 11 by means of an NMOS-type injection transistor N2. As a variant, the left-hand portion of the circuit may be turned upside down and the imaging microbolometer may be connected via a PMOS transistor to the top of the readout circuit without changing the invention.

[0080] In addition to the source coupled to the imaging microbolometer, the drain of the injection transistor N2 is connected to an integration node Ne. This integration node Ne is also connected to a PMOS-type skimming transistor P1. Skimming transistor P1 is coupled to a constant voltage source VSK. The gate voltage GCM of this skimming transistor P1 is connected to an offset circuit 19 (FIG. 4) enabling to transmit a skimming control signal to all the readout circuits 11 of the different pixels. As a variant, a plurality of offset circuits 19 may be used for different readout circuits integrated under different pixels without changing the invention. Further, the left-hand portion of the circuit may be turned upside down and skimming transistor P1 may be formed by an NMOS transistor without changing the invention.

[0081] Integration node Ne is also coupled to the gate of a transistor N4 assembled as an amplifier to form a CTIA-type assembly with a capacitor C.sub.int assembled in feedback between an output node No and integration node Ne. Thus, the drain of transistor N4 is connected to output node No, while the gate of this transistor N4 is connected to integration node Ne. Output node No is also connected to a switch RAZ enabling to short-circuit capacitor C.sub.int to reset the integration.

[0082] To obtain a constant voltage equivalent to the lower saturation threshold of a CTIA-type integrator, the source of transistor N4 is connected to constant voltage VDET via a diode D1. Preferably, this diode D1 is formed by a diode-assembled transistor.

[0083] Further, the output node is also coupled to a current source connected between constant voltage VSK and output node No to apply a fixed current, for example 1 μA, on the drain of transistor N4 and to bias the latter.

[0084] For example, injection transistor N2 is biased with a current I.sub.cm in the order of 100 nA.

[0085] The current I.sub.Ac flowing through bolometric resistor R.sub.ac corresponds to the bias current I.sub.cm plus the current variations due to the resistance variations of bolometric resistor R.sub.ac. At the level of integration node Ne, bias current I.sub.cm is subtracted to current I.sub.Ac, and only the current variations due to the resistance variations of bolometric resistor R.sub.ac are integrated in capacitor C.sub.int.

[0086] At the level of output node No, readout circuit 11 also comprises a switched-capacitor filter comprising a switch PART and a capacitor C.sub.part connected between switch PART and constant voltage VDET. When switch PART is turned on, the charges present in integration capacitor C.sub.int are transferred into storage capacitor C.sub.part. Then, switch PART may be turned off and a new integration may be performed after the turning on of switch RAZ for a few microseconds.

[0087] Similarly, the charges present in capacitor C.sub.part may then be transferred to a readout capacitor C.sub.lec, connected between a switch SH and constant voltage VDET, when switch SH is turned on. The reading from this capacitor C.sub.lec is obtained by an NMOS-type output transistor SF having its drain connected to voltage VSK and the source is coupled to an output signal VOUT via a switch LEC(i,j).

[0088] When the infrared sensor requires the reading of the pixel corresponding to the readout circuit of FIG. 3, the i and j coordinates of the pixel in the array are used to control switch LEC(i,j) and obtain the voltage value across capacitor C.sub.lec.

[0089] In addition to these elements present at the level of each pixel, the circuits illustrated in FIGS. 4 and 5 are preferably mutualized for all the pixels to deliver the gate voltages of GAC and GCM of transistors N2 and P1.

[0090] FIG. 4 illustrates the generation of gate voltage GCM by means of a circuit 19 integrating five thermalized microbolometers, of equivalent resistance R.sub.cm, assembled in parallel. Preferably, these thermalized microbolometers are formed in the same way as the imaging microbolometers of the pixels and have the same resistivity. However, these thermalized microbolometers are insulated from the observed scene by means of a protection shield so that they only capture the temperature variations of the substrate corresponding to the temperature variations of the focal plane of the image.

[0091] In the state of the art, a thermalized microbolometer is used at the level of each readout circuit of each column: there are thus as many thermalized microbolometers as columns in the array. In the invention, these five thermalized microbolometers are sufficient to deliver all the gate voltages GCM, which significantly decreases the surface area used around the pixels to form these thermalized microbolometers while improving the accuracy of skimming current I.sub.cm by averaging the current flowing through a plurality of thermalized microbolometers.

[0092] In circuit 19, a voltage V.sub.av originating from a digital-to-analog converter, not shown, enables to adjust gate voltages GCM and, more particularly, the current I.sub.cm intended to flow between the transistor P1 and the integration node Ne of each readout circuit 11. For this purpose, the five thermalized microbolometers are connected between constant voltage VDET and the source of an NMOS-type transistor N1.

[0093] The gate of this transistor N1 is connected to the output of an operational amplifier having its positive input coupled to voltage V.sub.av and its negative input connected to the source of this transistor N1. The drain of transistor N1 is connected to the drain of a PMOS-type transistor P1b. The source of this transistor P1b is connected to constant voltage VSK and the gate voltage of this transistor P1b enables to deliver voltage GCM.

[0094] Further, this transistor P1b is assembled in feedback with the gate coupled to the drain to form, with transistor P1, a current mirror where the current I.sub.cm obtained by the thermalized microbolometers is copied between transistor P1 and integrating node Ne. If the left-hand assembly of the readout circuit 11 of FIG. 3 is turned upside down, this circuit 19 also has to be turned upside down.

[0095] The assembly of FIG. 5 is close to that of FIG. 4 with the difference that gate voltage GAC is not extracted at the level of the gate of PMOS transistor P2, but at the level of the gate of NMOS transistor N2b. The voltage V.sub.ac imposed at the input of the operational amplifier enables to set the voltage across the imaging microbolometer by a current mirror operation between transistors N2 and N2b.

[0096] Similarly, current I.sub.cm2 is copied by a current mirror assembly between the transistors N2 of FIG. 3 and N2b of the circuit 21 of FIG. 5. However, the current I.sub.ac flowing through bolometric resistor R.sub.ac is not directly equivalent to I.sub.cm2 since it depends on the heating of the imaging microbolometer caused by the infrared flux.

[0097] Thus, with these very few components, the invention enables to obtain a very accurate reading of all the pixels of an infrared sensor.

[0098] Further, the elements of the readout circuit 11 of FIG. 3 may be integrated under the surface of each pixel to obtain a simultaneous reading of all the pixels of an infrared image. Thereby, the infrared image acquisition speed is significantly optimized, particularly for high resolutions (and for example 1280×1024 pixels).