GRADED HYDROGEN-FREE CARBON-BASED HARD MATERIAL LAYER COATED ONTO A SUBSTRATE

20220275498 · 2022-09-01

    Inventors

    Cpc classification

    International classification

    Abstract

    A method to produce a hard coating onto a substrate, wherein the hard coating comprises a hydrogen-free amorphous carbon coating, wherein the amorphous carbon coating is deposited onto the substrate using a cathodic arc discharge deposition technique, wherein a bias voltage is applied to the substrate with an absolute value that is greater than 0 V, preferably greater than 10 V and less than 1000 V, and wherein the absolute value of the bias voltage is increased during the coating process to obtain a first structure and a second structure and a gradient between the first and the second structure along the coating thickness, wherein the first and the second structure comprise sp2 and sp3 carbon bonds but differ in their relative concentration, wherein at least one coating pause is applied during the coating process in order to reduce the substrate temperature during the coating pause.

    Claims

    1. A method for producing a hard coating onto a substrate, comprising: depositing the hard coating comprising a hydrogen-free amorphous carbon coating onto a substrate using a cathodic arc discharge deposition technique, wherein a bias voltage is applied to the substrate with an absolute value that is greater than 0 V and less than 1000 V, and wherein the absolute value of the bias voltage is increased during the coating process to obtain a first structure and a second structure and a gradient between the first structure and the second structure along a coating thickness, wherein the first structure and the second structure comprise sp2 and sp3 carbon bonds but differ in their relative concentration, and applying at least one coating pause during the coating process in order to reduce a substrate temperature during the coating pause.

    2. The method according to claim 1, wherein the coating pause lasts at least one minute.

    3. The method according to claim 1, wherein the increase of the absolute value of the bias voltage is set by a rate defined by a ratio ΔU/Δs, which is a ratio of the absolute voltage difference to a unit of time.

    4. The method according to claim 1, wherein the increase of the absolute value of the bias voltage is set by a rate defined by a ratio of ΔU/Δd, which is a ratio between the absolute voltage difference to a difference of coating thickness.

    5. The method according to claim 4, wherein the ratio of ΔU/Δd is between about 0.02 V/nm and about 0.5 V/nm.

    6. The method according to claim 1, wherein the absolute bias voltage is increased in a linear manner.

    7. The method according to claim 1, wherein the absolute bias voltage is increased stepwise during the coating process.

    8. The method according to claim 1, wherein before the hard coating is coated onto the substrate, the substrate is pre-heated to about 150° C. in a vacuum chamber.

    9. The method according to claim 1, wherein before coating the substrate, the substrate is pre-treated by metal-ion etching (MIE) and/or by adding a very thin adherence layer.

    10. The method according to claim 8, comprising cooling the substrate to about 100° C. after the pre-heating and before applying the coating to the substrate to ensure good adhesion.

    11. The method according to claim 1, comprising coating the substrate with a carbon transition layer (C-Interlayer) at a process pressure between 1×10.sup.−3 to 2×10.sup.−3 mbar and carrying out carbon doping at an argon flow between 50 and 80 sccm, wherein the argon is introduced by means of gas showers in front of carbon targets, wherein the carbon targets are ignited by trigger wire and operated at a target current between 40 and 55 A, wherein resulting carbon ions (C.sup.+) are then accelerated onto the substrate by a bias voltage between −500 V and −300 V, which leads to an implantation of the carbon into a thin chromium layer, wherein the absolute value of the negative bias voltage is then reduced from −300V to −150 V.

    12. The method according to claim 1, comprising coating the substrate with the hard coating (ta-C coating) at a process pressure between 1×10.sup.−3 and 2×10.sup.−3 mbar and an argon flow between 80 and 100 sccm, wherein carbon targets are operated at a lower target current of about 25 to about 35 A, wherein the absolute value of the negative bias voltage is increased at a rate (ramp) over the entire coating time from about 0 to about −200 V, wherein the target current of the carbon targets is kept constant, wherein by applying a ramp of the bias voltage at the beginning of the coating, the ta-C layer with lower hardness is produced, wherein increasing the bias voltage afterwards creates a harder layer in a range between 40 and 50 GPa, wherein at bias voltages of about −160 V and a substrate temperature close to 160° C., a proportion of sp2 bonds is increased whereas a proportion of sp3 bonds is reduced, which results in a graphite-like top layer, which has a significantly lower hardness than a core of the coating, with the top layer having a hardness of about 15 to 30 GPa.

    13. The method according to claim 1, wherein a surface of the carbon-based coating is post-processed by sanding, grinding, and/or band-finishing.

    14. A workpiece comprising: a substrate and a hard coating coated onto the substrate, wherein the hard coating comprises a hydrogen-free amorphous carbon coating, wherein the amorphous carbon coating is deposited onto the substrate preferably using a method according to claim 1, wherein the hard coating obtains a first structure and a second structure and a gradient between the first structure and the second structure along the coating thickness, wherein the first structure and the second structure comprise sp2 and sp3 carbon bonds but differ in their relative concentration.

    15. The workpiece according to claim 14, wherein a surface roughness of the workpiece is between Rz=0.5 μm and 1.5 μm, target values for the roughness are Spk<0.4 μm, and/or Rpk<0.5 μm and/or Rpkx<0.2 μm and/or RfpH5n(F)<0.6 μm, and/or GKV<6 μm.

    16. The workpiece according to claim 14, wherein the hard coating can be split in three ranges A, B and C, wherein the region A is close to the substrate and corresponds to a fine structure having a thickness between 200 and 1000 nm, on top of the region A the region B is coated and is vitreous and more dense than the region A, the region B having a thickness between 200 and 500 nm, on top of the region B the region C is coated showing a more porous and rough coating compared to the region B, wherein in the region C the coating sp2 bonds are predominant and the coating of region C has a reduced hardness compared to the region B, wherein the thickness of the region C is between 200 and 500 nm.

    17. The workpiece according to claim 14, wherein on top of the substrate a Cr-layer is coated, and on top of the Cr-layer a C-interlayer is coated, and on top of the C-interlayer the hard coating is coated.

    18. The method according to claim 8, comprising using an integrated radiation heater to pre-heat the substrate.

    19. The method according to claim 9, wherein before coating the substrate, the substrate is pre-treated by adding a very thin Cr-based layer as the adherence layer.

    Description

    [0036] The invention is shown schematically in the drawings on the basis of embodiments and is further described with reference to the drawings.

    [0037] FIG. 1 shows a carbon-based coating build up from left to right showing different coating structures along the coating thickness. Temperature of the substrate is shown in red, bias voltage is shown in blue. The different coating structures are visible in the three regions marked by A, B, C.

    [0038] FIG. 2 shows the same cross-section as FIG. 1 without the legend and higher contrast to show the difference between the coating structures along the coating thickness.

    [0039] FIG. 3 shows a coating as described by the present invention. (1) is the substrate, (2) Cr-layer, (3) C-interlayer, (4) ta-C at low bias voltage (0-20 V), (5) ta-C at intermediate bias voltage (20-160 V) and (6) the ta-C top layer at bias voltages (160-200 V).

    [0040] FIG. 4 shows the relevant process data such as cathodic arc current, absolute bias voltage, gas flow and substrate temperature, where the values in the legend represents the full scale at 100. The X-Axis represents the time in minutes.

    [0041] FIG. 5 shows a table with the different roughness values before and after the surface finish of the coating using a) classical methods and b) optical method.

    [0042] FIG. 1 shows the carbon-based coating build up from left to right showing the different coating structures along the coating thickness. Temperature of the substrate is shown in red, bias voltage is shown in blue. The coating can be split in 3 ranges A, B, C. The region A close to the substrate corresponds to a fine structure having a coating thickness between 200 to 1000 nm, preferably about 700 mn, where the absolute bias voltage is increased from 10 V to 100V and substrate temperature increases from about 140 to 180° C. The coating pause between the region A and B induces a drop in the substrate temperature of about 20° and afterwards when the bias current is increased from 100 V to 150 V, the temperature increases from about 160° C. to 190° C. The coating in region B is vitreous and more dense (ta-C) with a coating thickness range of 200 to 500 nm, preferably about 400 nm. Region C shows a more porous and rough coating, where the absolute bias voltage is increased from 150 V to 200 V, there the substrate temperature increases from 190° C. to 220° C. In this region of the coating sp2 bonds are predominant and the coating has a reduced hardness and the coating thickness is in the range of 200 to 500 nm, preferably about 400 nm.

    [0043] FIG. 2 shows the same cross-section as FIG. 1 without the legend and higher contrast to show the difference between the coating structures along the coating thickness.

    [0044] FIG. 3 shows a coating as described by the present invention with absolute values of bias voltage as illustration. (1) is the substrate, (2) Cr-layer, (3)C-interlayer, (4) ta-C at low bias voltage (0-20 V), (5) ta-C at intermediate bias voltage (20-160 V) and (6) the ta-C top layer at bias voltages (160-200 V).

    [0045] FIG. 4 shows some relevant process data such as cathodic arc current, absolute bias voltage, gas flow and substrate temperature, where the values in the legend represents the full scale at 100. The X-Axis represents the time in minutes. The coating process in this example is represented by the dark blue line which is the input of the cathodic arc current and lasts about slightly more than 200 minutes, at about 100 minutes the process is interrupted to apply the coating pause of about 20 minutes, and afterwards the coating process continues until the desired coating thickness is reached. During the whole coating time of 200 minutes, including the coating pause, the absolute bias voltage, which is represented by the green line, is increased from 10 V to 200 V. During the break there is no coating process and the bias voltage remains constant but has no effect on the substrate. The positive effect of the coating pause can be seen on the substrate temperature that is dropping from 175° C. down to 140° C. resulting to a favorable temperature to create more sp3 bonds for a longer period of time, consequently a larger region on the coating where ta-C structure is present. The different data and ramps, such as the increase rate of the absolute bias voltage, the time of coating, the time of coating pause and number of coating pause are just shown as illustration. For example a different increase rate of the absolute bias voltage could be chosen between each interruption of the coatings or the coating could be interrupted more than one time, or the coating pause could last less or more than 20 minutes but not shorter than 1 minute.

    [0046] FIG. 5 shows typical roughness values for the unfiltered bias-ramp layer before (as-coated) and after finish can be decreased typically from Rz=1.5 down to 0.5 μm. The target values for the roughness and optimum values shown in parenthesis have been found to be Spk<0.4 μm (0.3 μm), Rpk<0.5 μm (0.3 μm), Rpkx<0.2 μm (0.1 μm), RfpH5n(F)<0.6 μm (<0.3 μm), GKV<6 μm (3 μm).