METHOD AND DEVICE FOR SHORT-CIRCUIT DETECTION BY SATURATION DETECTION IN POWER SEMICONDUCTOR SWITCHES

Abstract

The present invention relates to a method for short-circuit detection by saturation detection in power semiconductor switches and to a corresponding device. A reference voltage (U.sub.ref) is provided as a function of a supply voltage (U.sub.VDD) of a power semiconductor switch. A differential voltage (U.sub.diff) is generated from the difference of a voltage drop (U.sub.Δ) of a load path of the power semiconductor switch and the provided reference voltage (U.sub.ref). The generated differential voltage (U.sub.diff) is compared with a predetermined threshold voltage (U.sub.lim). A short-circuit current in the load path of the power semiconductor switch is detected when the differential voltage (U.sub.diff) exceeds the threshold voltage (U.sub.lim). In this case, the power semiconductor switch is opened.

Claims

1. A method for short-circuit detection by saturation detection in power semiconductor switches, comprising the following steps: providing (1) a reference voltage (U.sub.ref) depending on a supply voltage (U.sub.VDD) of a power semiconductor switch (20), with the result that the reference voltage (U.sub.ref) follows changes in the supply voltage (U.sub.VDD); generating (2) a differential voltage (U.sub.diff) which corresponds to a difference between a voltage drop (U.sub.Δ) across a load path of the power semiconductor switch (20) and the provided reference voltage (U.sub.ref); comparing (3) the generated differential voltage (U.sub.diff) with a predetermined limit voltage (U.sub.lim), wherein a short-circuit current is detected in the load path of the power semiconductor switch (20) when the differential voltage (U.sub.diff) exceeds the limit voltage (U.sub.lim); and opening (4) the power semiconductor switch (20) when a short-circuit current has been detected in the load path of the power semiconductor switch (20).

2. The method as claimed in claim 1, wherein the reference voltage (U.sub.ref) is provided between a Zener diode (13.1), which is electrically connected to the supply current source for the power semiconductor switch (20), and a parallel circuit comprising a first resistor (13.2) and a first capacitor (13.3), which is electrically connected to ground (GND).

3. The method as claimed in claim 1, wherein the voltage drop (U.sub.Δ) across the load path of the power semiconductor switch (20) is tapped off at an anode of at least one decoupling diode (11), which is electrically connected to a drain terminal or a collector terminal of the power semiconductor switch (20), wherein the at least one decoupling diode (11) is fed an auxiliary current from a current source (12) by means of a pull-up resistor (19).

4. The method as claimed in claim 3, further comprising the following step: preventing (5) charging of an input filter, which is connected electrically in parallel with the power semiconductor switch (20), by means of the pull-up resistor (19) in a switched-off state by means of a clamping transistor (16), which is connected electrically in parallel with the input filter.

5. A device (10) for short-circuit detection by saturation detection in power semiconductor switches, comprising: at least one decoupling diode (11), which is designed to be electrically connected to a drain terminal (21) or a collector terminal of a power semiconductor switch (20), wherein a voltage drop (U.sub.Δ) across an anode of the at least one decoupling diode (11) corresponds to a voltage drop (U.sub.Δ) across a load path of the power semiconductor switch (20); a current source (12), which is electrically connected to the at least one decoupling diode (11) and is designed to feed an auxiliary current into a load path of the power semiconductor switch (20) when the at least one decoupling diode (11) is electrically connected to the drain terminal or the collector terminal of the power semiconductor switch (20); a reference voltage source (13), which is designed to be electrically connected to a supply current source for the power semiconductor switch (20) and to provide a reference voltage (U.sub.ref) depending on a supply voltage (U.sub.VDD) of the supply current source, with the result that the reference voltage (U.sub.ref) follows changes in the supply voltage (U.sub.VDD); a comparator circuit (14), which is electrically connected to the at least one decoupling diode (11) and the reference voltage source (13) and is designed to generate a differential voltage (U.sub.diff), which corresponds to a difference between the voltage drop (U.sub.Δ) across the load path of the power semiconductor switch (20) and the provided reference voltage (U.sub.ref); and evaluation electronics (15), which are designed to compare the generated differential voltage (U.sub.diff) with a predetermined limit voltage (U.sub.lim), wherein a short-circuit current is detected in the load path of the power semiconductor switch (20) when the differential voltage (U.sub.diff) exceeds the limit voltage (U.sub.lim), and to open the power semiconductor switch (20) when a short-circuit current has been detected in the load path of the power semiconductor switch (20).

6. The device (10) as claimed in claim 5, wherein the reference voltage source (13) comprises a Zener diode (13.1) and a parallel circuit comprising a first resistor (13.2) and a first capacitor (13.3), wherein the reference voltage (U.sub.ref) is provided between the Zener diode (13.1), which is electrically connected to the supply current source for the power semiconductor switch (20), and the parallel circuit, which is electrically connected to ground (GND).

7. The device (10) as claimed in claim 5, wherein the at least one decoupling diode (11) is fed the auxiliary current by means of a pull-up resistor (19).

8. The device (10) as claimed in claim 5, further comprising an input filter, which is connected electrically in parallel with the power semiconductor switch (20).

9. The device (10) as claimed in claim 8, further comprising a clamping transistor (16), which is connected electrically in parallel with the input filter and is designed to prevent charging of the input filter by means of the pull-up resistor (19) in a switched-off state.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0038] The invention and the technical background will be explained in more detail below with reference to the figures. It will be mentioned that the invention is not intended to be restricted by the exemplary embodiments shown. In particular, insofar as it is not explicitly illustrated otherwise, it is also possible to extract sub-aspects of the substantive matter explained in the figures and to combine them with other parts and knowledge from the present description and/or figures. In particular, it will be mentioned that the figures and in particular the illustrated size relationships are merely schematic. The same reference symbols denote identical subjects, with the result that, if appropriate, explanations can be used from other figures in supplementary fashion.

[0039] FIG. 1 shows a schematic flowchart of the method for short-circuit detection by saturation detection in power semiconductor switches.

[0040] FIG. 2 shows a schematic basic circuit diagram of the device for short-circuit detection by saturation detection in power semiconductor switches.

[0041] FIG. 3 shows a schematic equivalent circuit diagram of a special embodiment of the device from FIG. 2.

DETAILED DESCRIPTION

[0042] FIG. 1 shows, schematically, the method for short-circuit detection by saturation detection in power semiconductor switches. The method comprises the step of providing 1 a reference voltage U.sub.ref, generating 2 a differential voltage U.sub.diff, comparing 3 the generated differential voltage U.sub.diff with a predetermined limit voltage U.sub.lim, opening 4 the power semiconductor switch and optionally preventing 5 charging of an input filter. The steps of the method can take place in any desired sequence and/or at least partially at the same time.

[0043] In the step of providing 1 the reference voltage U.sub.ref, the reference voltage is provided depending on the supply voltage U.sub.VDD of the power semiconductor switch. The reference voltage U.sub.ref in this case follows changes in the supply voltage U.sub.VDD. For this purpose, the reference voltage U.sub.ref is provided or tapped off between a Zener diode and a parallel circuit comprising a first resistor and a first capacitor. The Zener diode is electrically connected to the supply current source for the power semiconductor switch. The parallel circuit comprising the first resistor and the first capacitor is electrically connected to ground GND. The supply current source provides current with a supply voltage U.sub.VDD of 18 V.

U.sub.ref˜U.sub.VDD

[0044] In the step of generating 2 the differential voltage U.sub.diff, the differential voltage U.sub.diff corresponds to a difference between a voltage drop U.sub.Δ across a load path of the power semiconductor switch and the provided reference voltage U.sub.ref.

U.sub.diff=U.sub.66−U.sub.ref

[0045] The voltage drop U.sub.Δ across the load path of the power semiconductor switch is tapped off at an anode of at least one decoupling diode, which is electrically connected to a drain terminal or a collector terminal of the power semiconductor switch. The at least one decoupling diode is in this case fed the auxiliary current from a current source by means of a pull-up resistor.

[0046] In the step of comparing 3 the generated differential voltage U.sub.diff with the predetermined limit voltage U.sub.lim, the differential voltage U.sub.diff is compared with the predetermined limit voltage U.sub.lim. The limit voltage U.sub.lim is in this case 10 V to 20 V. In this case, a short-circuit current is detected in the load path of the power semiconductor switch when the differential voltage U.sub.diff reaches or exceeds the limit voltage U.sub.lim.

U.sub.diff≥U.sub.lim

[0047] In the step of opening 4 the power semiconductor switch, the power semiconductor switch is opened when a short-circuit current has been detected in the load path of the power semiconductor switch.

[0048] In addition, in the optional step of preventing 5 charging of the input filter, charging of the input filter by means of the pull-up resistor is prevented in the switched-off state. The input filter is connected electrically in parallel with the power semiconductor switch. By means of the pull-up resistor, the input filter could be charged in a switched-off state. This is prevented by a clamping transistor, which is connected electrically in parallel with the input filter.

[0049] FIG. 2 shows, schematically, the device 10 for short-circuit detection (short-circuit detection circuit) by saturation detection in power semiconductor switches. The device 10 can implement the method from FIG. 1.

[0050] The device 10 comprises the following components: [0051] a decoupling diode 11 to a drain terminal 21 (or alternatively to a collector terminal (not illustrated)) of the power semiconductor 20; [0052] a current source 12 (in the form of a pull-up resistor, not illustrated); [0053] a reference voltage source 13 with dependence on a supply voltage U.sub.VDD of the power semiconductor 20; [0054] a comparator circuit 14; [0055] evaluation electronics 15; [0056] a clamping transistor 16; and [0057] output circuitry 17.

[0058] The decoupling diode 11 is electrically connected (with its anode) to the current source 12 and is also electrically connected, in the direction of flow, (with its cathode) to the drain terminal 21 of the power semiconductor switch 20. The voltage drop U.sub.Δ across the load path of the power semiconductor switch 20 is tapped off at the anode of the decoupling diode 11. The current source 12 in this case provides the auxiliary current from the supply voltage U.sub.VDD for the decoupling diode 11 in order that the voltage drop U.sub.Δ can be measured or tapped off at the anode of the decoupling diode 11.

[0059] The reference voltage source 13 provides the reference voltage U.sub.ref. The reference voltage U.sub.ref follows a supply voltage U.sub.VDD of the supply current source of the power semiconductor switch 20.

[0060] The decoupling diode 11 (with its anode) and the reference voltage source 13 are electrically connected to the comparator circuit 14 in such a way that the output of the comparator circuit 14 has the differential voltage U.sub.diff, wherein the differential voltage U.sub.diff corresponds to the difference between the voltage drop U.sub.Δ across the load path of the power semiconductor switch 20 and the reference voltage U.sub.ref.

[0061] The comparator circuit 14 is electrically connected with its output to the evaluation electronics 15. The evaluation electronics 15 are in this case an integrated circuit (IC), which can implement the Desat method. In this case, the power semiconductor switch 20 is opened by the evaluation electronics/IC 15 when the differential voltage U.sub.diff is equal to or greater than a predetermined limit voltage U.sub.lim. In this case, the predetermined limit voltage U.sub.lim is selected in such a way that there is a short circuit in the power semiconductor switch 20 when the differential voltage U.sub.diff reaches or exceeds the predetermined limit voltage U.sub.lim.

[0062] The clamping transistor 16 is electrically connected to the output of the comparator circuit 14 and the current source 12. In this case, the clamping transistor 16 prevents charging of an input filter of the device 10 by means of a pull-up resistor of the current source 12 in a switched-off state.

[0063] In addition, output circuitry 17 is electrically connected to the output of the comparator circuit 14. The output circuitry is connected to ground (GND).

[0064] The functionality illustrated in the basic circuit diagram of the device 10 can also be implemented in a (single) integrated circuit (IC) or completely in a discrete (analog) circuit.

[0065] FIG. 3 schematically illustrates a special embodiment of the device 10 from FIG. 2. Only differences or special configurations of the device 10 in FIG. 3 in relation to the device from FIG. 2 will be explained.

[0066] The decoupling diode 11 is electrically connected with its anode via a pull-up resistor 19 to the current source 12 (more precisely to a collector terminal of a first PNP transistor 12.4 of the current source 12).

[0067] The current source 12 comprises a second resistor 12.1 and a fourth resistor 12.3, which are electrically connected to the supply current source of the power semiconductor 20 which provides the supply voltage U.sub.VDD. In addition, the current source comprises a third resistor 12.2, which is connected electrically in series with the first resistor 12.1. In addition, the current source 12 comprises the first PNP transistor 12.4, wherein a bulk terminal of the first PNP transistor 12.4 is electrically connected between the first resistor 12.1 and the second resistor 12.2, an emitter terminal of the first PNP transistor 12.4 is electrically connected to the third resistor 12.3, and the collector terminal of the first PNP transistor 12.4 is electrically connected, via the pull-up resistor 19, to the anode of the decoupling diode 11. The collector terminal of the first PNP transistor 12.4 is additionally electrically connected to a third capacitor 18, wherein the third capacitor 18 is additionally connected to ground (GND).

[0068] The reference voltage source 13 comprises a Zener diode 13.1 and a parallel circuit comprising a first resistor 13.2 and a first capacitor 13.3. The Zener diode is electrically connected (with its cathode) to the supply current source of the power semiconductor switch 20. In addition, the Zener diode is electrically connected (with its anode) to the parallel circuit. The first resistor 13.2 and the first capacitor 13.3 of the parallel circuit are additionally connected to ground (GND). The Zener diode 13.1 is electrically connected with its anode additionally to the comparator circuit 14 (more precisely to an emitter terminal of an NPN transistor 14.5 and to an anode of a first diode 14.6 of the comparator circuit 14).

[0069] The comparator circuit 14 comprises a second PNP transistor 14.1, which is electrically connected with its emitter terminal to the supply current source of the power semiconductor switch 20, with its collector terminal to a fifth resistor 14.2 of the comparator circuit 14 and with its bulk terminal to a sixth resistor 14.3 of the comparator circuit 14. In addition, the comparator circuit 14 comprises the first NPN transistor 14.5, which is electrically connected with its collector terminal, via the sixth resistor 14.3, to the bulk terminal of the second PNP transistor. In addition, the collector terminal of the first NPN transistor 14.5 is electrically connected, via a seventh resistor 14.4 of the comparator circuit 14, to the supply current source of the power semiconductor switch 20. The emitter terminal of the first NPN transistor 14.5 is electrically connected to the anode of the Zener diode 13.1 of the reference voltage source 13, the anode of the first diode 14.6 of the comparator circuit 14 and the third resistor 12.2 of the current source 12. A bulk terminal of the first NPN transistor 14.5 and a cathode of the first diode 14.6 are electrically connected to a cathode of a second diode 14.8 of the comparator circuit 14 and, via an eighth resistor 14.7 of the comparator circuit, to the collector terminal of the first PNP transistor 12.4 of the current source or additionally, via the pull-up resistor 19, to the anode of the decoupling diode 11. The collector terminal of the second PNP transistor is electrically connected, via the fifth resistor 14.2, to the evaluation electronics 15.

[0070] The clamping transistor 16 is an n-channel insulated-gate field-effect transistor which is connected with its gate terminal to ground (GND), and which is electrically connected, on one side, with its source terminal and its gate terminal to the collector terminal of the second PNP transistor 14.1 of the comparator circuit 14 and the evaluation electronics 15 and, on the other side, with its drain terminal to the collector terminal of the first PNP transistor 12.4 of the current source 12 and, via the pull-up resistor 19, to the anode of the decoupling diode 11.

[0071] The output circuitry 17 in this case comprises a parallel circuit comprising a ninth resistor 17.1 and a second capacitor 17.2. The ninth resistor 17.1 and the capacitor are electrically connected on one side to ground (GND) and on the other side to the collector terminal of the second PNP transistor 14.1 via the fifth resistor 14.2, the evaluation electronics 15 and the source terminal and gate terminal of the n-channel insulated-gate field-effect transistor 16.

[0072] Although specific embodiments have been illustrated and described here, it is clear to a person skilled in the art that there is a multiplicity of alternatives and/or equivalent implementations. It should be appreciated that the exemplary configurations or embodiments are merely examples and are not intended to restrict the scope, the applicability or the configuration in any way. Rather, the above summary and detailed description will provide a person skilled in the art with sufficient instructions for implementing at least one preferred embodiment, wherein it goes without saying that various changes to the function and arrangement of the elements which are described in an exemplary configuration do not result from the application field set forth in the attached claims and their legal equivalents. In general, this application is intended to cover all adaptations and variations of the specific embodiments discussed here.

[0073] In the detailed description above, various features have been summarized in one or more examples in order to keep the disclosure concise. It goes without saying that the above description is intended to be illustrative and not restrictive. It is intended to cover all alternatives, amendments and equivalents which can be contained within the scope of the invention. Many other examples will become obvious to a person skilled in the art when studying the above disclosure.

[0074] In order to enable comprehensive understanding of the invention, a specific nomenclature is used which has been used in the above disclosure. However, it will become apparent to a person skilled in the art in the light of the specification contained therein that the specific details are not required in order to apply the invention. Thus, the above descriptions of specific embodiments of the present invention are illustrated for illustrative and descriptive purposes. They are not intended to be exhaustive or to restrict the invention to the above-disclosed precise embodiments; many modifications and variations in respect of the abovementioned teachings are obviously possible.

[0075] The embodiments have been selected and described in order to best clarify the principles of the invention and their practical applications and in order to therefore give others skilled in the art the possibility of best applying the invention and various embodiments with various modifications as appears suitable for the respective application. Throughout the specification, the terms “including” and “in the case of which” are used as equivalents of the respective terms “comprising” and “in which”. Furthermore, the terms “first”, “second”, “third” etc. are merely used as a designation and are not intended to place numerical demands on the objects or prescribe a specific sequence. In connection with the above description and the claims, the conjunction “or” should be understood to be inclusive (“and/or”) and not exclusive (“either . . . or”).