DML driver

Abstract

A CMOS inverter circuit is provided as a circuit to modulate a current flowing into a laser diode on the basis of a digital signal. An amplitude of a current flowing in a PMOSFET in the CMOS inverter circuit is made to contribute to an amplitude of the current flowing into the laser diode, to reduce an input amplitude.

Claims

1. A DML driver comprising: a CMOS inverter circuit modulating current flowing into a laser diode on the basis of a digital signal, wherein a current flowing into the laser diode is modulated on the basis of a level change in a voltage input as the digital signal; a signal input terminal where the digital signal is input; a first voltage application terminal where a first DC voltage is applied; a second voltage application terminal where a second DC voltage is applied, the second DC voltage being lower than the first DC voltage; and wherein the CMOS inverter circuit comprises: a first PMOSFET; and a first NMOSFET, wherein a gate of the first PMOSFET and a gate of the first NMOSFET are connected to the signal input terminal, a source of the first PMOSFET is connected to the first voltage application terminal, a source of the first NMOSFET is connected to the second voltage application terminal, and a drain of the first PMOSFET and a drain of the first NMOSFET are connected to the laser diode.

2. The DML driver according to claim 1, further comprising: a third voltage application terminal where a third DC voltage is applied; a second PMOSFET having: a gate connected to the third voltage application terminal; a source connected to a first connection line, the first connection line is connected to the source of the first PMOSFET and the first voltage application terminal; and a drain connected to an anode of the laser diode; and a first capacitor connected between a grounded line and a second connection line, the second connection line is connected to the third voltage application terminal and the gate of the second PMOSFET.

3. The DML driver according to claim 1, further comprising: a series-connected circuit of a first resistor and a second capacitor, the series-connected circuit linking a third connection line to a fourth connection line, the third connection line is connected to the drain of the first PMOSFET, the drain of the first NMOSFET, and an anode of the laser diode, and the fourth connection line is connected to the source of the first PMOSFET and the first voltage application terminal.

4. The DML driver according to claim 1, further comprising: a fourth voltage application terminal where a fourth DC voltage is applied; a fourth resistor connected between the fourth voltage application terminal and a fifth connection line, the fifth connection line is connected to the gate of the first PMOSFET, the gate of the first NMOSFET, and the signal input terminal; and a fifth capacitor connected between a grounded line and a sixth connection line, the sixth connection line is connected to the fourth voltage application terminal and the fourth resistor.

5. The DML driver according to claim 1, comprising: a second resistor connected between the source of the first PMOSFET and the first voltage application terminal; a third capacitor connected between a grounded line and a seventh connection line, the seventh connection line is connected to the first voltage application terminal and the second resistor; a third resistor connected between the source of the first NMOSFET and the second voltage application terminal; and a fourth capacitor connected between a grounded line and a eighth connection line, the eighth connection line is connected to the second voltage application terminal and the third resistor.

6. The DML driver according to claim 5, comprising: a sixth capacitor that is connected to the third resistor in parallel.

7. The DML driver according to claim 1, further comprising: a first signal input terminal where a first digital signal is input; a second signal input terminal where a second digital signal is input; a first voltage application terminal where a first DC voltage is applied; a second voltage application terminal where a second DC voltage is applied, the second DC voltage being lower than the first DC voltage; and wherein the CMOS inverter circuit comprises: a first PMOSFET; a second PMOSFET; a first NMOSFET; and a second NMOSFET, wherein a gate of the first PMOSFET and a gate of the first NMOSFET are connected to the first signal input terminal, a gate of the second PMOSFET and a gate of the second NMOSFET are connected to the second signal input terminal, a source of the first PMOSFET and a source of the second PMOSFET are connected to the first voltage application terminal, a source of the first NMOSFET and a source of the second NMOSFET are connected to the second voltage application terminal, and a drain of the first PMOSFET, a drain of the first NMOSFET, a drain of the second PMOSFET, and a drain of the second NMOSFET are connected to an anode of the laser diode.

8. A DML driver comprising: a first signal input terminal where a first digital signal is input; a second signal input terminal where a second digital signal is input; a first voltage application terminal where a first DC voltage is applied; a second voltage application terminal where a second DC voltage is applied, the second DC voltage being lower than the first DC voltage; and a CMOS inverter circuit comprising: a first PMOSFET; a second PMOSFET; a first NMOSFET; and a second NMOSFET, wherein a gate of the first PMOSFET and a gate of the first NMOSFET are connected to the first signal input terminal, a gate of the second PMOSFET and a gate of the second NMOSFET are connected to the second signal input terminal, a source of the first PMOSFET and a source of the second PMOSFET are connected to the first voltage application terminal, a source of the first NMOSFET and a source of the second NMOSFET are connected to the second voltage application terminal, and a drain of the first PMOSFET, a drain of the first NMOSFET, a drain of the second PMOSFET, and a drain of the second NMOSFET are connected to an anode of a laser diode.

9. The DML driver according to claim 8, wherein the CMOS inverter circuit modulates current flowing into the laser diode on the basis of a level change in a voltage input as a digital signal.

10. A DML driver comprising: a signal input terminal where a digital signal is input; a first voltage application terminal where a first DC voltage is applied; a second voltage application terminal where a second DC voltage is applied, the second DC voltage being lower than the first DC voltage; and a CMOS inverter circuit comprising: a first PMOSFET; and a first NMOSFET, wherein a gate of the first PMOSFET and a gate of the first NMOSFET are connected to the signal input terminal, a source of the first PMOSFET is connected to the first voltage application terminal, a source of the first NMOSFET is connected to the second voltage application terminal, and a drain of the first PMOSFET and a drain of the first NMOSFET are connected to an anode of a laser diode.

11. The DML driver according to claim 10, wherein the CMOS inverter circuit modulates current flowing into the laser diode on the basis of a level change in a voltage input as the digital signal.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a diagram showing the structure of a principal part of a transmitter front-end using a DML driver according to Embodiment 1 of the present invention.

(2) FIG. 2 is a diagram showing the structure of a principal part of a transmitter front-end using a DML driver according to Embodiment 2 of the present invention.

(3) FIG. 3 is a diagram illustrating an example of further providing a fifth circuit for the structure shown in FIG. 2.

(4) FIG. 4 is a diagram showing the structure of a principal part of a transmitter front-end using a DML driver according to Embodiment 3 of the present invention.

(5) FIG. 5 is a diagram showing the structure of a principal part of a transmitter front-end using a DML driver according to Embodiment 4 of the present invention.

(6) FIG. 6 is a diagram illustrating an example of further providing sixth circuits for the structure shown in FIG. 5.

(7) FIG. 7 is a diagram showing a schematic structure of a transmission system of “100 GBase-LR4/ER4”.

(8) FIG. 8 is a diagram illustrating an example of the structure of a principal part of a transmitter front-end using a shunt-type LD driver.

(9) FIG. 9 are explanatory views of the OFF-operation of the transmitter front-end shown in FIG. 8.

(10) FIG. 10 are explanatory views of the ON-operation of the transmitter front-end shown in FIG. 8.

(11) FIG. 11 is a diagram illustrating a concrete example of the transmitter front-end shown in FIG. 8.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

(12) Hereinafter the embodiments of the present invention will be described in detail based on the drawings.

Embodiment 1

(13) FIG. 1 shows the structure of a principal part of a transmitter front-end using a DML driver according to Embodiment 1 of the present invention.

(14) In the following description, the transmitter front-end 100 of the present embodiment will be referred to as a transmitter front-end 100A, and the conventional transmitter front-end 100 shown in FIG. 11 will be referred to as a transmitter front-end 100X for distinguish the conventional transmitter front-end 100 shown in FIG. 11. Also, the LD driver 101 of the present embodiment will be referred to as a LD driver 101A, and the conventional LD driver 101 will be referred to as a LD driver 101X. Also, the LD drivers 101A and 101X will be referred to as DML drivers 101A and 101X.

(15) In the transmitter front-end 100A shown in FIG. 1, the DML driver 101A includes a CMOS inverter circuit INV as a circuit to modulate a current flowing into a laser diode LD on the basis of a digital signal D.sub.o (level change of an input voltage Vin). The DML driver 101A also includes a signal input terminal S0 where the digital signal D.sub.o is input, a first voltage application terminal P1 where a first DC voltage V.sub.SSP is applied, and a second voltage application terminal P2 where a second DC voltage V.sub.SSN that is lower than the first DC voltage V.sub.SSP is applied.

(16) The CMOS inverter circuit INV includes a PMOSFET⋅M.sub.1 and a NMOSFET⋅M.sub.2. A gate of the PMOSFET⋅M.sub.1 and a gate of the NMOSFET⋅M.sub.2 are connected to the signal input terminal S0. A source of the PMOSFET⋅M.sub.1 is connected to the first voltage application terminal P1, a source of the NMOSFET⋅M.sub.2 is connected to the second voltage application terminal P2, and a drain of the PMOSFET⋅M.sub.1 and a drain of the NMOSFET⋅M.sub.2 are connected to an anode of the laser diode LD.

(17) In FIG. 1, I.sub.DRVP is a current flowing between the source and drain of the PMOSFET⋅M.sub.1, I.sub.DRVN is a current flowing between the drain and source of the NMOSFET⋅M.sub.2, and I.sub.LD is a current flowing into the laser diode LD (LD driving current). The relationship between the current I.sub.DRVP flowing in the PMOSFET⋅M.sub.1, the current I.sub.DRVN flowing in the NMOSFET⋅M.sub.2, and the current I.sub.LD flowing into the laser diode LD is: I.sub.LD=I.sub.DRVP−I.sub.DRVN.

(18) In the drawing, thin arrows represent the currents I.sub.DRVP, I.sub.DRVN, and I.sub.LD when the digital signal D.sub.o to the CMOS inverter circuit INV is at level “H” (input voltage Vin is at level “H”), and thick arrows represent the currents I.sub.DRVP, I.sub.DRVN, and I.sub.LD when the digital signal D.sub.o to the DML driver 101A is at level “L” (input voltage Vin is at level “L”).

(19) When the digital signal D.sub.o is at level “H”, the PMOSFET⋅M.sub.1 is in an off state and the NMOSFET⋅M.sub.2 is in an on state, and the current I.sub.DRVP flowing in the PMOSFET⋅M.sub.1 decreases and the current I.sub.DRVN flowing in the NMOSFET⋅M.sub.2 increases, which leads to the current I.sub.LD flowing into the laser diode LD at level “L”.

(20) When the digital signal D.sub.o is at level “L”, the PMOSFET⋅M.sub.1 is in an on state and the NMOSFET⋅M.sub.2 is in an off state, and the current I.sub.DRVP flowing in the PMOSFET⋅M.sub.1 increases and the current I.sub.DRVN flowing in the NMOSFET⋅M.sub.2 decreases, which leads to the current I.sub.LD flowing into the laser diode LD at level “H”.

(21) The NMOSFET⋅M.sub.2 turns on to reduce the current I.sub.LD flowing into the laser diode LD, and the NMOSFET⋅M.sub.2 turns off to increase the current I.sub.LD flowing into the laser diode LD. Thus, for the laser diode LD, the PMOSFET⋅M.sub.1 and the NMOSFET⋅M.sub.2 are different from each other in state according to the state of the input voltage Vin, but function the same.

(22) Thus, when the amplitude of the current I.sub.DRVP flowing in the PMOSFET⋅M.sub.1 is defined as I.sub.AMPP, and the amplitude of the current I.sub.DRVN flowing in the NMOSFET⋅M.sub.2 is defined as I.sub.AMPN, the amplitude I.sub.AMP of the current I.sub.LD flowing into the laser diode LD is I.sub.AMPP+I.sub.AMPN, that is, the total of the amplitude I.sub.AMPP of the current I.sub.DRVP flowing in the PMOSFET⋅M.sub.1, and the amplitude I.sub.AMPN of the current I.sub.DRVN flowing in the NMOSFET⋅M.sub.2 is the amplitude I.sub.AMP of the current I.sub.LD flowing into the laser diode LD.

(23) Here, the DML driver 101A will be compared with the conventional DML driver 101X shown in FIG. 11. When the conventional DML driver 101X is used, a current I.sub.DD corresponding to the current I.sub.DRVP flowing in the PMOSFET⋅M.sub.1 takes a fixed value, and only the current I.sub.DD contributes to the amplitude I.sub.AMP of the current I.sub.LD flowing into the laser diode LD. In contrast, when the same amplitude I.sub.AMP is to be obtained, in the DML driver 101A of the present embodiment, the amplitude I.sub.AMPP of I.sub.DRVP flowing in the PMOSFET⋅M.sub.1 contributes to the amplitude I.sub.AMP of the current I.sub.LD flowing into the laser diode LD, which makes it possible to reduce the amplitude V.sub.AMP of the input voltage Vin.

(24) As can be seen from the foregoing description, using the DML driver 101A of the present embodiment can lead to the input voltage Vin of a lower amplitude V.sub.AMP (input amplitude) than using the conventional DML driver 101X, and obtainment of the amplitude I.sub.AMP of the LD driving current I.sub.LD same as that of the conventional DML driver 101X. This makes efficient modulation possible. The DML driver 101A of the present embodiment does not need any separate device such as “bias T”.

Embodiment 2

(25) Next, FIG. 2 shows the structure of a principal part of a transmitter front-end using a DML driver according to Embodiment 2 of the present invention. In this transmitter front-end 100B of Embodiment 2, a first circuit 1, a second circuit 2, third circuits 3 (3-1, 3-2), and a fourth circuit 4 are added to a DML driver 101B as a new circuit structure.

(26) The DML driver 101B also includes a third voltage application terminal P3 where a third DC voltage V.sub.CNT is applied, and a fourth voltage application terminal P4 where a fourth DC voltage VD.sub.obiaS is applied, in addition to the first voltage application terminal P1 where the first DC voltage V.sub.SSP is applied, and the second voltage application terminal P2 where the second DC voltage V.sub.SSN that is lower than the first DC voltage V.sub.SSP is applied.

(27) In the DML driver 101B, the first circuit 1 is configured by a PMOSFET⋅M.sub.3 to supply a bias current to the laser diode LD, and a capacitor C1 (decoupling capacitor). Adding this first circuit 1 makes it possible to operate the DML driver 101B in the linear regime.

(28) In the first circuit 1, a gate of the PMOSFET⋅M.sub.3 is connected to the third voltage application terminal P3, a source thereof is connected to a connection line L1 connecting the source of the PMOSFET⋅M.sub.1 and the first voltage application terminal P1, and a drain thereof is connected to the anode of the laser diode LD. The capacitor C1 links a connection line L2 connecting the third voltage application terminal P3 and the gate of the PMOSFET⋅M.sub.3, and a grounded line.

(29) The PMOSFET⋅M.sub.3 of the first circuit 1 is turned on, which can lead to the supply of the bias current to the laser diode LD. A bias voltage of D.sub.o is increased to operate the NMOSFET⋅M.sub.2 in the linear regime, which can lead to the operation of the DML driver 101B in the linear regime. The bias voltage of D.sub.o is increased, which leads to the PMOSFET⋅M.sub.1 in the off state, but the bias current from the PMOSFET⋅M.sub.3 of the first circuit 1 to the laser diode LD is supplied. Adjustment of V.sub.CNT can adjust the linearity of the driver.

(30) The second circuit 2 is configured by a resistor R1 and a capacitor C2 which are connected in series, to function as a RC filter to suppress overshoots in the light output waveform. In this second circuit 2, a series-connected circuit of the resistor R1 and the capacitor C2 links a connection line L3 connecting the drain of the PMOSFET⋅M.sub.1, the drain of the NMOSFET⋅M.sub.2, and the anode of the laser diode LD, and the connection line L1 connecting the source of the PMOSFET⋅M.sub.1 and the first voltage application terminal P1. When the PMOSFET⋅M.sub.1 turns on, the current to the laser diode LD increases, and an overshoot is seen in the light output waveform of the laser diode LD. Addition of the second circuit 2 for preventing eye patterns of the light output from deteriorating due to the influence of overshoots can suppress overshoots by the effect of the RC filter.

(31) The third circuits 3 (3-1, 3-2) are configured by a resistor R2 connected between the source of the PMOSFET⋅M.sub.1 and the first voltage application terminal P1, a capacitor C3 connected between the grounded line and the connection line L1 connecting the first voltage application terminal P1 and the resistor R2, a resistor R3 connected between the source of the NMOSFET⋅M.sub.2 and the second voltage application terminal P2, and a capacitor C4 connected between the grounded line and a connection line L4 connecting the second voltage application terminal P2 and the resistor R3.sub.1. The third circuits 3 (3-1, 3-2) have the function of suppressing resonances in a power line, and can suppress an impedance change of a power source due to LC resonance of a parasitic capacitance and a parasitic inductor component on the power line.

(32) The fourth circuit 4 is an input bias supplying part to the DML driver 101B, and is configured by a resistor R4 that links a connection line L5 connecting the gate of the PMOSFET⋅M.sub.1, the gate of the NMOSFET⋅M.sub.2 and the signal input terminal S0, and the fourth voltage application terminal P4, and a capacitor C5 that links a connection line L6 connecting the fourth voltage application terminal P4 and the resistor R4, and a grounded line. The fourth circuit 4 matches the resistor R4 to the impedance of an input line, to also play a role as an input matching part.

(33) While not shown in FIG. 2, connection of a capacitor C6 to the resistor R3 in parallel as a fifth circuit 5 as shown in FIG. 3 can improve frequency characteristics of the DML driver 101B.

Embodiment 3

(34) FIG. 4 shows the structure of a principal part of a transmitter front-end (PAM4 transmitter front-end) using a DML driver according to Embodiment 3 of the present invention. In this transmitter front-end 100C of Embodiment 3, the structure of the CMOS inverter circuit INV in the transmitter front-end 100A shown in FIG. 1 is changed to the structure of bilaterally arranging two CMOS inverter circuits INV symmetrically across the laser diode LD.

(35) In FIG. 4, branch numbers “1”, “2” are respectively added to corresponding signs of the structures corresponding to those in the DML driver 101A in the transmitter front-end 100A, to represent the corresponding structures. S0 and S1 are each signal input terminals of LSB and MSB.

(36) In this transmitter front-end 100C, the CMOS inverter circuit INV includes a PMOSFET⋅M.sub.11, a PMOSFET⋅M.sub.12, a NMOSFET⋅M.sub.21, and a NMOSFET⋅M.sub.22. A gate of the PMOSFET⋅M.sub.11 and a gate of the NMOSFET⋅M.sub.21 are connected to the signal input terminal S0, and a gate of the PMOSFET⋅M.sub.12 and a gate of the NMOSFET⋅M.sub.22 are connected to the signal input terminal S1. A source of the PMOSFET, M.sub.11 and a source of the PMOSFET⋅M.sub.12 are connected to the first voltage application terminal P1, and a source of the NMOSFET⋅M.sub.21 and a source of the NMOSFET⋅M.sub.22 are connected to the second voltage application terminal P2. A drain of the PMOSFET⋅M.sub.11 and a drain of the NMOSFET⋅M.sub.21, and a drain of the PMOSFET⋅M.sub.12 and a drain of the NMOSFET⋅M.sub.22 are connected to the anode of the laser diode LD.

(37) In this transmitter front-end 100C, the data of “0” and “1” as digital signals D.sub.o and D.sub.1 is given to the signal input terminals S0 and S1 respectively, which makes it possible to output PAM4 optical signals from the laser diode LD.

Embodiment 4

(38) FIG. 5 shows the structure of a principal part of a transmitter front-end (PAM4 transmitter front-end) using a DML driver according to Embodiment 4 of the present invention. In this transmitter front-end 100D of Embodiment 4, the first circuit 1 is excluded from the transmitter front-end 100B shown in FIG. 2, and a set of the rest of the circuit structure is further added thereto.

(39) In FIG. 5 as well, branch numbers “1”, “2” are respectively added to corresponding signs of the structures corresponding to those in the DML driver 101B in the transmitter front-end 100B, to represent the corresponding structures. In this transmitter front-end 100D as well, the data of “0” and “1” as the digital signals D.sub.o and D.sub.1 is given to the signal input terminals S0 and S1 respectively, which makes it possible to output PAM4 optical signals from the laser diode LD.

(40) As shown in FIG. 6 as sixth circuits 6 (6-1, 6-2), connection of a capacitor C7.sub.1 to a source resistor R3.sub.1 of the NMOSFFET⋅M.sub.21, which is on the side of giving the digital signal D.sub.o, in parallel, and connection of a capacitor C7.sub.2 to a source resistor R3.sub.2 of the NMOSFFET⋅M.sub.22, which is on the side of giving the digital signal D.sub.1, in parallel can improve frequency characteristics of the driver.

Extension of Embodiments

(41) The present invention has been described as the foregoing with reference to the embodiments. The present invention is not limited to the foregoing embodiments. Various modifications that can be understood by the person skilled in the art may be performed on the structures and details of the present invention within the scope of the technical concept of the present invention.

REFERENCE SIGNS LIST

(42) 100 Transmitter front-end 101 DML driver LD Laser diode INV CMOS inverter circuit M.sub.1, M.sub.3 PMOSFET M.sub.2 NMOSFET S0, S1 Signal input terminal P1 First voltage application terminal P2 Second voltage application terminal P3 Third voltage application terminal P4 Fourth voltage application terminal 1 First circuit 2 Second circuit 3 Third circuit 4 Fourth circuit 5 Fifth circuit 6 Sixth circuit L1 to L6 Connection line R1 to R4 Resistor C1 to C6 Capacitor