OPTOELECTRONIC SEMICONDUCTOR CHIP AND METHOD FOR PRODUCING AN OPTOELECTRONIC SEMICONDUCTOR CHIP

Abstract

The optoelectronic semiconductor chip may include a composite having a front face, a first semiconductor layer sequence and a second semiconductor layer sequence between the front face and the first semiconductor layer sequence, a first and a second contact element on a side of the composite opposite the front face, and a first and a second through-connection. The first and second semiconductor layer sequences each include an active layer for generating or absorbing electromagnetic radiation. The first contact element and the first through-connection are configured to electrically contact the first semiconductor layer sequence, and the second contact element and the second through-connection are configured to electrically contact the second semiconductor layer sequence. The first through-connection is guided through the active layer of the first semiconductor layer sequence and the second through-connection is guided through the active layer of the second semiconductor layer sequence.

Claims

1. An optoelectronic semiconductor chip comprising: a composite having a front face, a first semiconductor layer sequence and a second semiconductor layer sequence between the front face and the first semiconductor layer sequence; a first contact element and a second contact element on a side of the composite opposite the front face; a first through-connection and a second through-connection, each extending into the composite from the side opposite the front face; wherein: the first semiconductor layer sequence and the second semiconductor layer sequence each include an active layer for generating or absorbing configured to generate or absorb electromagnetic radiation; the first contact element and the first through-connection are configured to electrically contact the first semiconductor layer sequence; the second contact element and the second through-connection are configured to electrically contact the second semiconductor layer sequence; the first through-connection is guided through the active layer of the first semiconductor layer sequence and the second through-connection is guided through the active layer of the second semiconductor layer sequence; and the first contact element and the second contact element and the first through-connection and the second through-connection are arranged such that the first semiconductor layer sequence and the second semiconductor layer sequence are electrically connected in parallel, such that charge carriers flow simultaneously through both semiconductor layer sequences in operation; wherein charge carriers flowing through the first semiconductor layer sequence do not enter the second semiconductor layer sequence and vice versa.

2. The semiconductor chip according to claim 1, wherein the second contact element is guided through the first semiconductor layer sequence up to the second semiconductor layer sequence.

3. The semiconductor chip according to claim 1, wherein the first contact element and the second contact element are electrically connected to one another and are at the same potential in the intended operation; the first through-connection and the second through-connection are electrically conductively connected to one another and are at the same potential in the intended operation.

4. The semiconductor chip according to claim 1, wherein the first contact element and the second contact element are can be contacted independently of each other; and/or the first through-connection and the second through-connection are contacted independently of each other.

5. The semiconductor chip according to claim 1, wherein the active layers are configured to emit radiation of different wavelengths.

6. The semiconductor chip according to claim 1, wherein the second through-connection is guided through the second contact element and is electrically insulated from the second contact element.

7. The semiconductor chip according to claim 1, wherein: the second semiconductor layer sequence is formed contiguously; the first semiconductor layer sequence comprises a plurality of laterally spaced semiconductor blocks; the semiconductor blocks are distributed along the second semiconductor layer sequence; the second contact element extends in the region between the semiconductor blocks up to the second semiconductor layer sequence.

8. The semiconductor chip according to claim 1, wherein the semiconductor chip comprises a plurality of the first through-connection and/or the second through-connection.

9. The semiconductor chip according to claim 7, wherein each semiconductor block of the first semiconductor layer sequence is uniquely associated with at least one first through-connection.

10. The semiconductor chip according to claim 1, wherein: the first semiconductor layer sequence and the second semiconductor layer sequence are each formed contiguously; the first semiconductor layer sequence and the second semiconductor layer sequence each extend over at least 80% of the lateral extent of the semiconductor chip.

11. A method for producing a semiconductor chip, wherein the method comprises: forming a composite comprising a first semiconductor layer sequence including an active layer and a second semiconductor layer sequence including an active layer, the second semiconductor layer sequence being arranged between a front face of the composite and the first semiconductor layer sequence, forming a first contact element, forming a first through-connection; wherein: the first through-connection is guided through the active layer of the first semiconductor layer sequence; the first contact element and the first through-connection are configured to electrically contact the first semiconductor layer sequence; forming a second contact element on a side of the composite opposite the front face; forming a second through-connection; wherein: the second contact element and the second through-connection are configured to electrically contact the second semiconductor layer sequence; the second through-connection is guided through the active layer of the second semiconductor layer sequence; the first contact element and the second contact element and the first through-connection and the second through-connection are arranged such that the first semiconductor layer sequence and the second semiconductor layer sequence are electrically connected in parallel, such that charge carriers flow simultaneously through both semiconductor layer sequences in operation; charge carriers flowing through the first semiconductor layer sequence do not enter the second semiconductor layer sequence and vice versa; and the first semiconductor layer sequence and the second semiconductor layer sequence are electrically insulated from each other.

12. The method according to claim 11, wherein in forming the composition comprises: providing a plurality of semiconductor blocks each having an active layer; depositing the semiconductor blocks as separate elements spaced apart from each other on the second semiconductor layer sequence and together form the first semiconductor layer sequence.

13. The method according to claim 12, wherein forming the first through-connection occurs before forming the composite.

14. The method according to claim 11, wherein forming the composite comprises depositing the first semiconductor layer sequence as a contiguous semiconductor layer sequence on the second semiconductor layer sequence; and , further comprising segmenting the first semiconductor layer sequence into a plurality of semiconductor blocks

15. The method according to claim 11, wherein forming the composite comprises bonding the first semiconductor layer sequence and the second semiconductor layer sequence on top of each other.

16. The method according to claim 11, wherein forming the composite comprises gluing the first semiconductor layer sequence and the second semiconductor layer sequence on top of each other.

17. The method according to claim 11, wherein forming the composite comprises epitaxially growing the first semiconductor layer sequence and the second semiconductor layer sequence on top of each other.

18. An optoelectronic semiconductor chip comprising: a composite having a front face, a first semiconductor layer sequence and a second semiconductor layer sequence between the front face and the first semiconductor layer sequence; a first contact element and a second contact element on a side of the composite opposite the front face; a first through-connection and a second through-connection, each extending into the composite from the side opposite the front face; wherein: the first and the second semiconductor layer sequence each include an active layer configured to generate or absorb electromagnetic radiation; the first contact element and the first through-connection are configured to electrically contact the first semiconductor layer sequence; the second contact element and the second through-connection are configured to electrically contact the second semiconductor layer sequence; the first through-connection is guided through the active layer of the first semiconductor layer sequence and the second through-connection is guided through the active layer of the second semiconductor layer sequence; the first contact element and the second contact element and the first through-connection and the second through-connection are arranged such that the first semiconductor layer sequence and the second semiconductor layer sequence are electrically connected in parallel, such that charge carriers flow simultaneously through both semiconductor layer sequences in operation, charge carriers flowing through the first semiconductor layer sequence do not enter the second semiconductor layer sequence and vice versa; and the first semiconductor layer sequence and the second semiconductor layer sequence are electrically insulated from each other.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0062] In the figures:

[0063] FIGS. 1A to 1C show various views of a first exemplary embodiment of the optoelectronic semiconductor chip,

[0064] FIGS. 2 to 4 show cross-sectional views of further exemplary embodiments of the optoelectronic semiconductor chip,

[0065] FIGS. 5A and 5B show another exemplary embodiment of the optoelectronic semiconductor chip in various views,

[0066] FIGS. 6A to 7E show various positions in two exemplary embodiments of the method for producing an optoelectronic semiconductor chip.

[0067] In the detailed description that follows, reference will be made to the attached drawings, which form part of this description and in which specific exemplary embodiments may be realized are shown for illustration purposes. Because components of exemplary embodiments can be positioned in a number of different orientations, the directional terminology is used for illustration purposes only, and is in no way restrictive. It goes without saying that other exemplary embodiments can be used and structural or logical changes can be made without departing from the scope of protection. It goes without saying that the features of the various exemplary embodiments described herein can be combined with one another, unless specifically stated otherwise. The following detailed description is therefore not to be interpreted in a restrictive sense. In the figures, identical or similar elements are labeled with identical reference numerals, where this is appropriate.

DETAILED DESCRIPTION

[0068] FIG. 1A shows a first exemplary embodiment of the optoelectronic semiconductor chip in a cross-sectional view. The semiconductor chip is, for example, an LED chip. The optoelectronic semiconductor chip comprises a composite 1 having a front face 10 and a rear face 13 opposite the front face 10. In particular, the front face 10 forms a radiation exit surface of the semiconductor chip, via which a large part of the generated radiation is coupled out during intended operation of the semiconductor chip.

[0069] The composite 1 comprises a first semiconductor layer sequence 11 and a second semiconductor layer sequence 12, the first semiconductor layer sequence 11 being arranged downstream of the second semiconductor layer sequence 12 in the direction away from the front face 10. Between the first semiconductor layer sequence 11 and the second semiconductor layer sequence 12, a connection layer 14 is provided which mechanically connects the two semiconductor layer sequences 11, 12 to each other. The connection layer 14 may be electrically insulating. In the present case, the connection layer 14 is, for example, an adhesive layer, for example made of a silicone adhesive.

[0070] The first semiconductor layer sequence 11 comprises a first layer 11a of semiconductor material, a second layer 11c of semiconductor material, and an active layer 11b between the first layer 11a and the second layer 11c. The second semiconductor layer sequence 12 comprises a first layer 12a of semiconductor material, a second layer 12 of semiconductor material, and an active layer 12b therebetween. The first layers 11a, 12a are doped opposite to the second layers 11c, 12c. For example, the two first layers 11a, 12a are p-doped, and the two second layers 11c, 12c are n-doped, or vice versa.

[0071] The optoelectronic semiconductor chip comprises a first contact element 21 and a second contact element 22 at the rear face 13 of the composite 1 opposite the front face 10. In the present case, the two contact elements 21, 22 are formed contiguously, even integrally with each other. For example, the two contact elements 21, 22 are formed of a metal, such as silver.

[0072] The first contact element 21 adjoins and contacts the first layer 11a of the first semiconductor layer sequence 11. The second contact element 22 includes regions guided through the first semiconductor layer sequence 11 up to the first layer 12a of the second semiconductor layer sequence 12. In these regions, the second contact element 22 contacts the first layer 12a. The second contact element 22 is electrically insulated from the first semiconductor layer sequence 11 by an insulation material 5 in these regions. The insulation material 5 is, for example, SiO.sub.2 or SiN. The insulation material 5 between the second contact element 22 and the first semiconductor layer sequence 11 may also be a dielectric mirror.

[0073] Furthermore, the semiconductor chip comprises first through-connections 31 extending from the rear face 13 into the composite 1. The first through-connections 31 penetrate the first layer 11a as well as the active layer 11b of the first semiconductor layer sequence 11 and terminate in the second layer 11c of the first semiconductor layer sequence 11, where the first through-connections 31 contact the second layer 11c. Thus, the first semiconductor layer sequence 11 is electrically contacted via the first contact element 21 and the first through-connections 31. The first through-connections 31 are insulated from the semiconductor layer sequence 11 by the insulation material 5 in the region of the first layer 11a and the active layer 11b.

[0074] In addition, second through-connections 32 are provided in the semiconductor chip, which each extend from the rear face 13 through the first semiconductor layer sequence 11 into the second semiconductor layer sequence 12, completely penetrating the first semiconductor layer sequence 11. The second through-connections 32 further penetrate the first layer 12a and the active layer 12b of the second semiconductor layer sequence 12 and terminate in the second layer 12c of the second semiconductor layer sequence 12. The second through-connections 32 are electrically insulated in the region of the first layer 12a and the active layer 12b of the second semiconductor layer sequence 12 by the insulation material 5.

[0075] In FIG. 1A, it can also be seen that the second through-connections 32 are guided through the regions of the second contact element 22, which in turn are guided through the first semiconductor layer sequence 11.

[0076] In the present exemplary embodiment, the first through-connections 31 and the second through-connections 32 are electrically conductively connected to each other and are at the same potential in the intended operation of the semiconductor chip. The same applies to the first and second contact elements 21, 22. The first and second through-connections include or consist, for example, of Al.

[0077] The semiconductor chip of FIG. 1A comprises a carrier 6, for example a plastic carrier. The carrier 6 supports the composite 1 and stabilizes it. Connection areas 7, 8 are provided on a side of the carrier 6 facing away from the composite 1. One connection area 7 is electrically conductively connected to the first contact element 21 and the second contact element 22. Another connection area 8 is electrically conductively connected to the first and second through-connections 31, 32. In the unassembled state of the semiconductor chip, the connection areas 7, 8 are exposed. The semiconductor chip of FIG. 1A is a surface-mountable semiconductor chip.

[0078] In FIG. 1B, the semiconductor chip of FIG. 1A is shown in perspective view. For clarity, the carrier 6 and the first 21 and second 22 contact elements are not shown. FIG. 1A is a sectional view along the dashed-dotted line of FIG. 1B.

[0079] In FIG. 1B, it can be seen that the second semiconductor layer sequence 12 is formed contiguously and the first semiconductor layer sequence 11 is formed of a plurality of semiconductor blocks 11d. The semiconductor blocks 11d are arranged along the second semiconductor layer sequence 12 and are spaced apart from each other in pairs. A grid of trenches spaces the semiconductor blocks 11d, with one semiconductor block located in each mesh of the grid. The second contact element 22, which is not shown, extends up to the second semiconductor layer sequence 12 in the region between each two adjacent semiconductor blocks 11d and fills the grid of trenches.

[0080] The second through-connections 32 are arranged in the region of the intersections of the grid lines. One of the first through-connections 31 is biuniquely associated with each of the semiconductor blocks 11d, the first through-connections 31 each extending through the associated semiconductor block 11d.

[0081] In FIG. 1C, the optoelectronic semiconductor chip of FIG. 1B is again shown without the carrier and the contact elements in a further perspective view. In addition, a section of the semiconductor chip is shown enlarged.

[0082] FIG. 2 shows a second exemplary embodiment of the semiconductor chip, again in a cross-sectional view. In contrast to the semiconductor chip of FIG. 1A, here the first contact element 21 and the second contact element 22 can be electrically contacted independently of each other. In particular, the first contact element 21 and the second contact element 22 are not formed contiguously in this case.

[0083] The first contact element 21 is electrically conductively connected to a connection area 7a on a rear face of the carrier 6. The second contact element 22 is electrically conductively connected to a connection area 7b, which is different from the connection area 7a, on the rear face of the carrier 6. The two connection areas 7a, 7b can be contacted or supplied with current individually and independently of each other.

[0084] FIG. 3 shows a third exemplary embodiment of the semiconductor chip. Unlike in FIG. 2, here it is not the first contact element 21 and the second contact element 22 that can be contacted individually and independently of one another but the first through-connections 31 and the second through-connections 32. The first through-connections 31 are electrically conductively connected to their own connection area 8a on the rear face of the carrier 6, and the second through-connections 32 are electrically conductively connected to their own connection area 8b on the rear face of the carrier 6. The connection areas 8a, 8b can be contacted or supplied with current individually and independently of each other.

[0085] FIG. 4 shows a fourth exemplary embodiment of the optoelectronic semiconductor chip. In contrast to the optoelectronic semiconductor chip of FIG. 1, the second contact element 22 in the region adjacent to the second semiconductor layer sequence 12 is now not formed of metal, but by an electrically conductive Bragg mirror 22a comprising a plurality of transparent layers with different refractive indices. The layers of the mirror 22a contain, for example, different conductive oxides.

[0086] FIG. 5A shows a fifth exemplary embodiment of the optoelectronic semiconductor chip, again in cross-sectional view. In contrast to the exemplary embodiment of FIG. 4, here the Bragg mirror 22a is not made of electrically conductive transparent layers, but of dielectric layers. In order to nevertheless enable contacting to the second semiconductor layer sequence 12, the mirror 22a is interspersed with metallic contact pins 22b which electrically conductively connect the electrically conductive material of the second contact element 22 to the second semiconductor layer sequence 12.

[0087] Similarly, a dielectric mirror may be arranged between the first contact element 21 and the first semiconductor layer sequence 11, wherein an electrical connection between the first semiconductor layer sequence 11 and the first contact element 21 is provided by contact pins.

[0088] In FIG. 5B, the optoelectronic semiconductor chip of FIG. 5A is shown in a cross-sectional view when cut through and along the connection layer 14. Firstly, it can be seen here that in the present exemplary embodiment, the second contact element 22 does not form a grid around semiconductor blocks of the first semiconductor layer sequence. Rather, the second contact element 22 is guided through the first semiconductor layer sequence 11 in the region of rectangular apertures. For example, the first semiconductor layer sequence 11 is formed contiguously over its entire lateral extent. In the region of the apertures in the first semiconductor layer sequence 11, the second through-connections 32 are also guided through the second contact element 22. The first through-connections 31 are indicated as dashed circles and are arranged in the region outside the apertures. The second contact element 22 includes a dielectric Bragg mirror 22a through which the contact pins 22b extend.

[0089] FIGS. 6A to 6F show a first exemplary embodiment of the method for producing an optoelectronic semiconductor chip using a plurality of intermediate positions.

[0090] In the first position of FIG. 6A, a first semiconductor layer sequence 11 and a second semiconductor layer sequence 12 are applied to each other by means of a connection layer 14, in particular an adhesive layer 14. This results in a composite 1.

[0091] In the second position of FIG. 6B, apertures are made in the first semiconductor layer sequence 11 from a rear face 13 opposite a front face 10 of the composite 1. The apertures completely penetrate the first semiconductor layer sequence 11 as well as the connection layer 14 and extend up to the second semiconductor layer sequence 12. The apertures may form a contiguous grid (see for example FIG. 1B) or they may be apertures spaced apart from each other in pairs which are not connected (see for example FIG. 5B).

[0092] FIG. 6C shows a position in which a first contact element 22 is formed in the apertures and is electrically conductively connected to a first layer 12a of the second semiconductor layer sequence 12. In the region of the apertures, the second contact element 22 is electrically insulated from the first semiconductor layer sequence 11 by an insulation material 5.

[0093] FIG. 6D shows another position in the method in which a first contact element 21 is formed on the rear face 13. The first contact element 21 is used to contact the first semiconductor layer sequence 11 and is electrically conductively connected to a first layer 11a of the first semiconductor layer sequence 11. In the present case, the first contact element 21 is also electrically conductively connected to the second contact element 22. Other than shown in FIGS. 6C and 6D, the two contact elements 21, 22 could also be formed simultaneously in a common method step.

[0094] FIG. 6E shows a position in the method in which first through-connections 31 and second through-connections 32 are formed. The first through-connections 31 extend from the rear face 13 through the first layer 11a and the active layer 11b of the first semiconductor layer sequence 11 and terminate in a second layer 11c of the first semiconductor layer sequence 11. The second through-connections 32 are guided from the rear face 13 completely through the first semiconductor layer sequence 11 and the connection layer 14, cross the first layer 12a and the active layer 12b of the second semiconductor layer sequence 12 and terminate in a second layer 12c of the second semiconductor layer sequence 12. The first and second through-connections 31, 32 may be produced simultaneously or successively.

[0095] FIG. 6F shows a position in the method after a carrier 6 has been applied to the rear face 13 of the composite 1. The contact elements 21, 22 and through-connections 31, 32 can be electrically contacted on a side of the carrier 6 facing away from the composite 1 by means of connection areas 7, 8. FIG. 6F also shows an exemplary embodiment of a finished optoelectronic semiconductor chip.

[0096] FIGS. 7A to 7E show a second exemplary embodiment of the method using intermediate positions.

[0097] In the position shown in FIG. 7A, a second semiconductor layer sequence 12 is provided. A plurality of semiconductor blocks 11d are also provided. In the present case, the semiconductor blocks 11d are provided in the form of micro-LED chips 11d. These micro-LED chips 11d each already include a second through-connection 32 extending through the active layer 11b from one side thereof. On the same side from which the second through-connection 32 extends, a first contact element 21 is also arranged in each case. The micro-LED chips 11d can be contacted via the first contact element 21 and the first through-connection 31.

[0098] In FIG. 7A, the semiconductor blocks 11d are arranged on the second semiconductor layer sequence 12 spaced apart from each other by means of a connection layer 14.

[0099] FIG. 7B shows a position after the semiconductor blocks 11d have been attached to the second semiconductor layer sequence 12, thereby forming a composite 1. All the semiconductor blocks 11d together form a first semiconductor layer sequence 11 of the composite 1.

[0100] In the position shown in FIG. 7C, a second contact element 22 is now formed in the region between the semiconductor blocks 11d. The second contact element 22 extends up to and contacts the second semiconductor layer sequence 12.

[0101] FIG. 7D shows a position in the method in which second through-connections 32 are formed which are guided through the second contact element 22 in the region between the semiconductor blocks 11d and subsequently protrude into the second semiconductor layer sequence 12, thereby penetrating the active layer 12b of the second semiconductor layer sequence 12.

[0102] FIG. 7E shows another position in which a carrier 6 is applied to the rear face 13 of the composite 1. FIG. 7E also shows an exemplary embodiment of a finished optoelectronic semiconductor chip.

[0103] The invention is not limited to the exemplary embodiments by the description based thereon. Rather, the invention encompasses any new feature as well as any combination of features, which in particular includes any combination of features in the patent claims, even if this feature or combination itself is not explicitly stated in the patent claims or embodiments.

[0104] This patent application claims the priority of German patent application 102019119891.7, the disclosure content of which is hereby incorporated by reference.

LIST OF REFERENCE SIGNS

[0105] 1 composite [0106] 5 insulation material [0107] 6 carrier [0108] 7, 7a, 7b, 8 connection area [0109] 10 front face [0110] 11 first semiconductor layer sequence [0111] 11a first layer of the first semiconductor layer sequence [0112] 11b active layer of the first semiconductor layer sequence [0113] 11c second layer of the first semiconductor layer sequence [0114] 11d semiconductor block second semiconductor layer sequence [0115] 12a first layer of the second semiconductor layer sequence [0116] 12b active layer of the second semiconductor layer sequence [0117] 12c second layer of the second semiconductor layer sequence [0118] 13 rear face [0119] 21 first contact element [0120] 22 second contact element [0121] 22a mirror [0122] 22b contact pin [0123] 31 first through-connection [0124] 32 second through-connection