NUCLEAR REACTION DETECTION APPARATUS, METHOD, AND PROGRAM

Abstract

A nuclear reaction detection device includes an FPGA (Field Programmable Gate Array) 100 which is arranged in an environment in which particle radiation is incident, and includes a user circuit 101 configured to output a value different from that in a normal state, if an SEU (Single Event Upset) occurs in a semiconductor element included in the FPGA, and an SEF detection unit 210 which detects that an abnormal operation (SEF) has occurred in the user circuit based on the output value from the user circuit 101 of the FPGA 100.

Claims

1. A nuclear reaction detection device comprising: an FPGA (Field Programmable Gate Array) that is arranged in an environment in which particle radiation is incident, and includes a user circuit, the user circuit being configured to output a value different from that in a normal state, if an SEU (Single Event Upset) occurs in a semiconductor element included in the FPGA; and an abnormal operation detection unit, comprising one or more hardware processors, that detects that an abnormal operation has occurred in the user circuit based on the value that is output from the user circuit in the FPGA.

2. The nuclear reaction detection device according to claim 1, wherein the user circuit includes a memory circuit unit, and a memory monitoring circuit unit that monitors each of all pieces of data included in the memory circuit unit in a clock cycle of the FPGA, and detects a change in a value of any of the pieces of data to output a detection result.

3. The nuclear reaction detection device according to claim 2, wherein the memory monitoring circuit unit includes a data updating circuit unit that changes all pieces of data of the memory circuit unit with a same value and in the clock cycle, a data comparing circuit unit that compares individual pieces of data of the memory circuit unit, and a detection circuit unit that detects that values of the individual pieces of data are no longer the same based on a comparison result by the data comparing circuit unit, and outputs a detection result.

4. The nuclear reaction detection device according to claim 1, comprising: an SEU cross section calculation unit that calculates an SEU cross section based on a number of occurrences of the abnormal operation detected by the abnormal operation detection unit.

5. The nuclear reaction detection device according to claim 1, comprising: a particle energy calculation unit that calculates particle energy by using a time-of-flight method based on an occurrence time of the abnormal operation measured by the abnormal operation detection unit.

6. The nuclear reaction detection device according to claim 1, wherein the FPGA is an SRAM-type FPGA.

7. A nuclear reaction detection method comprising: a step of arranging, in an environment in which particle radiation is incident, an FPGA (Field Programmable Gate Array) that includes a user circuit, the user circuit being configured to output a value different from that in a normal state, if an SEU (Single Event Upset) occurs in a semiconductor element included in the FPGA; and an abnormal operation detection step of detecting that an abnormal operation has occurred in the user circuit based on the output value from the user circuit in the FPGA.

8. A computer readable recording medium storing a nuclear reaction detection program, wherein executing of the nuclear reaction detection program causes one or more computer to perform operations comprising: detecting that an abnormal operation has occurred in a user circuit based on a output value from a user circuit in a FPGA (Field Programmable Gate Array), wherein the FPGA that is arranged in an environment in which particle radiation is incident, and includes the user circuit, the user circuit being configured to output a value different from that in a normal state, if an SEU (Single Event Upset) occurs in a semiconductor element included in the FPGA.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0013] FIG. 1 is a diagram illustrating a configuration of a nuclear reaction detection device according to an embodiment of the present invention.

[0014] FIG. 2 is a diagram for explaining an internal structure of an FPGA.

[0015] FIG. 3 is a diagram for explaining an internal structure of a CLB of an FPGA, and the occurrence of an SEF.

[0016] FIG. 4 is a diagram for explaining an internal structure of an SM in an FPGA, and the occurrence of an SEF.

[0017] FIG. 5 is a diagram for explaining operations of a memory monitoring circuit in an FPGA.

[0018] FIG. 6 is a diagram showing the relationship between neutron energy and time-of-flight.

MODE FOR CARRYING OUT THE INVENTION

[0019] A nuclear reaction detection device according to an embodiment of the present invention will be described with reference to FIGS. 1 to 5. FIG. 1 is a configuration diagram of a nuclear reaction detection device according to an embodiment of the present invention. FIG. 2 is a diagram for explaining an internal structure of an FPGA. FIG. 3 is a diagram for explaining an internal structure of a CLB of an FPGA, and the occurrence of an SEF. FIG. 4 is a diagram for explaining an internal structure of an SM of an FPGA, and the occurrence of an SEF. FIG. 5 is a diagram for explaining operations of a memory monitoring circuit in an FPGA.

[0020] In this embodiment, by detecting an error caused by an SEU in the order of nanoseconds, the energy of the particle generating the SEU is specified using a time-of-flight method, and an SEU cross section of the energy is measured from the fluence of the particle with which an object has been irradiated. More specifically, as shown in FIG. 1, the SEU is detected by using a user circuit 101 of an SRAM-type FPGA 100. The FPGA of the present embodiment is arranged in an environment in which particle radiation is incident, and is formed with a user circuit configured to output a value different from that in a normal state, if an SEU occurs in a semiconductor element included in the FPGA.

[0021] First, the general internal structure of the FPGA, and the principle of detecting an SEU will be described. As shown in FIG. 2, the FPGA includes CLBs (Configuration Logic Block) which constitute the logic, IOBs (Input Output Block) which realize input/output functions, SMs (Switch Matrix) which are connection elements for realizing the connection between elements, and PSBs (Programmable Switch Box).

[0022] As shown in FIG. 3, each CLB includes an LUT (Look Up Table), and an FF (Flip Flop). The CLB can control an output value based on data of a CRAM (Configuration RAM) made of the SRAM of the LUT, and can configure various basic circuits. If an SEU occurs in the CRAM in the LUT, a circuit having a design different from the design intended by the user is formed, and a malfunction occurs.

[0023] As shown in FIG. 4, each SM (switch matrix) freely sets a wiring path by means of a pass-transistor. The pass-transistor being on/off is controlled by the CRAM made of the SRAM. If an SEU occurs in the CRAM, the wiring has a design different from the design intended by the user.

[0024] As described above, if an SEU occurs in the CLBs as logic units and the CRAMs of the SMs as connection units, the circuit immediately becomes an erroneous circuit, and may operate differently from the circuit operation designed by the user. This abnormal operation is called an SEF (Soft error failure) in this case. The detection of an SEF enables a high-speed detection of an SEU.

[0025] An example of the user circuit 101 capable of detecting an SEF will be described with reference to FIG. 1. As is well known, the user circuit 101 is configured by externally writing configuration data for the construction of the user circuit into the FPGA 100.

[0026] In the example of FIG. 1, the user circuit 101 includes a memory circuit unit 110, and a memory monitoring circuit unit 120. The memory monitoring circuit unit 120 monitors each piece of data included in the memory circuit unit 110 in an operation clock cycle of the FPGA 100, detects that a value of any of the pieces of data has changed, and outputs a detection result. This configuration enables the detection of an SEF in the order of the operation clock of the FPGA 100. Note that the frequency of the operation clock of the FPGA 100 does not necessarily coincide with an external clock input to the FPGA 100.

[0027] As a more specific example, the memory monitoring circuit unit 120 includes a data updating circuit unit 121, a data comparing circuit unit 122, and a detection circuit unit 123. The data updating circuit unit 121 changes all pieces of data of the memory circuit unit 110 with the same value and in a clock cycle. The data comparing circuit unit 122 compares the individual pieces of data of the memory circuit unit 110. The detection circuit unit 123 detects that the individual data values are no longer the same based on the comparison result by the data comparing circuit unit 122, and outputs a detection result.

[0028] As a more specific example, the memory circuit unit 110 includes as many registers as possible. Further, in the data updating circuit unit 121, a circuit is constructed for causing each register of the memory circuit unit 110 to repeat 0.fwdarw.1.fwdarw.0.fwdarw.1 at the maximum operating frequency (the timing can be converged). The data comparing circuit unit 122 compares and monitors the plurality of registers of the memory circuit unit 110. An example of the data comparing circuit unit 122 is an XOR circuit.

[0029] If an SEU occurs, the registers do not function correctly, and thus the value does not change. The detection circuit unit 123 can detect an SEU at high speed by detecting an operation in which an output value of the data comparing circuit unit 122 does not change. The detection circuit unit 123 outputs an error detection signal after detecting the SEU. FIG. 5 illustrates an example of operations of the detection circuit unit 123. In FIG. 5, only two registers A and B included in the memory circuit unit 110 are illustrated to simplify the explanation. As illustrated in FIG. 5, the user circuit 101 can detect the occurrence of an SEU with a resolution on the order of nanoseconds. That is, the circuit can detect that an SEU has occurred within a time range of two clocks.

[0030] As illustrated in FIG. 1, the nuclear reaction detection device according to the present embodiment includes a nuclear reaction detection device body 200 that is electrically connected to the FPGA 100, and is arranged in an environment protected from the particle radiation. The nuclear reaction detection device body 200 includes an SEF detection unit 210, a particle energy calculation unit 220, an SEU cross section calculation unit 230, and a clocking unit 290. The nuclear reaction detection device body 200 is constituted from an information processor. The individual units of the nuclear reaction detection device body 200 may be mounted in any form, and may be constituted by dedicated hardware, may be constituted by a general-purpose device installed with a program, or may be constituted by any combination thereof.

[0031] The SEF detection unit 210 (an abnormal operation detection unit) detects the occurrence of an abnormal operation in the user circuit 101, that is, the occurrence of an SEF, based on an output value from the user circuit 101 of the FPGA 100. After detecting the occurrence of the SEF based on the error detection signal from the detection circuit unit 123, the SEF detection unit 210 recognizes the time at which the SEF occurred by acquiring the current time clocked by the clocking unit 290. The SEF detection unit 210 stores the occurrence of the SEF, and the time at which the SEF occurred in predetermined storage means (not illustrated) or outputs the same to an external device (not illustrated).

[0032] The particle energy calculation unit 220 calculates particle energy by using the time-of-flight method based on the occurrence time of the abnormal operation measured by the SEF detection unit 210. Specifically, the particle energy calculation unit 220 calculates the difference between the time at which the acquired error detection signal from the detection circuit unit 123 is transmitted to the SEF detection unit 210, that is, the occurrence time of the SEF, and the time at which particles are generated. Accordingly, the particle energy calculation unit 220 can calculate the energy of the particles that generates the SEU and causes the SEF to occur. In order to acquire the time at which the particles are generated, the particle energy calculation unit 220 may detect the input of a particle generation timing signal from the external device, and acquire the current time at the time of detection from the clocking unit 290. The particle energy calculation unit 220 stores the calculated particle energy in a predetermined storage unit (not illustrated) or outputs the energy to the external device (not illustrated). The time at which the particles are generated may be acquired from the external device, or stored in advance in a predetermined storage unit, and acquired from the storage unit.

[0033] The SEU cross section calculation unit 230 calculates the SEU cross section of a CRAM. Specifically, the SEU cross section calculation unit 230 calculates the SEU cross section based on the number of occurrences of abnormal operations detected by the SEF detection unit 210. However, not all SEUs that occur in a CRAM cause an SEF. That is, an SEF may not be detected even if the SEU occurs in a CRAM that does not affect the circuit operation. SEFs vary depending on the user design, and thus it is not necessary to acquire the SEU cross section of an SEF, but it is necessary to acquire the SEU cross section of a CRAM.

[0034] To obtain an absolute value of the SEU cross section of a CRAM, correction is necessary. In order to perform the correction, the number of SEUs including CRAMs which are not used (N) is calculated by using a CRC check function of the CRAMs, the SEF count distribution is set as the SEF probability distribution p(t), and the SEF energy probability distribution p(E) is calculated from the relationship between the energy and an arrival time illustrated in FIG. 6. By multiplying N by p(E), an N.sub.SEU(E) absolute value which serves as the distribution of the number of SEU occurrences for each energy can be calculated. Finally, the SEU cross section for each energy is calculated from the fluence ϕ(E) for each energy measured with a neutron measuring device.

[0035] As described above, according to the nuclear reaction detection device of the present embodiment, the user circuit 101 of the FPGA 100 is configured such that the output behaves abnormally due to the occurrence of an SEU. Thus, the occurrence of an SEU can be detected in the order of the operation clock of the FPGA 100. In other words, the occurrence of an SEU can be detected at a high speed, and the measurement accuracy of the occurrence time of the SEU thereby becomes high. This enables high-accuracy measurement of the energy of the particles causing an event such as an SEU. Further, the occurrence rate of an event such as the SEU cross section for each continuous particle energy can be measured with high accuracy.

[0036] The particle energy calculation unit 210 and the SEU cross section calculation unit 220 in the nuclear reaction detection device body 200 are any components, and the nuclear reaction detection device body 200 may have only one of them.

[0037] The nuclear reaction detection device body 200 may further include an energy measuring unit for measuring the energy spectrum of a pulse particle source (pulse neutron source) by using the acquired occurrence rate of an event such as the SEU cross section.

[0038] The nuclear reaction detection device body 200 may further include energy detection means for detecting the energy in position information. The position information means a physical position (a spatial position) in the FPGA 100 at which an SEU has occurred. The position information can be acquired by, after detecting the occurrence of the SEU, comparing the configuration data for the user circuit construction with the user circuit 101, or by scanning data at each address of the memory circuit unit 110 to determine whether the data is appropriate.

EXAMPLE

[0039] An example of measuring the SEU cross section with neutrons will be given.

[0040] In a neutron irradiation field, a neutron flux and a neutron fluence are measured by the neutron measuring device during the irradiation of the semiconductor. A neutron generation target is irradiated with proton pulses accelerated by an accelerator to generate neutrons. The moment at which the proton pulse hits the neutron generation target is the time at which the neutrons are generated, and this corresponds to t=0 in the time-of-flight method. The time-of-flight is measured by taking the difference between a timing signal indicating t=0 and a timing signal for the detection of an SEF, and this can be converted into neutron energy.

[0041] The device uses the user circuit in the FPGA to construct the register, and causes the register to be operated at an operation clock. An object is irradiated with neutrons, and the time-of-flight and the SEF count are observed. In the measurement of the total SEU cross section for the entire CRAM area, the total number of CRAM errors is observed. From the above, the SEU cross section is calculated.

[0042] Although one embodiment of the present invention has been described in detail above, the present invention is not limited to the above described embodiment, and various improvements and modifications may be made without departing from the gist of the present invention.

[0043] For example, the present invention can be applied not only to an SRAM-type FPGA, but also to an EEPROM-type FPGA. Further, the particle radiation is not limited to neutron radiation, and the present invention can be applied to other particle radiation, as long as an SEU occurs when other particle radiation is incident on the FPGA.

[0044] The user circuit 101 is constructed of the memory circuit unit 110 and the memory monitoring circuit unit 120. However, another circuit may be adopted as long as an output value of another circuit changes owing to the occurrence of an abnormal operation due to the occurrence of an SEU.

[0045] The above described nuclear reaction detection device body 200 can use a general-purpose computer system. For example, the computer system includes a CPU (Central Processing Unit, a processor), a memory, a storage (HDD: Hard Disk Drive, SSD: Solid State Drive), a communication device, an input device, and an output device. The memory and storage are storage devices. In this computer system, each function of the nuclear reaction detection device body 200 is realized by the CPU executing a predetermined program loaded in the memory. Further, the nuclear reaction detection device body 200 may be implemented by a single computer, or alternatively by a plurality of computers. Further, the nuclear reaction detection device body 200 may be a virtual machine mounted on a computer. The program for the nuclear reaction detection device body 200 can be stored in a computer-readable recording medium such as an HDD, SSD, USB (Universal Serial Bus) memory, CD (Compact Disc), or DVD (Digital Versatile Disc), or alternatively the program may be distributed via a network.

EXPLANATION OF THE REFERENCE NUMERALS

[0046] 100 FPGA [0047] 101 User circuit [0048] 110 Memory circuit unit [0049] 120 Memory monitoring circuit unit [0050] 121 Data updating circuit unit [0051] 122 Data comparing circuit unit [0052] 123 Detection circuit unit [0053] 200 Nuclear reaction detection device body [0054] 210 SEF detection unit [0055] 220 Particle energy calculation unit [0056] 230 SEU cross section calculation unit [0057] 290 Clocking unit