Motor drive

Abstract

A motor drive comprises a rectifier arranged to receive an externally supplied AC voltage and to generate a DC bus voltage. An inverter is arranged to receive the DC bus voltage and to generate an AC output voltage for supply to an external load. A DC bus portion is connected between the rectifier and the inverter. The DC bus comprises first and second conductors, wherein an inductor is connected in series along the first conductor between the rectifier and the inverter. A DC link capacitor is connected in parallel between the conductors. A controller is arranged to supply a plurality of perturbation signals at a first node between the rectifier circuit portion and the DC bus portion, to measure a respective response signal at a second node between the DC bus and the inverter and is is arranged to generate a parameterised model of a transfer function of the DC.

Claims

1. A motor drive comprising: a rectifier circuit portion arranged to receive an externally supplied AC voltage and to generate a DC bus voltage therefrom; an inverter circuit portion arranged to receive the DC bus voltage and to generate an AC output voltage therefrom for supply to an external load; a DC bus portion connected between said rectifier and inverter circuit portions, said DC bus portion comprising first and second conductors, wherein an inductor is connected in series along the first conductor between said rectifier and inverter circuit portions, and wherein a DC link capacitor is connected in parallel between the first and second conductors; and a controller arranged to supply a plurality of perturbation signals at a first node between the rectifier circuit portion and the DC bus portion, and to measure a respective response signal, for each perturbation signal, at a second node between the DC bus portion and the inverter circuit portion; wherein the controller is arranged to generate a parameterised model of a transfer function of the DC bus portion from said perturbation and response signals and to extract an estimated capacitance of the DC link capacitor from said parameterised model.

2. The motor drive as claimed in claim 1, wherein the plurality of perturbation signals comprise sinusoidal signals, optionally wherein each of the perturbation signals comprises a sinusoidal signal having a different frequency, further optionally wherein the frequencies of the perturbation signals are a power of two.

3. The motor drive as claimed in claim 1, wherein an amplitude of each perturbation signal is less than 30 V.

4. The motor drive as claimed in claim 1, wherein fewer than twenty perturbation signals are used, optionally wherein fewer than fifteen perturbation signals are used, further optionally wherein ten or fewer perturbation signals are used.

5. The motor drive as claimed in claim 1, wherein the controller is arranged to carry out Frequency Response Function (FRF) measurements.

6. The motor drive as claimed in claim 1, wherein the controller uses IQ demodulation, said controller being arranged to generate in-phase and quadrature sequences for each perturbation signal and to determine in-phase and quadrature sequences for each respective response signal.

7. The motor drive as claimed in claim 1, wherein the parametrised model comprises a ratio of frequency-dependent complex polynomials.

8. The motor drive as claimed in claim 1, wherein the controller is arranged to minimise an error between the parametrised model and the transfer function.

9. The motor drive as claimed in claim 8, wherein the controller is arranged to linearise a cost function used to minimise the error between the parametrised model and the transfer function.

10. The motor drive as claimed in claim 9, wherein the controller modifies the cost function using a weighting function.

11. The motor drive as claimed in claim 10, wherein the weighting function comprises the denominator of the ratio of frequency-dependent complex polynomials.

12. The motor drive as claimed in claim 8, wherein the controller is arranged to determine a relative error function.

13. The motor drive as claimed in claim 12, wherein the controller is arranged to minimise the relative error between the measured transfer function and the parameterised model generated by the controller.

14. The motor drive as claimed in claim 1, wherein the controller is arranged to carry out an iterative computation process to fit the parametrised model to the measured transfer function.

15. The motor drive as claimed in claim 1, wherein the controller comprises a start-up built-in test (SBIT) controller.

16. A method of estimating a capacitance of a DC link capacitor within a DC bus portion of a motor drive, wherein the DC bus portion comprises an inductor and the DC link capacitor, the method comprising: supplying a plurality of perturbation signals at a first node between a rectifier circuit portion and the DC bus portion; for each perturbation signal, measuring a respective response signal at a second node between the DC bus portion and the inverter circuit portion; generating a parameterised model of a transfer function of the DC bus portion from said perturbation and response signals; and extracting an estimated capacitance of the DC link capacitor from said parameterised model.

17. A non-transitory computer-readable medium comprising instructions that, when executed by a processor, cause the processor to carry out a method of estimating a capacitance of a DC link capacitor within a DC bus portion of a motor drive, wherein the DC bus portion comprises an inductor and the DC link capacitor, the method comprising: supplying a plurality of perturbation signals, each having a respective frequency, at a first node between a rectifier circuit portion and the DC bus portion; for each perturbation signal, measuring a respective response signal at a second node between the DC bus portion and the inverter circuit portion; generating a parameterised model of a transfer function of the DC bus portion from said perturbation and response signals; and extracting an estimated capacitance of the DC link capacitor from said parameterised model.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Certain examples of the present disclosure will now be described with reference to the accompanying drawings, in which:

(2) FIG. 1 is a schematic diagram of a prior art motor drive system; and

(3) FIG. 2 is a schematic diagram of a motor drive system in accordance with an example of the present disclosure.

DETAILED DESCRIPTION

(4) FIG. 1 is a schematic diagram of a prior art motor drive system 2. The motor drive system 2 includes a front-end rectifier 4 and a power inverter 6, which are connected by a DC bus 8.

(5) The front-end rectifier 4 is arranged to receive an externally supplied AC voltage V.sub.supply, which in this example is a three-phase AC input voltage, via an electromagnetic compatibility (EMC) filter 3. The EMC filter 3 removes electromagnetic noise from the externally supplied AC voltage V.sub.supply and the conducted emissions from the system that can affect the external AC voltage.

(6) The rectifier 4 converts this AC voltage V.sub.supply to a DC bus voltage V.sub.DC_Bus which is transferred to the inverter 6 across the DC bus 8, the details of which are discussed in more detail below. It will be appreciated that other arrangements are possible, e.g. in which the rectifier 4 receives a single-phase input. Thus the rectifier 4 is an AC-to-DC converter (ADC).

(7) The inverter 6 takes the DC bus voltage V.sub.DC_Bus and converts it back to an AC output voltage V.sub.out suitable for supply to the connected load. In this example, the inverter 6 supplies the output voltage V.sub.out to a motor 10, which in turn is arranged to drive an actuator 12. In this example, the output voltage V.sub.out provided to the motor 10 is a three-phase voltage suitable to drive the three-phase motor 10. It will be appreciated that other arrangements are possible, e.g. in which the inverter 6 produces a single-phase output. Thus the inverter 6 is a DC-to-AC converter (DAC).

(8) The DC bus portion 8 is constructed from an inductor L.sub.1 along the positive conductor 7 (i.e. rail) of the DC bus portion 8, where this inductor L.sub.1 is shown in series with its equivalent resistance r.sub.L. A DC link capacitor C.sub.1 is connected in parallel between the positive conductor 7 and the negative conductor 9, where the equivalent resistance r.sub.C1 is shown in series with the DC link capacitor C.sub.1. This DC link capacitor C.sub.1 smooths the DC voltage output produced by the front-end rectifier, i.e. the DC bus voltage V.sub.DC_Bus. The DC link capacitor C.sub.1 also protects upstream circuits from the transient response of downstream circuits.

(9) A current control loop 14 serves to control the inverter 6 so as to provide the necessary amount of current to the motor 10 for proper driving of the actuator 12 to a desired set point. This current control loop 14 may use any suitable control mechanism, known in the art per se, such as proportional-integral (PI), closed loop control.

(10) Over time, the capacitance of the DC link capacitor C.sub.1 changes due to aging. The capacitance of the DC link capacitor C.sub.1 may also change in response to a ‘shock’, e.g. due to a large voltage spike.

(11) FIG. 2 is a schematic diagram of a motor drive system 2′ in accordance with an example of the present disclosure, where like reference numerals appended with a prime symbol (′) denote like components to those described above with reference to the prior art motor drive system 2 of FIG. 1.

(12) In the motor drive system 2′ of FIG. 2, an SBIT controller 16 is connected across the DC bus portion 8′ via a DC link voltage ADC interface 18. As outlined in further details below, the SBIT controller 16 measures the input and output signals of the DC bus portion 8′ to determine the transfer function of the DC bus portion 8′.

(13) The SBIT controller 16 is arranged to supply a plurality of perturbation signals 20 at a first node 22 between the rectifier circuit portion 4′ and the DC bus portion 8′, and to measure a respective response signal, for each perturbation signal, at a second node 24 between the DC bus portion 8′ and the inverter circuit portion 6′.

(14) The SBIT controller 16 is arranged to take FRF measurements 26 of the input and output signals associated with the DC bus portion 8′ as outlined below. The SBIT controller 16 also generates a parameterised model 28 of the transfer function of the DC bus portion 8′ from the perturbation and response signals and to extract an estimated capacitance of the DC link capacitor C.sub.1 from the parameterised model.

(15) The in-phase and quadrature response signals X.sub.I(k), X.sub.Q(k) at the input of the DC bus portion 8′ (i.e. at the node 22) may be given by Equations 1 and 2 below:

(16) $X_I\left(k\right)=\frac{2}{N}\underset{n=0}{\overset{N-1}{.Math.}}x\left(n\right)\sin \left(\frac{2\pi k}{N}n\right)$
Equation 1: In-Phase Response Signal X.sub.I(k) at the Input of the DC Bus Portion

(17) $X_Q\left(k\right)=\frac{2}{N}\underset{n=0}{\overset{N-1}{.Math.}}x\left(n\right)\cos \left(\frac{2\pi k}{N}n\right)$
Equation 2: Quadrature Response Signal X.sub.Q(k) at the Input of the DC Bus Portion
where X.sub.I(k) is the in-phase response signal, X.sub.Q(k) is the quadrature response signal, k is the perturbation frequency, and N is the number of measurement samples.

(18) The in-phase and quadrature response signals at the output of the DC bus portion 8′ (i.e. at the node 24), measured via the DC link voltage ADC interface 18, are given by Equations 3 and 4 below:

(19) $Y_I\left(k\right)=\frac{2}{N}\underset{n=0}{\overset{N-1}{.Math.}}y\left(n\right)\sin \left(\frac{2\pi k}{N}n\right)$
Equation 3: In-Phase Response Signal Y.sub.I(k) at the Output of the DC Bus Portion

(20) $Y_Q\left(k\right)=\frac{2}{N}\underset{n=0}{\overset{N-1}{.Math.}}y\left(n\right)\cos \left(\frac{2\pi k}{N}n\right)$
Equation 4: Quadrature Response Signal Y.sub.Q(k) at the Output of the DC Bus Portion
where Y.sub.I(k) is the in-phase response signal, Y.sub.Q(k) is the quadrature response signal, k is the perturbation frequency, and N is the number of measurement samples.

(21) The magnitude |H.sub.NP| and phase response arg (H.sub.NP(s.sub.k)) of the non-parametrised (i.e. measured) transfer function are then given by Equations 5 and 6 respectively:

(22) $.Math.H_{NP}.Math.=\sqrt{\frac{{\left(Y_I\left(k\right)\right)}^2+{\left(Y_Q\left(k\right)\right)}^2}{{\left(X_I\left(k\right)\right)}^2+{\left(X_Q\left(k\right)\right)}^2}}$
Equation 5: Magnitude |H.sub.NP| of the Non Parametrised Transfer Function

(23) $\arg \left(H_{NP}\left(s_k\right)\right)={\tan }^{-1}\left(\frac{Y_I\left(k\right)+j{Y}_Q\left(k\right)}{X_I\left(k\right)+j{X}_Q\left(k\right)}\right)$
Equation 6: Phase Response Arg (H.sub.NP(s.sub.k)) of the Non-Parametrised Transfer Function
where s.sub.k is the complex frequency in the Laplace domain and j is the imaginary unit.

(24) The SBIT controller 16 generates a parametrised model 28, which comprises a ratio of frequency-dependent complex polynomials, in accordance with Equation 7 below:

(25) $H_P\left(s_k\right)=\frac{N\left(s_k\right)}{D\left(s_k\right)}=\frac{{\Sigma }_{k=0}^n{n}_k{s}^k}{{\Sigma }_{k=0}^d{d}_k{s}^k}=\frac{n_0+n_{1}s+n_2{s}^2+\mathrm{.Math.}}{d_0+d_{1}s+d_2{s}^2+\mathrm{.Math.}}$
Equation 7: Parametrised Transfer Function H.sub.P(s.sub.k)

(26) The SBIT controller 16 is arranged to minimise an error between the parametrised model and the transfer function by summing the residual sum of squares and equating the partial derivative of the resulting sum with respect to the coefficients to zero. The function for minimising the absolute error is given in Equation 8 below:

(27) ${.Math.{\mathrm{.Math.}}_k.Math.}^2=\underset{k=1}{\overset{F}{.Math.}}{.Math.H_{NP}\left(s_k\right)-H_P\left(s_k\right).Math.}^2=\underset{k=1}{\overset{F}{.Math.}}{.Math.H_{NP}\left(s_k\right)-\frac{N\left(s_k\right)}{D\left(s_k\right)}.Math.}^2$
Equation 8: Function for Minimising Error Between the Non Parameterised Transfer Function H.sub.NP(s.sub.k) and the Parameterised Transfer Function H.sub.P(s.sub.k)

(28) The non-linear cost function can be minimised using non-linear optimisation techniques known in the art per se. However, such techniques typically depend on the initial values set. As a result, a simple least squares estimator may not be able to identify the non-linear function expressed in the form of a rational fraction. As such, the SBIT controller 16 is arranged to linearise the cost function. In some examples, the SBIT controller 16 modifies the cost function using a weighting function. In this case, the weighting function is the denominator D(s.sub.k) of the ratio of frequency-dependent complex polynomials, as per Equation 9:

(29) ${.Math.{\mathrm{.Math.}}_k^{\prime }.Math.D\left(s_k\right).Math.}^2=\underset{k=1}{\overset{F}{.Math.}}{.Math.H_{NP}\left(s_k\right).Math.D\left(s_k\right)-N\left(s_k\right).Math.}^2$
Equation 9: Linearised Function for Minimising Error Between the Non-Parameterised Transfer Function H.sub.NP(s.sub.k) and the Parameterised Transfer Function H.sub.P(s.sub.k)

(30) In order to fit the parametrised model to the measured transfer function, the SBIT controller 16 carries out an iterative computation process which minimises the cost function by constraining one of the coefficients to a constant and iteratively solving for the remaining coefficients. This iterative process may be carried out in accordance with Equation 10:

(31) 0${.Math.{\mathrm{.Math.}}_k^{″}.Math.}^2={.Math.\frac{{\mathrm{.Math.}}_k.Math.{D\left(s_k\right)}_i}{{D\left(s_k\right)}_{i-1}}.Math.}^2=\underset{i}{.Math.}\underset{k=1}{\overset{F}{.Math.}}{.Math.\frac{H_{NP}\left(s_k\right).Math.{D\left(s_k\right)}_i}{{D\left(s_k\right)}_{i-1}}-\frac{{N\left(s_k\right)}_i}{{D\left(s_k\right)}_{i-1}}.Math.}^2$
Equation 10: Iterative Computation Function to Minimise Error
where i denotes the iteration number. Subsequent iterations of the algorithm may allow D(s.sub.k) to asymptotically approach D(s.sub.k).sub.i while updating the weighting function and coefficients each iteration. By using d.sub.0=1 as an initial starting value, the absolute error (or cost) function may be minimised at all experimental points.

(32) In order to avoid an erroneous estimate of the system due to e.g. measurement errors and/or system uncertainties, the SBIT controller 16 is arranged to determine a relative error function which defines how large the error (i.e. the difference between the parameterised model and the non-parameterised measured transfer function) is in relation to the measured value, rather than how large the error itself is (i.e. its absolute value). This modified cost function, in accordance with Equation 11 below, may minimise the relative error between the measured transfer function and the parameterised model generated by the SBIT controller 16.

(33) ${.Math.{\mathrm{.Math.}}_k^{\mathrm{\prime \prime \prime }}.Math.}^2=\underset{i}{.Math.}\underset{k=1}{\overset{F}{.Math.}}{.Math.\frac{H_{NP}\left(s_k\right).Math.{D\left(s_k\right)}_i}{{D\left(s_k\right)}_{i-1}{H}_{NP}\left(s_k\right)}-\frac{{N\left(s_k\right)}_i}{{D\left(s_k\right)}_{i-1}.Math.H_{NP}\left(s_k\right)}.Math.}^2$
Equation 11: Iterative Computation Function to Minimise Relative Error

(34) The relative error criterion, combined with a weighing function and iterative process as outlined above may yield a best-fit for the system model. The estimated best-fit model defined in the form of a Laplace rational fraction may advantageously enable extracting the model coefficients and the components values. For example, if the best-fit model matches a second-order Laplace rational fraction of the system, comparison of the extracted and actual circuit component values may provide an estimate of degradation or anomalies in the system and/or electronic components.

(35) In order to extract the model parameters 30 from the numerator and denominator terms of the parameterised transfer function H.sub.P(s.sub.k) following the iterative best-fit process outlined above, the following relationships may be used:

(36) $n_0=\frac{1}{\left(R_{\mathrm{Load}}+r_L\right)}{n}_1=\frac{C_1.Math.r_{C1}}{R_{\mathrm{Load}}+r_L}{d}_0=1d_1=\frac{L_1+C_1.Math.r_{C1}.Math.r_L+C_1.Math.R_{\mathrm{Load}}.Math.r_L+C_1.Math.R_{\mathrm{Load}}.Math.r_{C1}}{R_{\mathrm{Load}}+r_L}{d}_2=\frac{C_1.Math.L_1.Math.r_{C1}+C_1.Math.L_1.Math.R_{\mathrm{Load}}}{R_{\mathrm{Load}}+r_L}$
where r.sub.L is the DC resistance of the inductor L.sub.1 in ohms, R.sub.Load is the load resistance in ohms and represents the equivalent load of the inverter 6′, L.sub.1 is the inductance of the inductor L.sub.1 in henrys, C.sub.1 is the capacitance of the DC link capacitor C.sub.1, and r.sub.C1 is the equivalent series resistance (ESR) of the DC link capacitor C.sub.1 in ohms.

(37) By using the determined values of n.sub.0, n.sub.1, d.sub.0, d.sub.1, and d.sub.2, and assuming the inductance of the inductor L.sub.1 remains constant, the capacitance value of the DC link capacitor C.sub.1 can be determined.

(38) This determined capacitance value of the DC link capacitor C.sub.1 can then be stored in a non-volatile memory (NVM) 32 via an NVM interface 34. By comparing the determined capacitance values stored in the NVM 32 over time, a determination can be made as to the degradation rate of the DC link capacitor C.sub.1 such that pre-emptive maintenance can be scheduled when necessary.

(39) Thus examples of the present disclosure may allow the use of light, small-volume DC link capacitors, the health of which can be advantageously monitored to determine when maintenance is required. While specific examples of the disclosure have been described in detail, it will be appreciated by those skilled in the art that the examples described in detail are not limiting on the scope of the disclosure.