OPTICAL MODULATOR AND METHOD OF FABRICATING AN OPTICAL MODULATOR

Abstract

A MOS capacitor-type optical modulator comprising a silicon-on-insulator (SOI) substrate, a first doped region in a silicon device layer of the SOI substrate, and a second doped region laterally separated from the first doped region by a vertically extending insulator layer to form a lateral MOS capacitor region. The first doped region, second doped region and insulator layer are formed from different materials.

Claims

1. A MOS capacitor-type optical modulator comprising: a silicon-on-insulator, SOI, substrate; a first doped region in a silicon device layer of the SOI substrate; and a second doped region laterally separated from the first doped region by a vertically extending insulator layer to form a lateral MOS capacitor region, wherein the first doped region, second doped region and insulator layer are formed from different materials.

2. The MOS capacitor-type optical modulator of claim 1, wherein the second doped region is formed in a type III-V semiconductor region.

3. The MOS capacitor-type optical modulator of claim 1, wherein the insulator layer comprises silicon nitride.

4. The MOS capacitor-type optical modulator of claim 1, wherein the silicon device layer of the SOI substrate has a (100) crystalline orientation.

5. The MOS capacitor-type optical modulator of claim 1, wherein a first portion of the insulator layer extends horizontally on top of the first doped region, and a second portion of the insulator layer extends horizontally beneath the second doped region.

6. The MOS capacitor-type optical modulator of claim 1, wherein the insulator layer extends at an oblique angle relative to the substrate, so as to laterally separate the second doped region from the first doped region.

7. A method of fabricating a MOS capacitor-type optical modulator having a lateral MOS capacitor region, the lateral MOS capacitor region comprising a vertically extending insulator layer laterally separating a first doped region and a second doped region, wherein the method comprises the steps of: providing a first doped region in a silicon device layer of a silicon-on-insulator, SOI, substrate; and epitaxially growing a semiconductor region from the silicon device layer of the SOI substrate, wherein the semiconductor region comprises the second doped region, and the first doped region, second doped region and insulator layer are each formed from different materials.

8. The method according to claim 7, wherein the semiconductor region is epitaxially grown from a region of the silicon device layer laterally offset from the MOS capacitor region.

9. The method according to claim 7, wherein the semiconductor region is a type III-V semiconductor region.

10. The method according to claim 7, wherein the silicon device layer of the SOI substrate has a (100) crystalline structure.

11. The method according to claim 7, wherein the method further comprises the step of: etching a portion of the semiconductor region to form a waveguide structure, the waveguide structure comprising the MOS capacitor region.

12. The method according to claim 11, further comprising the steps of: depositing an isolation layer on the waveguide structure; applying a first electrical contact through the isolation layer to the first doped region; and applying a second electrical contact through the isolation layer to the second doped region.

13. The method according to claim 7, wherein the method further comprises the steps of: creating a cavity underneath an upper mask layer; and epitaxially growing the semiconductor region from the silicon device layer of the SOI substrate in the cavity.

14. The method according to claim 13, wherein the upper mask layer comprises silicon nitride.

15. The method according to claim 13, wherein the step of creating the cavity comprises: providing a sacrificial layer; depositing the upper mask layer on top of the sacrificial layer; and selectively etching the sacrificial layer to create the cavity.

16. The method according to claim 15, wherein the method further comprises the steps of: etching a trench in the silicon device layer of the SOI substrate; depositing a lower mask layer on top of the silicon device layer and in the trench; etching an opening in the lower mask layer to the silicon device layer at a region of the silicon device layer laterally offset from the MOS capacitor region; and depositing the sacrificial layer on the lower mask layer and in the opening in the lower mask layer.

17. The method according to claim 16, further comprising the step of etching a portion of the sacrificial layer to the lower mask layer before depositing the upper mask layer.

18. The method according to claim 15, wherein the method further comprises the step of planarizing the sacrificial layer by Chemical Mechanical Planarization, CMP.

19. The method according to claim 15, wherein the sacrificial layer comprises aluminium oxide or amorphous silicon.

20. (canceled)

21. (canceled)

22. A method of fabricating a MOS capacitor-type optical modulator having a MOS capacitor region comprising a semiconductor region, the method comprising the steps of: creating a cavity underneath an upper mask layer; and epitaxially growing the semiconductor region from a silicon device layer of a silicon-on-insulator, SOI, substrate in the cavity.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0077] Embodiments of the invention will now be described by way of example with reference to the accompanying drawings in which:

[0078] FIG. 1 is a schematic cross-section of a MOS capacitor-type optical modulator according a first embodiment of the present invention;

[0079] FIG. 2 is a schematic cross-section of a MOS capacitor-type optical modulator according to a second embodiment of the present invention;

[0080] FIGS. 3a-3l depict steps of a method of fabricating the modulator of FIG. 1;

[0081] FIGS. 4a-4l depict steps of a method of fabricating the modulator of FIG. 2; and

[0082] FIGS. 5a-5g depict steps of a variant method of fabricating the modulator of FIG. 2.

DETAILED DESCRIPTION

[0083] The detailed description set forth below in connection with the appended drawings is intended as a description of exemplary embodiments of a MOS capacitor-type optical modulator and its method of fabrication provided in accordance with the present invention and is not intended to represent the only forms in which the present invention may be constructed or utilized. The description sets forth the features of the present invention in connection with the illustrated embodiments. It is to be understood, however, that the same or equivalent functions and structures may be accomplished by different embodiments that are also intended to be encompassed within the spirit and scope of the invention. As denoted elsewhere herein, like element numbers are intended to indicate like elements or features.

[0084] A MOS capacitor-type optical modulator 1 and its method of fabrication according to a first embodiment are described below with reference to FIGS. 1 and 3a-l. The modulator 1 comprises a SOI substrate 20.

[0085] As shown in FIG. 3a, the silicon-on-insulator substrate 20 is initially provided comprising a silicon base layer 23, a buried silicon dioxide (BOX) layer 22 and a silicon device layer 21. The silicon device layer 21 has a Si(100) crystalline structure. A trench 24 is etched in the silicon device layer 21 to the BOX layer 22. The trench is etched using standard patterning and etching techniques. Although not illustrated in FIG. 3a, a first doped region is created in the silicon device layer 21 using standard implantation techniques.

[0086] Next, as shown in FIG. 3b, a lower mask layer 25 comprising silicon nitride is deposited on top of the silicon device layer 21 and in the trench 24.

[0087] An opening 26 is then etched in the lower mask layer 25 to the silicon device layer 21 (see e.g. FIG. 3c). Again, opening 26 is etched using standard patterning and etching techniques. This opening 26 provides a point of exposed silicon from which a type III-V semiconductor layer will later be grown. The opening 26 is etched in the lower mask layer 25 in a region which will be laterally offset from a MOS capacitor region having a p-i-n junction of the modulator 1.

[0088] As shown in FIG. 3d, a sacrificial layer 27 is then deposited on top of the lower mask layer 25, and in the opening 26. The sacrificial layer 27 may comprise aluminium oxide or amorphous silicon, for example.

[0089] Next, a portion of the sacrificial layer 27 is etched to the lower mask layer 25. Specifically, as shown in FIG. 3e, a portion of each side of the sacrificial layer 27 is etched to reveal the lower mask layer 25 underneath. Furthermore, a portion of the sacrificial layer 27 positioned in the opening 26 in the lower mask layer 25 is etched to reveal a portion of the silicon device layer 21. In alternative embodiments, the portion of the sacrificial layer 27 positioned in the opening 26 in the lower mask layer 25 is not etched, so that the sacrificial layer 27 extends across the opening 26 and the silicon device layer 21 is not exposed. Again, standard patterning and etching techniques are used.

[0090] As shown in FIG. 3f, an upper mask layer 28 is then deposited on top of the sacrificial layer 27 and in the opening 26. Accordingly, the upper and lower mask layers 25, 28 surround the sacrificial layer 27.

[0091] Next, an opening 29 is etched in the upper mask layer 28 to the sacrificial layer 27 (see e.g. FIG. 3g). Again, standard patterning and etching techniques are used.

[0092] The sacrificial layer 27 is then selectively etched, whilst maintaining the upper and lower mask layers 25, 28. Accordingly, a cavity 30 is formed between the upper and lower mask layers 25, 28; beneath the upper mask layer 28, and above the lower mask layer 25 (see e.g. FIG. 3h). The cavity 30 extends from the silicon device layer 21 at the opening 26 in the lower mask layer 25, between the upper and lower mask layers 25, 28 to the opening 29 in the upper mask layer 28.

[0093] As shown in FIG. 3i, a type III-V semiconductor region 31 is then epitaxially grown in the cavity 30 from the exposed silicon device layer 21 at the opening 26 in the lower mask layer 25. Standard epitaxial growing techniques are used. The type III-V semiconductor region 31 grows to fill the shape of the cavity 30 and is thus limited by the upper and lower mask layers 25, 28. In this example embodiment, the type III-V semiconductor region 31 is InP, GaAs, InGaAs or InGaAsP, although other type III-V materials may also be used.

[0094] The second doped region of the type III-V semiconductor region 31 is created by in situ doping using standard dopant techniques. In alternative embodiments, the second doped region of the semiconductor region 31 may be created using standard implantation and/or diffusion techniques. If the first doped region is n-doped, the second doped region is p-doped, and vice versa.

[0095] Next, a waveguide structure 32 is formed by etching a portion of the unneeded type III-V semiconductor region 31, the upper mask layer 28, and a portion of the lower mask layer 25. The waveguide structure 32 comprises a MOS capacitor region having the p-i-n junction. Again, standard etching techniques are used. As shown in FIG. 3j, the portion of the type III-V semiconductor region 31 adjacent to the silicon device layer 21 at the opening 26 is etched in this step. Accordingly, any defects in the type III-V semiconductor region 31 are removed.

[0096] An isolation layer 33 is then deposited on top of the waveguide structure 32. In the example embodiment shown in FIG. 3k, the isolation layer 33 is an isolation oxide, such as silicon dioxide.

[0097] Finally, the isolation layer 33 is etched at two openings to the silicon device layer 21 and to the type III-V semiconductor region 31 respectively, and electrical contacts 34 are deposited through the isolation layer 33 (see e.g. FIG. 3l). The electrical contacts 34 are applied to regions of the silicon device layer 21 and the type III-V semiconductor region 31 that are laterally offset from the MOS capacitor region of the waveguide structure 32. The remaining portion of the lower mask layer 25 forms the insulator layer of the p-i-n junction in the MOS capacitor region.

[0098] The resulting modulator 1 is shown in FIG. 1. The silicon device layer 21 of the SOI substrate 20 extends horizontally, parallel and contiguous with the BOX layer 22. The insulator layer 25 (formed by the lower mask layer) has a “Z” shape formed by a first upper horizontally-extending portion 25a, a second vertically-extending portion 25b, and a third lower horizontally-extending portion 25c. Advantageously, this “Z” shape increases the surface area in which charge can accumulate. This correspondingly increases the modulation efficiency, whilst not affecting the size of the optical mode.

[0099] The first horizontally-extending portion 25a of the insulator layer 25 extends above and contiguous with the silicon device layer 21, and specifically above the first doped region of the silicon device layer 21. The second vertically-extending portion 25b of the insulator layer 25 extends vertically away from the BOX layer 22 to the first upper horizontally-extending portion 25a of the insulator layer 25. Accordingly the insulator layer 25 forms both a vertical junction (i.e. at the second vertically-extending portion 25b) and a horizontal junction (i.e. at the first upper horizontally-extending portion 25a) with the silicon device layer 21, and specifically the first doped region of the silicon device layer 21. In a variation, not shown, the insulator layer 25 extends obliquely across the waveguide structure 32. For example, the insulator layer 25 may extend at an angle greater than 0° and less than 90°. This extension may be a linear one, in contrast to the “Z” shaped insulator layer shown in FIG. 1.

[0100] The third lower horizontally-extending portion 25c of the insulator layer 25 extends horizontally from a lower end of the second vertically-extending portion 25b of the insulator layer 25 on top of, and contiguous with, the BOX layer 22.

[0101] Similarly to the insulator layer 25, the type III-V semiconductor region 31 also has a “Z” shape formed by a first upper horizontally-extending portion 31a, a second vertically-extending portion 31b, and a third horizontally-extending portion 31c.

[0102] The first upper horizontally-extending portion 31a of the type III-V semiconductor region 31 extends horizontally on top of, and is contiguous with, the first upper horizontally-extending portion 25a of the insulator layer 25. The third lower horizontally-extending portion 31c of the type III-V semiconductor region 31 extends horizontally on top of, and is contiguous with, the third lower horizontally-extending portion 25c of the insulator layer 25. The second vertically-extending portion 31b of the type III-V semiconductor region 31 extends vertically between the first upper horizontally-extending portion 31a and the third lower horizontally-extending portion 31c of the type III-V semiconductor region 31.

[0103] Accordingly, the first doped region of the silicon device layer 21 is laterally (i.e. horizontally) spaced from the second doped region of the second vertically-extending portion 31b of the type III-V semiconductor region 31 by the second vertically-extending portion 25b of the insulator layer 25. This forms a lateral MOS capacitor region.

[0104] The first doped region of the silicon device layer 21 is also vertically spaced from the first upper horizontally-extending portion 31a of the type III-V semiconductor region 31 by the first upper horizontally-extending portion 25a of the insulator layer 25. Therefore, modulator 1 has a p-i-n junction which extends both perpendicularly and parallel to the BOX layer.

[0105] In the example embodiment shown in FIG. 1, the insulator layer 25, first doped region of the silicon device layer 21, and the second doped region of the type III-V semiconductor region 31 are formed from different materials. Specifically, the insulator layer 25 comprises silicon nitride, the silicon device layer 21 has a Si(100) crystalline orientation, and the type III-V semiconductor region 31 comprises InP or InGaAsP.

[0106] A MOS capacitor-type optical modulator 100 and its methods of fabrication according to a second embodiment are described below with reference to FIGS. 2, 4a-4l and 5a-5g. The modulator 100 comprises a SOI substrate 120.

[0107] According to a first method of fabricating the MOS capacitor-type optical modulator, and as shown in FIG. 4a, the silicon-on-insulator substrate 120 is initially provided comprising a silicon base layer 123, a buried silicon dioxide (BOX) layer 122 and a silicon device layer 121. The silicon device layer 121 has a Si(100) crystalline structure. A trench 124 is etched in the silicon device layer 121 to the BOX layer 122. The trench is etched using standard patterning and etching techniques. Although not illustrated in FIG. 4a, a first doped region is created within the silicon device layer 121 using standard implantation techniques.

[0108] Next, as shown in FIG. 4b (and similarly to the step illustrated in FIG. 3b with reference to the first embodiment) a lower mask layer 125 comprising silicon nitride is deposited on top of the silicon device layer 121 and in the trench 124.

[0109] An opening 126 is then etched in the lower mask layer 125. However, in contrast to the corresponding step in the first embodiment, the opening 126 in the lower mask layer 125 extends to the silicon device layer 121 and the BOX layer 122 in the trench 124. Again, opening 126 is etched using standard patterning and etching techniques. This opening 126 provides a point of exposed silicon from which a type III-V layer will subsequently be grown. The opening 126 is etched in the lower mask layer 125 in a region which will be laterally offset from a MOS capacitor region having a p-i-n junction of the modulator 100.

[0110] As shown in FIG. 4d, a sacrificial layer 127 is then deposited on top of the lower mask layer 125, in the trench 124 and in the opening 126. The sacrificial layer 127 may comprise aluminium oxide or amorphous silicon.

[0111] Next, the sacrificial layer 127 is planarized by Chemical Mechanical Planarization (CMP) so that the sacrificial layer 127 is only present in the trench 124 (see e.g. FIG. 4e). Accordingly, the sacrificial layer 127 in the trench 124 is levelled to the lower mask layer 125.

[0112] As shown in FIG. 4f, an upper mask layer 128 is then deposited on top of the sacrificial layer 127 such that the upper and lower mask layers 125, 128 surround the sacrificial layer 127.

[0113] Similarly to the step illustrated in FIG. 3g with reference to the first embodiment, an opening 129 is etched in the upper mask layer 128 to the sacrificial layer 127. Again standard patterning and etching techniques are used.

[0114] The sacrificial layer 127 is then selectively etched, whilst maintaining the upper and lower mask layers 125, 128. Accordingly, a cavity 130 is formed in the trench 124 between the upper and lower mask layers 125, 128. The cavity 130 is formed beneath the upper mask layer 128.

[0115] As shown in FIG. 4i, a type III-V semiconductor region 131 is then epitaxially grown in the cavity 130 from the exposed silicon device layer 121 at the opening 126 in the lower mask layer 125. Standard epitaxial growing techniques are used. The type III-V semiconductor region 131 grows to fill the shape of the cavity 130 and is thus limited by the upper and lower mask layers 125, 128. In this example embodiment, the type III-V semiconductor region 131 is InP or InGaAsP. The second doped region of the type III-V semiconductor region 131 is created by in situ doping using standard dopant techniques. If the first doped region is n-doped, the second doped region is p-doped, and vice versa.

[0116] Next, a waveguide structure 132 is formed by etching a portion of the unneeded type III-V semiconductor region 131, the upper mask layer 128 and a portion of the lower mask layer 125. The waveguide structure 132 comprises a MOS capacitor region having the p-i-n junction. Standard etching techniques are used. The portion of the type III-V semiconductor region 131 adjacent to the silicon device layer 121 at the opening 126 is positioned away from the p-i-n junction of the MOS capacitor region. Accordingly, any defects in the type III-V semiconductor region 131 are positioned away from the p-i-n junction and so have a reduced affect on the MOS capacitor region.

[0117] Similarly to the step illustrated in FIG. 3k with reference to the first embodiment, an isolation layer 133 is then deposited on top of the waveguide structure 132. In the example embodiment shown in FIG. 4k, the isolation layer 133 is an isolation oxide, such as silicon dioxide.

[0118] Finally, the isolation layer 133 is etched at two openings to the silicon device layer 121 and to the type III-V semiconductor region 131 respectively, and electrical contacts 134 are deposited through the isolation layer 133 (see e.g. FIG. 4l). The electrical contacts 134 are applied to regions of the silicon device layer 121 and the type III-V semiconductor region 131 that are laterally offset from the MOS capacitor region of the waveguide structure 132. The remaining portion of the lower mask layer 125 forms the insulator layer of the p-i-n junction in the MOS capacitor region.

[0119] The resulting modulator 100 is shown in FIG. 2. Similarly to the first embodiment shown in FIG. 1, the insulator layer 125 of modulator 2 (formed by the lower mask layer) has a “Z” shape formed by a first upper horizontally-extending portion 125a, a second vertically-extending portion 125b, and a third lower horizontally-extending portion 125c.

[0120] Unlike the first embodiment shown in FIG. 1, the silicon device layer 121 of the SOI substrate 120 shown in FIG. 2 comprises a first horizontally-extending portion 121a and a second vertically-extending portion 121b. The first horizontally-extending portion 121 extends parallel to, and on top of, the BOX layer 122, and the second vertically-extending portion 121b extends vertically away from the BOX layer 122.

[0121] The first horizontally-extending portion 125a of the insulator layer 125 extends horizontally above the vertically-extending portion 121b of the silicon device layer 121. The second vertically-extending layer 125b of the insulator layer 125 extends vertically and contiguously with the vertically-extending portion 121b of the silicon device layer 121. The third lower horizontally-extending portion 125c of the insulator layer 125 extends horizontally from a lower end of the second vertically-extending portions 125b of the insulator layer 125 on top of the BOX layer 122.

[0122] Unlike the first embodiment shown in FIG. 1, the type III-V semiconductor region 131 does not have a “Z” shape. Instead, type IIIV semiconductor region 131 comprises a first vertically-extending portion 131a, a second horizontally-extending portion 131b, and a third vertically-extending portion 131c. The first vertically-extending portion 131a of the type III-V semiconductor region 131a extends vertically and contiguously with the vertically-extending portion 125b of the insulator layer 125. Accordingly, the second vertically-extending portion 125b of the insulator layer 125 laterally (i.e. horizontally) spaces the second vertically-extending portion 121b of the silicon device layer 121, and the first vertically-extending portion 131a of the type III-V semiconductor region 131. A first doped region is formed in the second vertically-extending portion 121b of the silicon device layer 121, and a second doped region is formed in the first vertically-extending portion 131a of the type III-V semiconductor region 131, to form a lateral MOS capacitor region with a p-i-n junction which extends parallel to the BOX layer.

[0123] In the example embodiment shown in FIG. 2, the insulator layer 125, first doped region of the silicon device layer 121, and the second doped region of the type III-V semiconductor region 131 are formed from different materials. Specifically, the insulator layer 125 comprises silicon nitride, the silicon device layer has a Si(100) crystalline orientation, and the type III-V semiconductor region 131 comprises InP, GaAs, InGaAs or InGaAsP.

[0124] An alternative method of fabrication of the MOS capacitor-type optical modulator 100 shown in FIG. 2 is described below with reference to FIGS. 5a-5g.

[0125] As shown in FIG. 5a, a silicon-on-insulator substrate 120 is initially provided comprising a silicon base layer 123, a buried silicon dioxide (BOX) layer 122 and a silicon device layer 121. The silicon device layer 121 has a Si(100) crystalline structure. A trench 124 is etched in the silicon device layer 121 to the BOX layer 122. The trench is etched using standard patterning and etching techniques. Although not illustrated in FIG. 5a, a first doped region is created within the silicon device layer 121 using standard implantation techniques.

[0126] Next, as shown in FIG. 5b, a lower mask layer 125 comprising silicon nitride is deposited on top of the silicon device layer 121 and in the trench 124. The lower mask layer 125 will form the insulator layer 125 of the MOS capacitor-type optical modulator 100, shown in FIG. 2.

[0127] An opening 126 is then etched in the lower mask layer 125. Similarly to the step illustrated in FIG. 4c, the opening 126 in the lower mask layer 125 extends to the silicon device layer 121 and the BOX layer 122 in the trench 124. Again, opening 126 is etched using standard patterning and etching techniques. This opening 126 provides a point of exposed silicon from which a type III-V layer will subsequently be grown. The opening 126 is etched in the lower mask layer 125 in a region which will be laterally offset from a MOS capacitor region having a p-i-n junction of the modulator 100.

[0128] In contrast to the method step illustrated in FIG. 4d where a sacrificial layer is deposited, in FIG. 5d, a type III-V semiconductor region 131 is selectively and epitaxially grown from the exposed silicon device layer 121 in the opening 126. The type III-V semiconductor region 131 grows outwardly from the opening 126 to at least fill the trench 124.

[0129] Then, the type III-V semiconductor region 131 is planarized by CMP so that the semiconductor region 131 is only present in the trench 124 (see e.g. FIG. 5e). In this way, the semiconductor region 131 in the trench 124 is levelled to the lower mask layer 125.

[0130] A waveguide structure 132 is formed by etching a portion of the unneeded type III-V semiconductor region 131, a portion of the lower mask layer 125 and a portion of the silicon device layer 121. An isolation layer 133 is deposited on top of the waveguide structure 132 (FIG. 5f).

[0131] Finally, the isolation layer 133 is etched at two openings to the silicon device layer 121 and to the type III-V semiconductor region 131 respectively, and electrical contacts 134 are deposited through the isolation layer (FIG. 5g).

[0132] While the invention has been described in conjunction with the exemplary embodiments described above, many equivalent modifications and variations will be apparent to those skilled in the art when given this disclosure. Accordingly, the exemplary embodiments of the invention set forth above are considered to be illustrative and not limiting. Various changes to the described embodiments may be made without departing from the spirit and scope of the invention.