Hall sensor structure
11437569 · 2022-09-06
Assignee
Inventors
- Maria-Cristina Vecchi (Freiburg, DE)
- Reinhard Erwe (Freiburg, DE)
- Martin Cornils (Freiburg, DE)
- Kerwin Khu (Freiburg, DE)
Cpc classification
H10B61/00
ELECTRICITY
H10N59/00
ELECTRICITY
International classification
Abstract
A Hall sensor structure comprising a semiconductor body of a first conductivity type, a well region of a second conductivity type extending from a top side of the semiconductor body into the semiconductor body, at least three first semiconductor contact regions of the second conductivity type, each extending from a top side of the well region into the well region, at least one second semiconductor contact region of a second conductivity type, wherein the first semiconductor contact regions are spaced apart from one another and from an edge of the well region, a metallic connection contact layer is arranged on each first semiconductor contact region, the at least one second semiconductor contact region extends along the top side of the semiconductor body at least partially around the well region.
Claims
1. A Hall sensor structure comprising: a semiconductor body of a first conductivity type; a well region of a second conductivity type extending from a top side of the semiconductor body into the semiconductor body; at least three first semiconductor contact regions of the second conductivity type, each extending from a top side of the well region into the well region, the first semiconductor contact regions each being spaced apart from one another; at least one second semiconductor contact region of the first conductivity type, extending from the top side of the well region into the well region; and a metallic connection contact layer arranged on each first semiconductor contact region, wherein the at least one second semiconductor contact region extends along a top side of the semiconductor body at least partially around the well region, wherein the well region and the second semiconductor contact region overlap in an overlap region that extends from the top side of the semiconductor body into the semiconductor body, the overlap region being formed along and overlapping an edge of the well region, and wherein the second semiconductor contact region extends along at least one edge and at most along three edges of the well region.
2. The Hall sensor structure according to claim 1, wherein the overlap region along the top side of the semiconductor body has a width of at least 0.1 μm or a width of 1-2 μm.
3. The Hall sensor structure according to claim 1, wherein all second semiconductor contact regions contained in the Hall sensor structure extend along at least 50% or at least 75% or at least 95% of a perimeter of the well region.
4. The Hall sensor structure according to claim 1, wherein the well region has a rectangular top side.
5. The Hall sensor structure according to claim 1, wherein the Hall sensor structure has a dielectric isolation layer, wherein the isolation layer comprises an oxide and covers a top side of the semiconductor body and a top side of the well region, and wherein the oxide has a thickness of at least 1 nm or a thickness in a range between 3 nm and 30 nm.
6. The Hall sensor structure according to claim 5, wherein the Hall sensor structure has a polysilicon layer, wherein the polysilicon layer covers part of a top side of the isolation layer, and wherein the polysilicon layer has a thickness of 0.1-0.8 μm or 0.4-0.6 μm.
7. The Hall sensor structure according to claim 6, wherein the polysilicon layer has a distance of at least 0.2 μm or at least 0.4 μm from each first semiconductor contact region.
8. The Hall sensor structure according to claim 1, wherein the first conductivity type is n-type and the second conductivity type is p-type or wherein the first conductivity type is p-type and the second conductivity type is n-type.
9. The Hall sensor structure according to claim 1, wherein the first semiconductor contact regions each have a dopant concentration of 5.Math.10.sup.18 N/cm.sup.3.
10. The Hall sensor structure according to claim 1, wherein the well region has a dopant concentration of 5.Math.10.sup.14-5.Math.10.sup.16 N/cm.sup.3.
11. The Hall sensor structure according to claim 1, wherein at least the areas of the well region, areas extending between the first semiconductor contact regions, or the entire well region is free of threshold voltage implantation.
12. The Hall sensor structure according to claim 1, wherein the second semiconductor contact region is electrically connected via a channel region formed outside the well region.
13. The Hall sensor structure according to claim 1, wherein the first semiconductor contact regions are each spaced apart from an edge of the well region.
14. The Hall sensor structure according to claim 1, wherein the second semiconductor contact regions each have a dopant concentration of 5.Math.10.sup.18 N/cm.sup.3.
15. The Hall sensor structure according to claim 1, wherein the second semiconductor contact regions extend from a surface of the semiconductor body less than 0.5 μm deep into the semiconductor body.
16. The Hall sensor structure according to claim 1, wherein the second semiconductor contact regions are at least partially or completely covered by an isolation layer, formed as a gate oxide, and wherein a polysilicon layer is arranged on the isolation layer.
17. The Hall sensor according to claim 1, further comprising a spacer oxide formed on ends of the polysilicon layer to space the polysilicon layer from the metallic connection layer.
18. The Hall sensor according to claim 1, wherein the metallic connection layer extends along an entire surface of each of the at least three first semiconductor contact regions.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
(1) The present invention will become more fully understood from the detailed description given hereinbelow and the accompanying drawings which are given by way of illustration only, and thus, are not limitive of the present invention, and wherein:
(2)
(3)
(4)
(5)
DETAILED DESCRIPTION
(6) The illustration of
(7) A metallic connection contact layer K1 is in each case formed flat on a top side of each first semiconductor contact region HK1 in order to form active electrical connections.
(8) The remaining top side of substrate SUB is covered by an isolation layer ISO, e.g., by a gate oxide. A polysilicon layer POL, e.g., silicided polysilicon, is formed on a top side of isolation layer ISO at a distance from the metallic connection contact layers K1. The distances between polysilicon layer POL and connection contact layers K1 each comprise a spacer oxide ISO2.
(9) In addition, a, for example, p-doped second semiconductor contact region HK2 is formed in substrate SUB, wherein second semiconductor contact region HK2 extends from the top side of substrate SUB into substrate SUB and along the top side around well region W. Second semiconductor contact region HK2 is arranged next to well region W such that it overlaps well region W. The overlap region U formed by the overlap has a width B1.
(10) A plan view of a further embodiment is shown in the illustration of
(11) Metallic contact layers K1 are formed in areas on first semiconductor contact regions HK1. In particular, if the polysilicon layer is sufficiently silicided, it is not absolutely necessary to form metal contact layers K1 over the entire surface.
(12) Well region W has a rectangular top side, wherein second semiconductor contact region HK2 completely surrounds the top side of well region W, therefore, extends along all four sides of the top side of well region W.
(13) In addition, second semiconductor contact region HK2 has a channel region KAW. Channel region KAW extends outward from second semiconductor contact region HK2 to form a connection contact layer K2.
(14) A cross section of a further embodiment is shown in the illustration in
(15) Only substrate SUB is shown without the gate oxide and polysilicon layer and without metal contact layers.
(16) Five first semiconductor contact regions HK1, each spaced apart from one another, are arranged in well region W in the substrate.
(17) A plan view of a further embodiment is shown in the illustration of
(18) In the illustrated embodiment, Hall sensor structure HAL comprises five first semiconductor contact regions HK1 and two second semiconductor contact regions HK2, wherein second semiconductor contact regions HK2 extend along two mutually opposite sides of the rectangular top side of well region W.
(19) The invention being thus described, it will be obvious that the same may be varied in many ways. Such variations are not to be regarded as a departure from the spirit and scope of the invention, and all such modifications as would be obvious to one skilled in the art are to be included within the scope of the following claims.