MEMS PIEZOELECTRIC DEVICE AND CORRESPONDING MANUFACTURING PROCESS

Abstract

A MEMS piezoelectric device includes a monolithic semiconductor body having first and second main surfaces extending parallel to a horizontal plane formed by first and second horizontal axes. A housing cavity is arranged within the monolithic semiconductor body. A membrane is suspended above the housing cavity at the first main surface. A piezoelectric material layer is arranged above a first surface of the membrane with a proof mass coupled to a second surface, opposite to the first surface, along the vertical axis. An electrode arrangement is provided in contact with the piezoelectric material layer. The proof mass causes deformation of the piezoelectric material layer in response to environmental mechanical vibrations. The proof mass is coupled to the membrane by a connection element arranged, in a central position, between the membrane and the proof mass in the direction of the vertical axis.

Claims

1. A process for manufacturing a MEMS piezoelectric device, comprising: forming a buried cavity within a wafer of semiconductor material, said buried cavity defining from said wafer a membrane positioned between an inner surface of said buried cavity and a top surface of said wafer and further defining from said wafer a connection element extending from a bottom surface of the membrane; forming a piezoelectric material layer above a top surface of said membrane; forming an electrode arrangement in contact with the piezoelectric material layer; and etching an opening in said wafer from a back surface of said wafer to reach said buried cavity and define from the wafer a proof mass coupled to the membrane through the connection element and surrounded by said opening.

2. The process of claim 1, wherein the top and bottom surfaces of said membrane extend parallel to a horizontal plane and wherein the connection element extends perpendicular to said horizontal plane.

3. The process of claim 2, wherein the buried cavity delimits a first width of the connection element parallel to the horizontal plane, and wherein the opening delimits a second width of the proof mass parallel to the horizontal plane, and wherein the second width is greater than the first width.

4. The process of claim 1, wherein said connection element is arranged centrally with respect to said membrane.

5. The process of claim 11, wherein forming the buried cavity comprises: forming an etch mask on the top surface of said wafer, a geometry of said etch mask configured to define a geometry and dimensions of said membrane and of said connection element; using the etch mask to form trenches within said wafer which delimit walls of semiconductor material; epitaxially growing, starting from said walls a closing layer of semiconductor material, said closing layer closing at a top said trenches and enabling formation of said membrane; and carrying out a thermal treatment such as to cause migration of the semiconductor material of the walls and form the buried cavity and at a same time defining said connection element and said membrane.

6. The process of claim 5, wherein forming said buried cavity further comprises forming a buried channel as a lateral prolongation of said buried cavity.

7. The process of claim 6, further comprising: forming an access trench through a surface portion of said wafer to reach the buried channel; and carrying out a thermal oxidation within the buried cavity through the access trench to form an internal dielectric region which coats inner walls of the buried cavity and of the access trench.

8. The process of claim 1, further comprising forming a release opening in fluid communication with the opening and arranged laterally to the membrane and separating said membrane from said wafer at said top surface of the wafer.

9. The process of claim 8, wherein said release opening defines a constraint of said membrane to said wafer.

10. A process for manufacturing a MEMS piezoelectric device, comprising: providing a wafer of semiconductor material having a first main surface and a second main surface, the first and second main surfaces that are opposite to one another along a vertical axis; forming a buried cavity within said wafer, said buried cavity defining from said wafer a membrane positioned between an inner surface of said buried cavity and the first main surface and further defining from said wafer a connection element extending from a bottom surface of the membrane; forming a piezoelectric material layer above the first main surface at said membrane; forming an electrode arrangement in contact with the piezoelectric material layer; and etching an opening in said wafer from a back surface of said wafer to define a proof mass coupled to the bottom surface of the membrane by said connection element, said proof mass configured to deform the membrane in response to environmental mechanical vibrations; wherein said connection element is arranged in a central position between said membrane and said proof mass in the direction of said vertical axis.

11. The process of claim 10, wherein the buried cavity delimits a first width of the connection element perpendicular to the vertical axis, and wherein the opening delimits a second width of the proof mass perpendicular to the vertical axis, and wherein the second width is greater than the first width.

12. The process according to claim 10, wherein forming the buried cavity comprises defining a geometry and size of each of said membrane and said connection element.

13. The process of claim 10, wherein forming the buried cavity comprises: forming an etch mask on the first main surface of said wafer, a geometry of said etch mask configured to define a geometry and dimensions of said membrane and of said connection element; using the etch mask to form trenches within said wafer which delimit walls of semiconductor material; epitaxially growing, starting from said walls a closing layer of semiconductor material, said closing layer closing at a top said trenches and enabling formation of said membrane; and carrying out a thermal treatment such as to cause migration of the semiconductor material of the walls and form the buried cavity and at a same time defining said connection element and said membrane.

14. The process of claim 13, wherein forming said buried cavity further comprises forming a buried channel as a lateral prolongation of said buried cavity.

15. The process of claim 14, further comprising: forming an access trench through a surface portion of said wafer to reach the buried channel; and carrying out a thermal oxidation within the buried cavity through the access trench to form an internal dielectric region which coats inner walls of the buried cavity and of the access trench.

16. The process of claim 10, further comprising forming a release opening in fluid communication with the opening and arranged laterally to the membrane and separating said membrane from said wafer at said first main surface of the wafer.

17. The process of claim 16, wherein said release opening defines a constraint of said membrane to said wafer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0032] For a better understanding of the present invention, preferred embodiments thereof are now described, purely by way of non-limiting example and with reference to the attached drawings, wherein:

[0033] FIGS. 1A and 1B are schematic cross-sectional views of a MEMS piezoelectric structure, in different operating conditions;

[0034] FIG. 2A is a schematic cross-sectional view of a portion of a micromechanical structure of a MEMS piezoelectric device of a known type;

[0035] FIG. 2B is a top schematic perspective view of the micromechanical structure of FIG. 2A;

[0036] FIG. 3A is a cross-sectional view of a micromechanical structure of a MEMS piezoelectric device according to an embodiment of the present solution;

[0037] FIG. 3B is a schematic top perspective view of the micromechanical structure of FIG. 3A;

[0038] FIG. 4 is a schematic cross-sectional view of a portion of the micromechanical structure of FIG. 3A;

[0039] FIGS. 5, 6A-6B, 7, 8A-8C, 9-14 and 15 are schematic cross-sectional views, or schematic plan views, of the micromechanical structure of FIG. 3A in successive steps of a corresponding manufacturing process;

[0040] FIGS. 16 and 17A are schematic top perspective views regarding different embodiments of the micromechanical structure;

[0041] FIG. 17B is a schematic bottom perspective view of the micromechanical structure of FIG. 17A;

[0042] FIGS. 18 and 19 are schematic plan views of further embodiments of the micromechanical structure;

[0043] FIG. 20 is a block diagram of a system for harvesting electrical energy that uses the MEMS piezoelectric device as a energy micro-generator; and

[0044] FIG. 21 shows a portable electronic apparatus in which the electrical-energy-harvesting system of FIG. 20 may be used.

DETAILED DESCRIPTION

[0045] As shown in FIGS. 3A and 3B, a MEMS piezoelectric device 20 comprises a monolithic body 21 of semiconductor material, in particular silicon, having a front surface 21a and a rear surface 21b that lie in a horizontal plane xy defined by a first horizontal axis x and by a second horizontal axis y.

[0046] The monolithic body 21 has at the center a housing cavity 22, which extends from the rear surface 21b as far as a membrane 23, which is suspended over the housing cavity 22 at the front surface 21a of the monolithic body 21; in plan view, the membrane 23 and the underlying housing cavity 22 may, for example, have a circular, square, rectangular, or generically polygonal shape.

[0047] The MEMS piezoelectric device 20 further comprises a proof mass 24, arranged within the housing cavity 22 and coupled to the membrane 23 by a connection, or support, element 25. This connection element 25 is arranged between a top surface 24a of the proof mass 24 and a bottom surface 23b of the membrane 23, which faces the top surface 24a.

[0048] In one embodiment, the connection element 25 has a column configuration and is connected to the membrane 23 at a geometrical center thereof.

[0049] The housing cavity 22 surrounds the proof mass 24 laterally (along the first and second horizontal axes x, y) and at the top (a portion of the housing cavity 22 is in fact arranged between the front surface 24a of the proof mass 24 and the membrane 23); the proof mass 24 has a rear surface 24b arranged, in the embodiment illustrated, at the same level as the rear surface 21b of the monolithic body 21.

[0050] In particular (see also the schematic representation of FIG. 4), D1 once again designates a lateral extension of the proof mass 24 (parallel to the front surface 21a of the monolithic body 21 in the horizontal plane xy, for example along the first horizontal axis x), and D2 designates a corresponding main extension of the membrane 23 along the same first horizontal axis x.

[0051] According to one aspect, as is evident from examination of FIG. 3A and also of FIG. 4, sizing of the proof mass 24 is in this case independent of sizing of the membrane 23 (the same membrane designed, as described hereinafter, to carry piezoelectric elements for detecting deformations). The dimension D1 may in this case even advantageously be approximately equal to the dimension D2.

[0052] Furthermore, a corresponding dimension of the connection element 25 (in this case, along the first horizontal axis x), designated by D3, is smaller than the dimension D1 of the proof mass 24 (for instance, much smaller, in the example illustrated). In other words, only a central portion of the proof mass 24, with extension much shorter than the entire lateral extension D1 of the proof mass 24 along the first horizontal axis x, is connected to the membrane 23 via the connection element 25.

[0053] The MEMS piezoelectric device 20 further comprises, on the front surface 21a of the monolithic body 21 and in general above the membrane 23: a first dielectric layer 27, for example an oxide layer, arranged on the front surface 21a of the monolithic body 21; a service layer 28, for example a polysilicon layer, the function of which will be clarified hereinafter with reference to the manufacturing process (see FIG. 10); a second dielectric layer 29, which is also, for example, an oxide layer, arranged above the service layer 28 and the first dielectric layer 27; a piezoelectric material layer 30, for example PZT, arranged on the second dielectric layer 29, vertically in an area corresponding to the membrane 23; an electrode arrangement 32, arranged on, and in contact with, the piezoelectric material layer 30; in particular, the electrode arrangement 32 comprises at least one first set of electrodes 33a and one second set of electrodes 33b, which are arranged above the membrane 23, on opposite sides with respect to the connection element 25 in the horizontal plane xy, for example on opposite sides along the first horizontal axis x, and are designed to enable detection of the deformations of the same membrane 23; a passivation layer 35, for example of silicon oxide or silicon nitride, arranged on the electrode arrangement 32, the piezoelectric material layer 30, and the second dielectric layer 29; and electrical contact elements 36 (the so-called “vias”), which are arranged on the passivation layer 35, and further extend, at least in part, through the same passivation layer 35, for electrically contacting the electrode arrangement 32 and in particular the first and second sets of electrodes 33a, 33b, and in this way enable detection of an electrical signal and execution (as described more fully hereinafter), for example, of energy-harvesting operations.

[0054] During operation, the proof mass 24 displaces in response to mechanical vibrations, thus causing deformation of the membrane 23 and of the associated layer of piezoelectric material 30. This deformation is detected by the first and second sets of electrodes 33a, 33b, which supply, through the electrical contacts 36, respective electrical signals for generation of electrical energy starting from the aforesaid vibrations.

[0055] As illustrated in FIG. 3B, a release opening 38 may be provided, laterally to the membrane 23 and the proof mass 24, in the example having opening portions extending along the first horizontal axis x and arranged laterally to the proof mass 24 with respect to the horizontal axis y. As will be discussed more fully hereinafter, this release opening 38 defines the mode of constraint of the membrane 23 to the monolithic body 21, in the example being of the doubly clamped type (given that the membrane 23 is coupled to the monolithic body 21 at two sides thereof that extend along the second horizontal axis y).

[0056] Furthermore, in a way not illustrated herein (but that will be evident to a person skilled in the field), a supporting body may be coupled underneath the monolithic body 21, at the rear surface 21b, with supporting functions (the supporting body having in this case an appropriate cavity in fluid communication with the housing cavity 22 for providing freedom of movement for the proof mass 24).

[0057] A description of a possible process for manufacturing the MEMS piezoelectric device 20 is now provided.

[0058] In an initial step of the manufacturing process (see FIG. 5), a wafer 41 of semiconductor material is provided, for example of monocrystalline silicon, comprising a substrate 42, for example of an N type, and having a front surface 41a and a rear surface 41b.

[0059] The manufacturing process continues with formation of a buried cavity within the wafer 41, with techniques described in detail for example in U.S. Pat. No. 8,173,513 (European Patent 1577656) (incorporated by reference).

[0060] In brief, and as illustrated in FIGS. 6A and 6B (which are not drawn to scale, as likewise the remaining figures), on the front surface 41a of the wafer 41 a resist mask 43 is provided. The mask 43 has, in particular, (see FIG. 6B) an etching area 44, in the example approximately square (but it may also be circular or generically polygonal), and comprises a plurality of mask portions 43a, for example hexagonal, which define a lattice, for example a honeycomb lattice.

[0061] As will emerge clearly hereinafter, the etching area 44 of the mask 43 corresponds to the area that will be occupied by the housing cavity 22 and has an extension corresponding to the extension of the membrane 23 (the lateral extension of the mask 43 is thus substantially equal to the dimension D2, along first horizontal axis x).

[0062] The mask 43 has a central portion 43′, for example having a square or circular or generically polygonal shape in plan view, which corresponds to the positioning of the connection element 25, which in the example also has a square or circular or generically polygonal shape in plan view. In particular, the lateral extension of the central portion 43′ of the mask 43 determines the extension D3 of the connection element 25, along first horizontal axis x.

[0063] Furthermore, the mask 43 has a lateral prolongation 45, which is arranged at a central axis of the same mask 43 and extends, in the example, along the second horizontal axis y.

[0064] Then (see FIG. 7, which, as FIG. 6A, represents only a small portion of the wafer 41 at an enlarged scale, for reasons of clarity of illustration), using mask 43, an anisotropic chemical etching of the substrate 42 is performed, following upon which trenches 46 are formed, which communicate with one another and delimit a plurality of silicon columns 47. In practice, trenches 46 form an open region of a complex shape (corresponding to the lattice of the mask 43) in which the columns 47 (having a shape corresponding to the mask portions 43a) extend.

[0065] Next (see FIG. 8A, which represents a more extensive portion of the wafer 41, as compared to FIGS. 6a and 7), the mask 43 is removed, and an epitaxial growth is carried out in deoxidizing environment (typically, in atmosphere with high concentration of hydrogen, preferably with trichlorosilane —SiHCl.sub.3). Consequently, an epitaxial layer 48 (appearing only in FIG. 8A and hereinafter not distinguished from the substrate 42) grows on the columns 47 and closes at the top the aforesaid open region formed by the trenches 46.

[0066] A thermal annealing step is then carried out, for example for 30 min at 1190° C., preferably in a reducing atmosphere, typically a hydrogen atmosphere.

[0067] The annealing step causes migration of the silicon atoms, which tend to move into a position of lower energy. Consequently, and also thanks to the short distance between the columns 47, the silicon atoms migrate completely from the portions of the columns 47 present within the aforesaid region formed by the trenches 46, and a buried cavity 50 is formed, starting from the same region.

[0068] On the buried cavity 50 a thin silicon layer remains, constituted in part by silicon atoms grown epitaxially and in part by migrated silicon atoms, which forms the membrane 23, which is flexible and may deflect in the presence of external stresses.

[0069] During the same step of the manufacturing process, the connection element 25 is defined within the buried cavity 50, which extends in particular at the center with respect to the membrane 23, between a top inner surface 50a and a bottom inner surface 50b of the buried cavity 50.

[0070] Furthermore, as illustrated in the different cross-section of FIG. 8B and in the corresponding plan view of FIG. 8C (where the lines of section regarding the aforesaid FIGS. 8A and 8B are highlighted), with the same steps of the manufacturing process a buried channel 51 is provided, in the region identified by the lateral prolongation 45 of the mask 43, communicating with the buried cavity 50, laterally thereto (in the example, extending along the second horizontal axis y).

[0071] An access trench 54 is then formed through a surface portion of the substrate 42, to reach the buried channel 51, by means of an etching performed from the front of the wafer 41, starting from the front surface 41a.

[0072] The manufacturing process then continues (FIG. 9) with a step of thermal oxidation within the buried cavity 50 (performed through access trench 54) and on the front surface 41a of the wafer 41, to form the first dielectric layer 27, made, for example, of silicon oxide, SiO.sub.2. Following upon this step, in particular, an internal dielectric region 55a is formed, which coats the inner walls of the buried cavity 50 and the inner walls of the access trench 54.

[0073] A step of deposition, for example of polysilicon, is then carried out (FIG. 10), which leads to formation of the service layer 28 on the wafer 41 and within the access trench 54, for closing the opening previously provided for the oxidation.

[0074] The manufacturing process envisages at this point (FIG. 11) formation of the second dielectric layer 29, on the service layer 28, and then formation, by deposition and subsequent definition, of the piezoelectric material layer 30 on the second dielectric layer 29 (FIG. 12).

[0075] In particular, the layer of piezoelectric material 30 may be formed using the technique known as “sol-gel”, which envisages successive steps of formation of a colloidal solution (sol), which operates as a precursor for the subsequent formation of a continuous inorganic lattice containing an interconnected liquid phase (gel), through reactions of hydrolysis and condensation. Thermal post-treatments of drying and solidification are generally used for eliminating the liquid phase from the gel, promoting further condensation, contributing to formation of the correct crystallographic phase, and enhancing the mechanical and, consequently, piezoelectric properties.

[0076] The piezoelectric material layer 30 is hereinafter defined, so as to have a main lateral extension, along the first horizontal axis x, larger than the dimension D2 of the entire membrane 23, as illustrated in the same FIG. 12.

[0077] The manufacturing process then continues with deposition, on the piezoelectric material layer 30, of an electrode layer, for example of titanium/tungsten (TiW), which is then appropriately shaped, as has been described in detail previously, with reference to FIG. 3A, for the formation of the electrode arrangement 32.

[0078] The passivation layer 35 is then deposited on the electrode arrangement 32 previously provided, and contact openings are formed (FIG. 13) through the same passivation layer 35 and are subsequently filled with a suitable conductive material, for formation of the electrical contact elements 36.

[0079] According to an aspect, see once again FIG. 13, an etch mask 61 is then formed on the rear surface 41b of the wafer 41, for etching of the wafer 41 and formation of back trenches 62, reaching the buried cavity 50 from the back. In particular, this etching is performed with etch-stop on the dielectric region 55a, coating a bottom wall of the buried cavity 50.

[0080] In this step of the manufacturing process, the extension D1 of the proof mass 25 is determined, according to the positioning and dimensions of the back trenches 62. In particular, the back trenches 62 have in sectional view an outer side wall vertically in a position corresponding to the perimeter of the buried cavity 50, and an inner side wall, whose position defines the aforesaid dimension D1.

[0081] It is thus clear that, in the solution described, it is possible to size in a desired way the proof mass 25, in this step of etching from the back of the wafer 41, in a way distinct and separate from the steps of formation and sizing of the membrane 23 (which have been previously carried out).

[0082] The manufacturing process continues (FIG. 14) with etching of the dielectric region 55a within the buried cavity 50, thus defining entirely the housing cavity 22 within the wafer 41.

[0083] According to a further aspect, in a final step of the manufacturing process, the type of constraint may be defined of the membrane 23 to the wafer 41 (or, in a similar way, to the monolithic body 21 that will be obtained after final dicing of the same wafer 41); in this respect, the proposed solution advantageously offers ample freedom of design for adapting to various needs and applications, for example with the possibility of obtaining a solution of a doubly clamped type, of a completely clamped type, or with four points of constraint.

[0084] In detail, as illustrated in FIG. 15 (which corresponds to the top perspective view of FIG. 3B, described previously), a further etching of the wafer 41 may then be carried out (in this case, the embodiment is of a doubly clamped type), for example from the back, starting from the rear surface 41b.

[0085] This etching, which is carried out through the housing cavity 22, involves an edge portion of the membrane 23 and the layers possibly present on the front surface 41a of the wafer 41, in this case the first dielectric layer 27, the service layer 28, and possibly the second dielectric layer 29.

[0086] In particular, the release opening 38 is thus formed, in fluid communication with the housing cavity 22, and comprising in this case (once again referring to the embodiment of a doubly clamped type) a first cavity portion 38a and a second cavity portion 38b, which are arranged alongside the membrane 23, on opposite sides with respect to the second horizontal axis y, and separate the same membrane 23 from the semiconductor material of the wafer 41.

[0087] In this embodiment, the membrane 23 is connected to the wafer 41 at two sides, for example the sides parallel to the first horizontal axis x, and is separated from the wafer 41 itself along the other two sides, in the example the sides parallel to the second horizontal axis y.

[0088] As illustrated in FIG. 16, a different embodiment, which provides a four-point constraint of the membrane 23 to the wafer 41, envisages providing, by means of the etching described previously, two further cavity portions 38c, 38d of the release cavity 38, which are arranged along the sides of the membrane 23 parallel to the second horizontal axis y, laterally on opposite sides of the membrane 23 with respect to the first horizontal axis x.

[0089] Accordingly, the membrane 23 is in this case connected and constrained to the wafer 41 at four vertices thereof (since it has, in the example, a substantially square shape) by connection portions 66a-66d that extend at said vertices, between the membrane 23 and the wafer 41 (as illustrated in the aforesaid FIG. 16).

[0090] FIGS. 17A-17B instead show an embodiment with complete constraint, where the membrane 23 is connected to the wafer 41 along its entire perimeter (in this case, the last etching step, described previously for formation of the release cavity 38, here not present, may thus not be envisaged).

[0091] In any case, the manufacturing process terminates with a step of dicing or sawing of the wafer 41, for definition of the dies, each of which comprises the body of semiconductor material 21 and the corresponding piezoelectric structure.

[0092] As illustrated in FIGS. 18 and 19, which refer, merely by way of example, to a structure with four points of constraint, a further possibility offered by the present solution regards formation of the electrode arrangement 32.

[0093] In particular, as illustrated in FIG. 18, in a possible embodiment, both the first set of electrodes 33a and the second set of electrodes 33b have a comb-fingered configuration, i.e., each comprising a first “comb” and a second “comb” of electrodes, electrically contacted by a respective contact element 36 (in this case, the contact elements 36 being arranged at the four points of constraint).

[0094] Alternatively, as illustrated in FIG. 19, the electrode arrangement 32 may be of a circular type. In this case, the first and second sets of electrodes 33a, 33b comprise a respective plurality of rings of electrodes of increasing diameter that depart concentrically from a respective connection element 69 that terminates at a respective contact element 36 (the contact elements 36 being in this case arranged at two diametrically opposite points of constraint).

[0095] The advantages of the solution described are clear from the foregoing discussion.

[0096] It is underlined, in any case, that it allows to solve the problems highlighted previously afflicting the known solutions for MEMS piezoelectric devices, in particular: using technologies and processes altogether compatible with MEMS-device technologies; having low manufacturing costs and using standard manufacturing processes, with a resulting reduced occupation of area in the integrated implementation (and the possibility of integration with further micromechanical structures, or ASICs); offering ample freedom of design of the proof mass 25, which may in particular have dimensions comparable with the corresponding membrane 23, such as not to require the presence of an additional outer proof mass (in this way, leading to a further reduction of the complexity of production and a marked decrease in defectiveness and costs); and, in general, guaranteeing improved electrical performance, in particular as regards the efficiency in generation of electrical energy starting from mechanical vibrations.

[0097] The aforesaid characteristics render the use of the MEMS piezoelectric device 20 particularly advantageous in an electrical-energy-harvesting system, for use, for example, in a portable electronic apparatus (such as a smartphone), for example of the type represented schematically and by functional blocks in FIG. 20.

[0098] In particular, the energy-harvesting system, designated as a whole by 70, comprises the MEMS piezoelectric device 20, used as transducer for conversion of environmental vibrations into electrical energy, to generate a transduction signal S.sub.TRANSD.

[0099] The energy-harvesting system 70 further comprises: an electrical harvesting interface 71, configured to receive at its input the transduction signal S.sub.TRANSD, appropriately process the same signal, and supply at output a harvesting signal S.sub.IN; a storage capacitor 72, which is connected to the output of the harvesting interface 71 and receives the harvesting signal S.sub.IN, which causes charging thereof and consequent storage of energy; and a voltage regulator, or converter 74, connected to the storage capacitor 72 for receiving at its input the electrical energy stored and generating at its output a regulated signal S.sub.REG, with a suitable value to be supplied to an electric load 75, for its supply or recharging.

[0100] As previously mentioned, the energy-harvesting system 70 may advantageously be used for electrically supplying an electrical or electronic apparatus, which may even be without a battery or provided with a rechargeable battery.

[0101] By way of example, FIG. 21 shows an electronic apparatus 76, in the example of a portable or wearable type, such as a bracelet or a watch, which incorporates the energy-harvesting system 70 for generation of electrical energy by exploiting mechanical vibrations, in this case originated by the movement of the body of the user. The electronic apparatus 76 may advantageously be used in the field of fitness.

[0102] Finally, it is clear that modifications and variations may be made to what has been described and illustrated herein, without thereby departing from the scope of the present invention, as defined in the annexed claims.

[0103] In particular, modifications may be made to the shape or dimensions of one or more of the elements that constitute the MEMS piezoelectric device 20; for example, according to the requirements of application and design of the MEMS piezoelectric device 20, the central connection element 25 may have a different shape or a different extension (in the limits of the dimensions of the proof mass 24); for example, it may have an extension elongated along the second horizontal axis y, which may be substantially equal to the corresponding extension of the membrane 23 along the same second horizontal axis y.

[0104] Furthermore, the micromechanical structure described previously may in general be used in any MEMS device for generating an electrical signal starting from detected mechanical vibrations, for example, in a piezoelectric accelerometer or in other devices that envisage the use of a proof mass.