Semiconductor Transistor Device and Method of Manufacturing the Same

Abstract

A method for manufacturing a semiconductor transistor device includes etching a vertical gate trench into a silicon region, depositing a silicon gate material on an interlayer dielectric formed in the vertical gate trench so that an upper side of the interlayer dielectric is covered, etching through the silicon gate material in the vertical gate trench to partly uncover the upper side of the interlayer dielectric and so that a silicon gate region of a gate electrode of the semiconductor transistor device remains in the vertical gate trench, and depositing a metal material into the vertical gate trench so that the partly uncovered upper side of the interlayer dielectric is covered by the metal material.

Claims

1. A method for manufacturing a semiconductor transistor device, the method comprising: etching a vertical gate trench into a silicon region; depositing a silicon gate material on an interlayer dielectric formed in the vertical gate trench so that an upper side of the interlayer dielectric is covered; etching through the silicon gate material in the vertical gate trench to partly uncover the upper side of the interlayer dielectric and so that a silicon gate region of a gate electrode of the semiconductor transistor device remains in the vertical gate trench; and depositing a metal material into the vertical gate trench so that the partly uncovered upper side of the interlayer dielectric is covered by the metal material.

2. The method of claim 1, further comprising: etching a vertical contact trench into a source region of the semiconductor transistor device; and filling the vertical contact trench with a metal material filler, wherein an upper end of the metal material filler lies vertically above an upper end of a metal inlay region of the gate electrode.

3. The method of claim 2, wherein the vertical contact trench is etched simultaneously as the etching through of the silicon gate material, and wherein a thickness which the silicon gate material has prior to the etching through of the silicon gate material is chosen such that the upper side of the interlayer dielectric is uncovered by the etching through of the silicon gate material before the vertical contact trench has been etched to a final depth.

4. The method of claim 1, wherein the silicon gate material has a uniform width in the vertical gate trench.

5. The method of claim 1, further comprising forming a field electrode in the gate trench, and wherein the interlayer dielectric is formed to cover the field electrode.

6. The method of claim 1, wherein the gate electrode is formed to comprise a silicon gate region made of the silicon gate material and a metal inlay region made of the metal material, wherein the silicon gate region forms at least a section of the sidewall of the gate electrode, wherein the metal inlay region extends up from a lower end of the gate electrode, and wherein the silicon gate region forms an upper section of the sidewall of the gate electrode, and wherein the metal inlay region forms a lower section of the sidewall of the gate electrode.

7. The method of claim 1, wherein the gate electrode is formed to comprise a silicon gate region made of the silicon gate material and a metal inlay region made of a metal material, wherein the silicon gate region forms at least a section of the sidewall of the gate electrode, wherein the metal inlay region extends up from a lower end of the gate electrode, and wherein the metal inlay region comprises a silicide layer which is arranged adjacent to the silicon gate region, so that the metal inlay region is electrically connected to the silicon gate region via the silicide layer.

8. A method for manufacturing a semiconductor transistor device, the method comprising: etching a vertical gate trench into a silicon region; depositing a metal material into a bottom of the vertical gate trench to form a metal inlay region in the vertical gate trench; depositing a silicon gate material in the vertical gate trench over the metal material to form a silicon gate region in the vertical gate trench.

9. The method of claim 8, wherein the metal inlay region extends over not more than ⅓ of a sidewall of the vertical gate trench, and wherein the silicon gate material extends over a remainder of the sidewall of the vertical gate trench above the metal inlay region.

10. The method of claim 8, wherein the metal material is initially deposited into the bottom of the vertical gate trench and subsequently etched to lower a height of the metal material along the sidewall of the vertical gate trench.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0048] Below, the invention is explained in further detail by means of exemplary embodiments. Therein, the individual features can also be relevant for the invention in a different combination.

[0049] FIG. 1 shows a transistor device according to the invention in a sectional view;

[0050] FIGS. 2a-2c illustrate different stages of manufacturing the transistor device of FIG. 1;

[0051] FIGS. 3a-3b show alternative transistor devices according to the invention in sectional views;

[0052] FIG. 4 illustrates the manufacturing of a transistor device with a metal inlay region having an increased cross-section, starting from the processing stage shown in FIG. 2c;

[0053] FIG. 5 shows a further transistor device according to the invention in a sectional view;

[0054] FIG. 6 illustrates the manufacturing of a transistor device according to the invention in a block diagram.

DETAILED DESCRIPTION

[0055] FIG. 1 shows a semiconductor transistor device 1 according to the invention, comprising a source region 2 and a drain region 3. By a gate electrode 4 placed in a vertical gate trench 5, the current flow in a channel region 6 can be controlled. The channel region 6 extends vertically between the source region 2 and the drain region 3 (through the body region). It lies laterally aside a gate dielectric 26 (e. g. gate oxide), which is arranged laterally aside the gate electrode 4, namely in between a sidewall 7 of the gate electrode 4 and the channel region 6. The channel region 6 extends vertically along the gate dielectric 26.

[0056] The gate electrode 4 comprises a silicon gate region 8, which is for example made of n-doped polysilicon. Additionally, it comprises a metal inlay region 9. The metal inlay region 9 can for example comprise tungsten as a bulk material 21. The inclusion of the metal reduces the resistance R.sub.G of the gate electrode 4, which can enhance the gate signal propagation across the device 1. As the metal inlay region 9 extends down to a lower end 10 of the gate electrode 4, the cross-section of the metal can be maximized Since the sidewall 7 of the gate electrode 4 is formed by polysilicon, the threshold voltage is kept low (in comparison to a metal gate).

[0057] Below the gate electrode 4, a field electrode 11 is arranged in the gate trench 5. Above the field electrode 11, an interlayer dielectric 12 is formed, on which the gate electrode 4 is fabricated, as explained in further detail by means of FIG. 2.

[0058] The transistor device 1 shown here is a power device with a lightly doped drift region 13 in between the highly doped drain region 3 and the channel region 6. The bottom of the channel region 6 exits into the drift region 13. The drift region 13 is epitaxially grown, the channel region 6 and the source region 2 are formed by ion implantation into this epitaxial layer. In case of the NMOS device shown here, the drain region 3 and the source region 2 are highly n-doped, the channel region 6 is p-doped, and the drift region 13 is lightly n-doped. After the epitaxial growth, the vertical gate trench 5 is etched into the silicon, using a hard mask (TEOS), see in detail U.S. Pat. No. 7,005,351 B2.

[0059] The source region 2 is electrically contacted by a metal material filler 16 arranged in a vertical contact trench 15. Like the metal inlay region 9, it can comprise tungsten as a bulk material 22. Further, it can comprise a silicide layer 14, so that the electrical contact to the source region 2 and the body region with the channel region 6 can be made via this silicide layer 14. Optionally, also in the gate electrode 4, the metal inlay region 9 and the silicon gate region 8 can be electrically connected via a silicide layer 18 of the metal inlay region 9. The numerals 19 reference optional barrier layers of the metal material filler 16 and the metal inlay region 9. They can for instance be made of titanium and/or titanium nitride, which can have been deposited before for the silicide formation (silicide formation layer). Afterwards, the titanium could be removed. When it remains in the gate trench 5, it is considered as a part of the metal inlay region 9,

[0060] FIG. 2a illustrates the gate trench 5 and a sidewall 5a thereof in a detailed view prior to etching through the silicon gate material to form the silicon gate region 8. In the processing stage shown here, the silicon gate material, which is polysilicon 23, covers the interlayer dielectric 12 vertically and the gate dielectric 26 laterally. On top of the polysilicon 23, the gate trench 5 is filled up with an interlayer dielectric 24. Regarding the manufacturing of the structure shown in FIG. 2a, reference is made to the description above and also to U.S. Pat. No. 7,005,351 B2.

[0061] For etching through the interlayer dielectric 24 and the polysilicon 23, a mask 25 is used, for instance a patterned hard mask or photo resist layer, see FIG. 2b. The etch chemistry for the interlayer dielectric 24, typically silicon dioxide, stops automatically on the polysilicon 23. Then, the etch chemistry is changed and a hole is etched through the polysilicon 23 to form the silicon gate region 8, as shown in FIG. 2c. Subsequently, for instance a layer of titanium or titanium and titanium nitride can be deposited for the silicide formation. Then the tungsten is deposited.

[0062] Apart from the manufacturing details, FIGS. 2a-c give a detailed view of the gate dielectric 26 formed laterally in between the sidewall 7 of the gate electrode 4 and the channel region 6.

[0063] To manufacture the device shown in FIG. 1, the metal inlay region 9 and the metal material filler 16 in the contact trench 15 are preferably deposited at the same time. Therein, the metal inlay region trench 27 (see FIG. 2c) is filled up completely by the tungsten material. To obtain the structure of FIG. 1, the tungsten is etched back thereafter. Before, a photoresist can be deposited and structured to protect the metal material filler 16 during etching.

[0064] The metal inlay region 9 can be etched back to a level shown in FIG. 1, so that the inner sidewall 20 of the silicon gate region 8 is covered, but the metal inlay region 9 does not project above. Alternatively, an upper end 30 of the metal inlay region 9 can lie slightly above an upper end 31 of the silicon gate region 8, as shown in FIG. 3a. Likewise, the cross-section of the metal inlay region 9 can be increased, which reduces R.sub.G.

[0065] In this respect, the embodiment shown in FIG. 3b can be advantageous. The metal inlay region 9 is not etched back at all, its upper end 30 lies on the same height as the upper end 17 of the metal material filler 16. For manufacturing this structure, an interlayer dielectric 35 is deposited after forming the metal inlay region 9 and the metal material filler 16, namely a low temperature dielectric to not impair the silicide formed before. Then, a vertical interconnect 36 is etched into the interlayer dielectric 35, and the metallization 37 is deposited for the source contact. The design shown in FIG. 3b lowers R.sub.G but can cause a capacitive coupling between the metal material filler 16 and the metal inlay region 9.

[0066] FIG. 4 illustrates an alternative approach to increase the cross-section of the metal inlay region 9. Following on the process step shown in FIG. 2c, an additional anisotropic dielectric etch is applied to deepen the metal inlay region trench 27 further. After etching through the silicon gate material (e.g. polysilicon), the etch chemistry is changed to etch the interlayer dielectric 12. Then, after for instance a titanium or titanium and titanium nitride deposition for the silicide, the bulk material 21, for instance tungsten, is deposited to complete the metal inlay region 9. In this case, the lower end 45 of the metal inlay region 9 lies below a lower end 46 of the silicon gate region 8, the gate electrode 4 is formed with a step 41.

[0067] FIG. 5 shows a transistor device 1 with an alternative design of the gate electrode 4. Regarding the setup of the source region 2, the channel region 6, the drift region 13 and the drain region 3, the device 1 is comparable to the embodiments discussed above, the same applies for the metal material filler 16 and the metallization 37. However, in contrast to the embodiments above, the silicon gate region 8 forms only an upper section 7.1 of the sidewall 7 of the gate electrode 4. A lower section 7.2 of the sidewall 7 is formed by the metal inlay region 9. In the upper section 7.1, the threshold voltage remains unchanged compared to a conventional polysilicon gate. In the lower section 7.2 however, the threshold voltage is increased due to the metal-silicon work function difference. This design takes advantage of the local increase of the threshold voltage in the lower section 7.2 close to the drain region 3 to counteract drain induced barrier lowering.

[0068] FIG. 6 summarizes some of the manufacturing steps discussed above. After epitaxially growing 60 the layer for the drift region 13, the vertical gate trench 5 is formed by etching 61. Optionally, the field plate region 11 can be formed by depositing 62 field plate material into the vertical gate trench 5 (see in detail U.S. Pat. No. 7,005,351 B2). After forming 63 the interlayer dielectric 12 in the vertical gate trench 5, a preform of the silicon gate region 8 is formed by depositing 64 the silicon gate material into the vertical gate trench 5 (before, the gate dielectric 26 has been grown or deposited). By etching through 65 the silicon gate material, the dielectric 12 is uncovered and the silicon gate region 8 is formed. Optionally, the metal inlay region trench 27 can be deepened by etching 66 into the interlayer dielectric 12 below. Finally, the metal inlay region 9 is formed by depositing 67 the metal material into the vertical gate trench 5.

[0069] Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and/or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that this invention be limited only by the claims and the equivalents thereof.