PRODUCING AN OHMIC CONTACT AND ELECTRONIC COMPONENT WITH OHMIC CONTACT

Abstract

A method for producing an ohmic contact for an electronic part, wherein a layer consisting of a semiconductor is applied to a substrate is disclosed. A surface to be contacted of the applied semiconductor is wet-chemically etched, which is rinsed with radicals. An electrical conductor or a semiconductor is applied to the surface rinsed with radicals. An electronic component having several semiconductor layers on a substrate is also disclosed. A top layer on the one or more semiconductor layers is applied to the substrate. The top layer consists of an electrically non-conductive dielectric having an access through the top layer to a semiconductor layer, wherein adjacent semiconductor layers consist of different II-VI semiconductors. The access is at least partially filled with a II-VI semiconductor. A metallic contact applied to the II-VI semiconductor extends to the outer side of the top layer or projects outwardly relative to the top layer.

Claims

1. A method for producing an ohmic contact for an electronic part, wherein a layer consisting of a semiconductor is applied indirectly or directly to a substrate, wherein a surface to be contacted of the applied semiconductor is wet-chemically etched, the wet-chemically etched surface is rinsed with radicals, and an electrical conductor or a semiconductor is applied to the surface rinsed with radicals.

2. The method of claim 1, wherein rinsing is carried out with hydrogen radicals.

3. The method of claim 1, wherein rinsing is carried out in an ultra-high vacuum.

4. The method of claim 1, wherein rinsing is carried out at a temperature between 100° C. and 200° C.

5. The method of claim 1, wherein wet-chemical etching is carried out with K2Cr2O7+HBr+H2O or with NH3+H2O2+H2O or with K2Cr2O7+H2SO4+H2O.

6. The method of claim 1, wherein wet-chemical etching is carried out for 1 to 20 seconds.

7. The method of claim 1, wherein the semiconductor (3) is a II-VI semiconductor or a III-V semiconductor and consists in particular of (Zn,Mg)Se, Zn(S,Se), ZnSe, CdSe or (Zn,Mg)(S,Se).

8. The method of claim 1, wherein the metal of the semiconductor is selected from zinc (Zn), cadmium (Cd), magnesium (Mg) and/or beryllium (Be).

9. The method of claim 1, wherein the non-metal of the semiconductor is selected from selenium (Se) and/or sulfur (S).

10. The method of claim 1, wherein the semiconductor is doped with chlorine (Cl) or can be doped with chlorine (Cl).

11. An electronic component having one or more semiconductor layers on a substrate, a top layer on the one or more semiconductor layers applied to the substrate, wherein the top layer consists of an electrically non-conductive dielectric, having an access which leads through the top layer to a semiconductor layer, wherein adjacent semiconductor layers consist of different II-VI semiconductors, wherein the access is at least partially filled with a doped II-VI semiconductor and a metallic contact is applied to the doped II-VI semiconductor, which contact extends to the outer side of the top layer or projects outwardly relative to the top layer.

12. The electronic component of claim 11, wherein the first and/or the third semiconductor layer applied consists of (Zn,Mg)Se, (Zn,Mg)(S,Se), (Zn,Be)Se, Zn(S,Se) and/or that the second semiconductor layer consists of ZnSe.

13. The electronic component of claim 11, wherein the top layer consists of aluminum oxide, silicon oxide, hafnium oxide or silicon nitride.

14. The electronic component of claim 11, wherein the substrate consists of GaAs, ZnSe, (In,Ga)As, InAs, (In,Ga)P, (In,Ga,Al)P or InP.

15. The electronic component of claim 11, wherein the electronic component is a unipolar component.

16. The electronic component of claim 12, wherein the top layer consists of aluminum oxide, silicon oxide, hafnium oxide or silicon nitride.

17. The electronic component of claim 12, wherein the substrate consists of GaAs, ZnSe, (In,Ga)As, InAs, (In,Ga)P, (In,Ga,Al)P or InP.

18. The electronic component of claim 13, wherein the substrate consists of GaAs, ZnSe, (In,Ga)As, InAs, (In,Ga)P, (In,Ga,Al)P or InP.

19. The electronic component of claim 12, wherein the electronic component is a unipolar component.

20. The electronic component of claim 13, wherein the electronic component is a unipolar component.

Description

[0061] The figures show:

[0062] FIG. 1: Layer structure with a ZnSe layer;

[0063] FIG. 2: Layer structure with hole;

[0064] FIG. 3: Layer structure with hole partially filled with semiconductor;

[0065] FIG. 4: Layer structure with applied aluminum;

[0066] FIG. 5: Layer structure with finished local ohmic contact;

[0067] FIG. 6: measured current-voltage characteristics;

[0068] FIG. 7: further structure for an electronic component with buried semiconductor layers and local ohmic contact.

[0069] FIG. 1 shows a substrate 1 of gallium arsenide on which a buried first semiconductor layer 2 of (Zn,Mg)Se has been deposited in an ultra-high vacuum. On the first semiconductor layer 2, a buried second semiconductor layer 3 of ZnSe has been deposited in situ in the ultra-high vacuum. On the second semiconductor layer 3, a buried third semiconductor layer 4 of (Zn,Mg)Se has been deposited in situ in the ultra-high vacuum. On the third semiconductor layer 4, a top layer 5 of Al.sub.2O.sub.3 has been deposited in situ in the ultra-high vacuum. The deposition is done for example by atomic layer deposition. The layers can be several 10 nanometers thick, for example 20 nm thick.

[0070] In situ means that the structure produced in FIG. 1 was not removed from the ultra-high vacuum during its producing, so that no detrimental oxidation effects could occur.

[0071] After deposition of the Al.sub.2O.sub.3 layer, the structure is removed from the ultra-high vacuum. By means of conventional optical lithography, a reticular mask with holes is defined in a previously applied photoresist, in which the ohmic contacts will later be created by regrowth. At the positions of the holes, the Al.sub.2O.sub.3 layer 5 is first opened either wet-chemically with HF or by reactive ion etching with CHF.sub.3+O.sub.2. Then the underlying (Zn,Mg)Se and ZnSe layers 4 and 3 are opened by reactive ion etching with Cl.sub.2+Ar. Thus, etching down is performed, as shown in FIG. 2, to create a hole 6. The semiconductor layer 3 can be contacted through this hole 6.

[0072] After reactive ion etching, the resulting radiation damage is removed by wet-chemical re-etching for about 5 seconds with a solution of K.sub.2Cr.sub.2O.sub.7+HBr+H.sub.2O. Then the photoresist is removed and the etched ZnSe semiconductor layer 3 is cleaned with isopropanol and reintroduced into the ultra-high vacuum for the regrowth process. Afterwards, the structure is heated up to 150° C. for 30 minutes in the ultra-high vacuum and then rinsed with hydrogen radicals for 5 minutes. In this way, chemical residues from the etching and cleaning process as well as possible oxide residues on the surface are removed. The etched layer is then slowly heated under zinc flux to the growth temperature suitable for the regrowth process of 300° C. This serves to fill possibly remaining zinc defects near the etched surface. This is followed by the growth of a chlorine-doped ZnSe layer 7 by molecular-beam epitaxy (MBE) under standard growth parameters. This is shown in FIG. 3. The layer 7 should be at least thick enough to fill the hole up to the Al.sub.2O.sub.3 layer 5. Otherwise, the metal 8 on the layer 7 would contact the layer 4 and thus the semiconductor (Zn,Mg)Se laterally. This could be disadvantageous and should therefore be avoided.

[0073] Subsequently, the newly grown doped ZnSe layer 7 is coated in situ with aluminum 8 as an ohmic contact material, which is shown in FIG. 4. The in situ deposited aluminum layer 8 prevents the formation of an oxide between the chlorine-doped ZnSe layer 7 and the aluminum layer 8, so that an unhindered current transport can take place through the aluminum-ZnSe interface.

[0074] In a final step, optical lithography and subsequent wet-chemical etching is used to remove the excess aluminum and ZnSe between the actual local contacts until the structure shown in FIG. 5 is achieved.

[0075] The layer thicknesses in FIG. 5 are only schematic. The two semiconductor layers 2 and 4 may be thicker than the semiconductor layer 3. The top layer 5 may be thinner than the semiconductor layer 3. Advantageously, the semiconductor layer 7 is at least thick enough to extend into the dielectric layer 5.

[0076] In this way, excellent local ohmic contacts with minimum contact resistance and a linear current-voltage characteristic at room temperature and low temperature can be realized. FIG. 6 shows a diagram with correspondingly linear current-voltage characteristics measured at room temperature RT (solid line) and 4 K (dashed line) with the structure shown in FIG. 7. The distance between two ohmic contacts of the part used for the measurement was 30 μm. The measured current in milliamperes is plotted against the applied voltage in volts. In addition to the excellent linearity of the current-voltage characteristics, the contact resistance and sheet resistance of the component shown in FIG. 7 can be determined from the measurement. At room temperature the contact resistance is ρ.sub.K≤3×10.sup.−5 Ωcm.sup.2 and the sheet resistance ρ.sub.S 6×10.sup.−2 Ωcm, at low temperature the contact resistance is ρ.sub.K≤8×10.sup.−3 Ωcm.sup.2 and the sheet resistance ρ.sub.S≤4×10.sup.−2 Ωcm.

[0077] The component shown in FIG. 7 comprises a substrate 1 of gallium arsenide. On the substrate there is a non-doped, approx. 20 nm thick ZnSe semiconductor layer 2. On the ZnSe semiconductor layer 2 there is an approx. 800 nm thick chlorine-doped ZnSe semiconductor layer 3. On the semiconductor layer 3 there is an approx. 20 nm thick dielectric layer 5 of Al.sub.2O.sub.3. An access created to the semiconductor layer 2 by means of a hole has been completely filled with chlorine-doped ZnSe, i.e. with ZnSe:Cl. Aluminum 8 with a thickness of approx. 120 nm is applied on this ZnSe:Cl filling 7.