ON-CHIP INTEGRATION OF INDIUM TIN OXIDE (ITO) LAYERS FOR OHMIC CONTACT TO BOND PADS

Abstract

An apparatus includes an optical device (22) and an electrically conductive bond pad (32). A multi-layer stack (42,44,46) of electrically conductive materials is disposed on the bond pad (32). An ITO layer (48) is disposed at least partially on the optical device (22) and makes ohmic contact with the multi-layer stack (42,44,46).

Claims

1. An apparatus comprising: an optical device; an electrically conductive bond pad; a multi-layer stack of electrically conductive materials on the bond pad, the stack including a first ITO layer as a top layer; and a second ITO layer disposed at least partially on the optical device and on the first ITO layer.

2. The apparatus of claim 1 wherein the first ITO layer has a composition that differs from that of the second ITO layer.

3. The apparatus of claim 1 wherein the second ITO layer covers the optical device.

4. The apparatus of claim 1 wherein the multi-layer stack of electrically conductive materials forms an ohmic contact to the bond pad.

5. The apparatus of claim 1 wherein the multi-layer stack of electrically conductive materials includes a conductive layer in direct contact with the bond pad, and a sub-stack of at least one diffusion barrier layer or adhesion layer is in direct contact with the conductive layer, wherein the first ITO layer is in direct contact with the sub-stack of at least one diffusion barrier layer or adhesion layer.

6. The apparatus of claim 1 wherein the multi-layer stack comprises a titanium layer on an aluminum layer that is in direct contact with the bond pad, wherein the first ITO layer is on the titanium layer.

7. The apparatus of claim 1 wherein the optical device is an optical interference filter; optionally wherein the optical interference filter is disposed over a light detecting element in an integrated semiconductor circuit.

8. (canceled)

9. The apparatus of claim 1 wherein the optical device is a photodetector and wherein the second ITO layer covers the photodetector, the apparatus further including: a second electrically conductive bond pad; a second multi-layer stack of different electrically conductive materials on the second electrically conductive bond pad, the second stack including a top layer comprising a first ITO layer; an electrode layer disposed on a side of the optical device opposite that of the second ITO layer and connected to the first ITO layer of the second stack; optionally wherein the photodetector is an organic photodetector.

10. (canceled)

11. The apparatus of claim 9 wherein the electrode layer disposed on a side of the optical device opposite that of the second ITO layer is composed of a third ITO layer.

12. The apparatus of claim 1 wherein the first and second ITO layers are integrated as part of a CMOS integrated circuit.

13. A method comprising: providing a substrate that includes an electrically conductive bond pad, an optical device being disposed on the substrate; providing a multi-level stack of electrically conductive materials on the bond pad, the stack including a first ITO layer as a top layer; and providing a second ITO layer at least partially on the optical device and the first ITO layer.

14. The method of claim 13 wherein the first ITO layer has a composition that differs from that of the second ITO layer.

15. The method of claim 13 including providing the second ITO layer so that it covers the optical device.

16. The method of claim 13 wherein the multi-layer stack of electrically conductive materials forms an ohmic contact to the bond pad.

17. The method of claim 13 wherein providing a multi-layer stack includes: depositing a conductive layer in direct contact with the bond pad; depositing a sub-stack of at least one diffusion barrier layer or adhesion layer in direct contact with the conductive layer; and depositing the first ITO layer in direct contact with the sub-stack of at least one diffusion barrier layer or adhesion layer.

18. The method of claim 13 wherein providing a multi-level stack includes: depositing an aluminum layer on the bond pad; depositing a titanium layer on the aluminum layer; and depositing the first ITO layer on the titanium layer.

19. The method of claim 13 wherein the optical device is an optical interference filter; optionally wherein the optical interference filter is disposed over a light detecting element in an integrated semiconductor circuit in the substrate.

20. (canceled)

21. The method of claim 13 wherein the substrate is processed in accordance with CMOS fabrication techniques.

22. A method comprising: providing a substrate that includes first and second electrically conductive bond pads; providing a first multi-level stack of electrically conductive materials on the first bond pad and providing a second multi-level stack of electrically conductive materials on the second bond pad, each of the stacks including a respective first ITO layer as a top layer; providing a second ITO layer on the substrate and connected to the first ITO layer of the first multi-level stack; providing an optical device on the second ITO layer; and providing a third ITO layer at least partially on the optical device and connected to the first ITO layer of the second multi-level stack.

23. The method of claim 22 wherein providing the first multi-level stack of electrically conductive materials includes: depositing a first conductive layer on the first bond pad; depositing a first sub-stack of at least one diffusion layer or barrier layer on the first conductive layer; and depositing the first ITO layer for the first stack on the first sub-stack of at least one diffusion layer or barrier layer, and wherein providing the second multi-level stack of electrically conductive materials includes: depositing a second conductive layer on the second bond pad; depositing a second sub-stack of at least one diffusion layer or barrier layer on the second conductive layer; and depositing the first ITO layer for the second stack on the second sub-stack of at least one diffusion layer or barrier layer.

24-31. (canceled)

32. A method comprising: providing a substrate that includes an electrically conductive bond pad, an optical device being disposed on the substrate; providing an ITO layer at least partially on the optical device, the ITO layer extending along a surface of the substrate; and subsequently providing a multi-level stack of electrically conductive materials on the bond pad, the multi-layer stack including a sub-stack of at least one diffusion barrier layer or adhesion layer in direct contact with the bond pad, and a conductive layer in direct contact with the sub-stack, and wherein the layers of the multi-layer stack extend along a surface of the substrate and overlie a portion of the ITO layer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0015] FIGS. 1-3 illustrate various steps in a first example process of on-chip integration of ITO thin films for an ohmic contact to a bond pad.

[0016] FIG. 4 illustrates another example of on-chip integration of ITO thin films for ohmic contacts to bond pads.

[0017] FIG. 5 illustrates a further example of on-chip integration of an ITO thin film having an ohmic contact to a bond pad.

DETAILED DESCRIPTION

[0018] The present disclosure describes the on-chip integration of ITO thin films for ohmic contacts to CMOS or other electrically conductive bond pads. As described in greater detail below, the present techniques use an ITO-to-ITO contact to avoid problems that otherwise can occur as a result of the formation of an oxide interlayer.

[0019] An example is described in connection with FIGS. 1-3, which illustrate a substrate 20, such as a CMOS semiconductor wafer, having an interference filter 22 on top of an n-well photodiode 24. The interference filter is an optical filter that reflects one or more spectral bands or lines and transmits others so that they pass to the photodiode 24 where they can be detected. FIGS. 1-3 also show a backend stack that includes a multi-level metal structure 26 and corresponding conductive via levels. The multi-level metal structure can be composed, for example, of aluminum (Al) or some other conductive metal. In the illustrated example, the wafer 20 includes a p-type substrate 28 in which the n-well photodiode 24 is disposed. A dielectric layer (e.g., oxide) 30 is disposed on the substrate 28 and surrounds the multi-level metal stack 26. A portion of the backend stack forms a bond pad 32. In some instances, other types of substrates (e.g., glass) can be used instead of a semiconductor wafer.

[0020] Depending on the spectral characteristic of the filter 22, the arrangement can be used for various kinds of optical sensing purposes. For some applications, it is beneficial to provide a conductive shielding layer over the interference filter 22. A conductive shielding layer over the interference filter 22 may be formed, for example, by providing a transparent conductive material that is electrically coupled to the bond pad 32. ITO can provide a suitable material for this purpose because it can be both transparent in the visible spectrum and electrically conductive. In some applications, the thickness of the ITO layer preferably is in the range of 30 nm to 300 nm to achieve to achieve desirable optical and electrical characteristics. The bond pad 32 can be used to apply a well-defined voltage to the ITO layer. However, depositing the ITO layer directly on to the bond pad 32 and performing a subsequent lift-off process for patterning the ITO can be difficult for at least two reasons. First, as mentioned above, a reliable low-ohmic contact cannot be achieved simply by depositing ITO onto aluminum because of the chemical properties of these materials, resulting in formation of a thin oxide layer. Second, as shown in FIG. 1, for a typical CMOS manufacturing process, there will be a step “h” of about 2 μm from the passivation surface 34 down to the bond pad 32. Accordingly, the step height “h” exceeds the ITO layer thickness by about one or two orders of magnitude. Thus, the formation of a reliable ITO contact directly to the bond pad 32 is very challenging, if not virtually impossible, in view of the step coverage issues.

[0021] To address the foregoing issues, the present disclosure describes a method including the formation of two different ITO layers that electrically couple the bond pad to the interference filter, so as to form at least part of an electrode for the filter. A first one of the ITO layers forms a top layer of a layered stack on the bond pad. The second ITO layer electrically extends over the interference filter and contacts the first ITO layer. Details of the method according to some implementations are described in connection with FIGS. 2 and 3.

[0022] As shown in the example of FIG. 2, a layered stack 40 of electrically conductive materials is deposited in a sequential manner on the bond pad 32 such that the materials are not exposed to air. Each of the layers in the stack 40 should form a good ohmic contact to the underlying layer on which it is deposited. In the illustrated example, the first layer 42 is composed of aluminum and has a thickness in a range of 0.5 μm-3 μm. This layer thickness helps ensure that the step coverage down to the bond pad 32 is sufficient to provide a good ohmic contact. Although aluminum is a preferred material because it is compatible with existing CMOS technology, other conductive materials (e.g., gold, silver, chromium and/or copper) can be used for the first layer 42 in some implementations.

[0023] Subsequently, without exposing the first layer 42 to air, a sub-stack of at least one diffusion barrier layer or adhesion layer 44 is deposited on the first layer 42. The at least one diffusion barrier layer or adhesion layer 44 can be composed, for example, of titanium (Ti). In some implementations, the at least one diffusion barrier layer or adhesion layer 44 includes cobalt, chromium, nickel-chromium, a nickel chromium alloy, molybdenum, and/or titanium sub-oxide. The thickness of this second layer 44 can be adjusted so as to maintain a good diffusion barrier to the subsequently deposited third layer material 46.

[0024] The third layer 46 is an ITO layer that provides electrical functionality, but need not provide any particular optical functionality. Therefore, the process parameters can be set such that the properties of the ITO layer 46 are optimized for low contact resistance to the underlying diffusion barrier layer 44. Preferably, the deposition technique (e.g., sputtering) should ensure that there is no significant oxidation of the sub-stack of at least one barrier layer or adhesion layer (e.g., the Ti layer 44) prior to the ITO deposition.

[0025] The three layers 42, 44, 46 in the stack 40 can exhibit and provide different electrical functionalities. Thus, for example, in some implementations, the relatively thick aluminum layer 42 ensures there is sufficient step coverage and low resistance. The Ti layer 44 can act as a diffusion barrier between the aluminum layer 42 and the ITO layer 46 to ensure reliable and low contact resistivity. The ITO layer 46 can exhibit low resistivity and also can act as a cap layer. As the ITO material for the layer 46 already is in an oxidized state, it is not prone to further oxidation. By providing the ITO layer 46 as an oxidized, but conductive, cap layer, subsequent process steps will not harm the surface of the ITO layer 46 by further oxidation.

[0026] After depositing the layers 42, 44, 46 for the stack 40, the stack is patterned (e.g., structured), for example, by a lift-off or other technique to ensure that the perimeter is free of fences or other lift-off artefacts that adversely may affect reliability.

[0027] Next, a second ITO layer 48 is deposited and patterned (e.g., structured), for example, by a lift-off technique. The second ITO layer 48 covers the interference filter 32 that is over the photodiode 24, as well as part of the three-layer-stack 40. Formation of a non-conductive oxide layer does not present a problem because the contact formation takes place between the first ITO layer 46 (which already is oxidized) and the second ITO layer 48. The second ITO layer 48 can provide both optical and electrical functionality and, therefore, may have a composition different from that of the first ITO layer 46. Thus, in addition to providing an electrical connection to the bond pad 32 via the stack 40 so as to provide electrostatic or RF shielding for the optical filter 22, the ITO layer 48 also can have specified optical properties (e.g., transparency in a particular part of the visible spectrum) to allow electromagnetic radiation in the visible range to pass to the filter 32 for detection by the photodiode 24.

[0028] In some instances, the ITO layer 48 is covered with a single- or multilayer anti-reflection coating (ARC) 50 to reduce reflection losses. The ARC 50 also can act as a protective layer for the underlying ITO layer 48 against humidity and oxidation.

[0029] Similar techniques can be used for other types of optoelectronic devices as well. For example, thin ITO layers can be integrated on a CMOS wafer to provide top and bottom electrodes for an infra-red (IR) sensor. FIG. 4 illustrates an example that includes an IR sensitive organic layer 60 that serves as an organic photodetector for sensing light in the IR range. The device also includes top and bottom electrodes each of which is coupled electrically to a respective CMOS bond pad 32A, 32B by a respective stack 40A, 40B on the bond pads. The electrodes allow the optoelectronic properties of the sensor to be modified by adjusting the applied voltage.

[0030] Respective stacks 40A, 40B can deposited, in the manner described above, on each of the bond pads 32A, 32B. Each stack 40A, 40B includes a respective first ITO layer 46A, 46B on at least one diffusion barrier layer or adhesion layer 44 that is on a conductive layer 42. As noted above, the conductive layers 42 can be composed, e.g., of aluminum, gold, silver, chromium and/or copper. The at least one diffusion barrier layer or adhesion layer 44 in each stack 40A, 40B can include, e.g., of titanium, cobalt, chromium, nickel-chromium, a nickel chromium alloy, molybdenum, and/or titanium sub-oxide.

[0031] Next, a second ITO layer 48B, which serves as the bottom electrode, is deposited. Then, the IR sensitive organic layer 60 that serves as the organic photodetector is deposited, followed by deposition of a third ITO layer 48A that serves as the top electrode. Both ITO layers 48A, 48B that serve, respectively, as the top and bottom electrodes are connected to the respective bond pads 40A, 40B by the previously deposited multi-layer stack 40A, 40B. In some instances, an ARC layer 50 is deposited to encapsulate the ITO layers 48A, 48B and improve optical performance.

[0032] As explained in connection with the example of FIGS. 2 and 3, the ITO layers 46A, 46B that form part of the multi-layer stacks 40A, 40B on the bond pads 32A, 32B do not need to have any particular optical characteristics. Instead, they can be tailored to optimize their electrical characteristics. On the other hand, the ITO layers 48A, 48B that serve as the top and bottom electrodes, can be optimized for the desired optical characteristics as well. Thus, the ITO layers 48A, 48B may have a composition that differs from that of the ITO layers 46A, 46B. Further, the compositions of the ITO layers 48A, 48B may differ from one another.

[0033] The top electrode 48A should have a relatively low absorption for infrared light and a relatively low contact resistance to the detector material 60. The bottom electrode 48B should not be transparent for IR light, but should have a relatively low contact resistance to the detector material 60. Although an ITO layer is thus suitable for the bottom electrode 48B, in some cases, a noble metal that does not form a native oxide at the interface with the detector material 60 can be used instead.

[0034] By varying the voltage signal applied to the bond pads 32A, 32B the voltage applied to the interference filter 32 can be varied so as to so to achieve particular optical filtering characteristics and, thereby, impact the wavelength(s) of light sensed by the photodiode 24.

[0035] FIG. 5 illustrates an alternative implementation in which the layered stack of electrically conductive materials on the bond pad 32 does not include the ITO layer 46. Instead, a layered stack 140 includes a conductive layer 142 disposed on a sub-stack of at least one diffusion barrier layer or adhesion layer 144 that is disposed on the bond pad 32. The at least one diffusion barrier layer or adhesion layer 144 can be composed, for example, of titanium (Ti). In some implementations, the at least one diffusion barrier layer or adhesion layer 144 includes cobalt, chromium, nickel-chromium, a nickel chromium alloy, molybdenum, and/or titanium sub-oxide. The conductive layer 142 can be composed, for example of aluminum, gold, silver, chromium and/or copper.

[0036] In the implementation of FIG. 5, the ITO layer 148 that covers the interference filter 32 is deposited and patterned prior to depositing the layers 144, 142 of the stack 140. The layers 144, 142 of the stack are disposed over the bond pad 32 and extend over the surface of the wafer 20 so that they make electrical contact with the ITO layer 148.

[0037] As in the implementation of FIG. 3, the ITO layer 148 can provide both optical and electrical functionality. Thus, in addition to providing an electrical connection to the bond pad 32 via the stack 140 so as to provide electrostatic or RF shielding for the optical filter 22, the ITO layer 148 also can have specified optical properties (e.g., transparency in a particular part of the visible spectrum) to allow electromagnetic radiation in the visible range to pass to the filter 32 for detection by the photodiode 24.

[0038] In some instances, the ITO layer 148 is covered with a single- or multilayer anti-reflection coating (ARC) 150 to reduce reflection losses. The ARC 150 also can act as a protective layer for the underlying ITO layer 148.

[0039] The foregoing techniques enable the fabrication of ITO layers connected to an electric circuit directly on top of a CMOS device and can enable the on-chip integration of ITO into CMOS processes. The techniques described here can be used, more generally, in connection with any ITO electrode that is formed at least partially on an optical device, and in particular, where the ITO electrode needs to be transparent to wavelength(s) of light that are to be sensed by, or transmitted through, the optical device. Thus, in addition to the examples of an interference filter and an organic IR photodiode discussed above, the techniques can be used in conjunction with optical other devices, such as spectrometers in which a Fraby-Perot interferometer in the form of a piezoelectric element is provided to tune the spectrometer's cavity thickness. Likewise, the techniques can be used on conjunction with electro-optic devices in which a voltage is applied so as to adjust the transparency or opaqueness of device. Further, the foregoing techniques can be used to adjust the polarization state, for example, of liquid crystals.

[0040] Various modifications can be made within the spirit of the disclosure. Features described in connection with different embodiments can, in some cases, be combined in the same implementation. Accordingly, other implementations are within the scope of the claims.