Data processing apparatus having multiple processors and multiple interfaces

Abstract

A data processing apparatus is specified, having multiple processor devices (4), multiple interface devices (5), to which external devices (E) are respectively connectable, and having connections (8, 10) between the interface devices (5) and the processor devices (4), via which data are transportable between the interface devices (5) and the processor devices (4). In the connections (8, 10), there is provision for at least one data management device (20) for handling data flows between the interface devices (5) and the processor devices (4). The data management device (20) is in the form of a hardware component.

Claims

1. An avionics computer system comprising a data processing apparatus, comprising: a plurality of processor devices, wherein at least one of the processor devices has one or more processor cores on which multiple software applications can be executed in parallel; a plurality of interface devices configured for connection to external devices; and connections between the interface devices and the processor devices, via which data can be transported between the interface devices and the processor devices, wherein at least one data management device configured to handle data flows between the interface devices and the processor devices is provided in the connections, wherein the processor devices have memory areas configured to store data, wherein the memory areas are each coupled to the processor cores, wherein the at least one data management device is configured to handle data flows to the memory areas of the processor devices, wherein the memory areas are directly controllable by the at least one data management device, such that the at least one data management device can write data into or read data from physical memory areas that are firmly defined for relevant applications, wherein the at least one data management device is configured as a hardware component, wherein the hardware component is configured modularly and/or logically distinct from the processor devices and the interface devices, wherein the hardware component is directly connected to at least one part of the interface devices, wherein data can flow between the data management device and the interface devices and between the at least one data management device and the processor devices using separated connections.

2. The avionics computer system of claim 1, wherein the interface devices are configured to receive data from external devices that can be connected to the interface devices, and/or transmit data to external devices that can be connected to the interface devices.

3. The avionics computer system of claim 1, wherein at least one of the interface devices is configured to receive data from an external device that can be connected to the interface device, and wherein at least one of the interface devices is configured to transmit data to an external device that can be connected to the interface device.

Description

(1) These and additional advantages and features are explained in the following text, based on an example with the aid of the accompanying figures, in which:

(2) FIG. 1 shows a schematic example of the consolidation of older computer systems to new computer architectures;

(3) FIG. 2 shows the principal structure of a data processing apparatus according to the prior art;

(4) FIG. 3 shows a schematic representation of a data processing apparatus according to the invention; and

(5) FIG. 4 shows a detailed representation of the memory management.

(6) FIG. 3 shows the schematic structure of a data processing apparatus according to the invention, which can, for example, be part of a computer system. Components which are similar to the components described above in connection with FIG. 2 regarding the prior art or can be identical to them are marked with the same reference numerals.

(7) It thus emerges that, in contrast to the data processing apparatus of FIG. 2, at least one additional data management device 20 is provided in the connection 8 between the interfaces 5 and the processors 4 in the data processing apparatus according to the invention of FIG. 3. In the example shown in FIG. 3, two data management devices 20 (HW I/O manager-hardware) are used. Other variants can also be equipped with only one data management device 20 or with multiple data management devices.

(8) The data management device 20 handles the data flow between the different interface devices 5 and the applications running on the processors 4. In particular, the data management device 20 is implemented as hardware, e.g. in the form of an integrated circuit (HW I/O manager).

(9) The data management device 20 takes over the interface management and the data transport, whereby significantly lower latency times are possible, as explained later. The significantly lower latency times are mainly based on the virtualization of the interfaces through the data management device, the direct common usage of a processor main memory to be explained later, and the autonomous sorting and transferring of incoming and outgoing data through the data management device 20.

(10) In the concrete example shown in FIG. 3, the data management device 20 receives data from the interface 5a which, in turn, is connected to an external device E, and writes them directly into the main memory areas which are used in the processor 4a by the applications 1 and 2. In contrast to the example of FIG. 2 known from the prior art, it is therefore not required that—unlike in FIG. 2—an application (in FIG. 2: application 2) receives data and must copy such data for the use by another application (in FIG. 2: application 1). Rather, the data management device 20 makes the data available to both applications 1 and 2 at the same time.

(11) In addition, the data received via the interface 5a are also written directly into the main memory area of the application 3, so that also therein elaborate copying processes (copying data from application 2 to application 3 in FIG. 2) are omitted.

(12) For this purpose, fixed physical connections, in particular, for the data management device 20, to the relevant memory areas are defined which ideally also remain unaltered in operation. The data management device 20 therefore “knows” exactly which data must be written into which memory areas of the processors 4.

(13) The data flows therefore occur via the connection 8 between the (receiving) interface 5a and the memory areas of the applications 1 and 2 for the processor 4a and the memory area of the application 3 on the processor 4b.

(14) For the writing processes by the data management device 20 extremely short latency times result. These are typically less than 5 μs. For comparison: for the reading and copying processes of the apparatus of FIG. 2, significantly longer latency times in the range of milliseconds were required. The latency times or their underlying processes are marked by dashed arrows in FIG. 3.

(15) An example of transmitting data from the applications 3 and 4 is explained in the right part of the image of FIG. 3. Here the data management device 20 (shown in FIG. 3 in the right part of the image) directly accesses the memory areas of the applications 3 and 4 and transfers the data read therein directly to the interface 5b.

(16) The data flow therefore occurs from the application 3 in the processor 4b via the connection 10 and the application 4 in the processor 4c to the (transmitting) interface 5b via the data management device 20.

(17) Here, too, the occurring latency times are very short and are typically less than 10 μs.

(18) In addition, the processors 4 can be connected among one another via connections 11 in the usual manner.

(19) The processors 4 shown in FIG. 3 can, in each case, have a processor core (“CPU”) as well as the associated memory hierarchy and memory management. If the processors 4 are part of multi-core processors (cf., e.g., the multi-core processors 7 in FIG. 1), it is also possible that the processor cores (CPU) share the memory management with other processor cores (CPU) which are part of the multi-core processor in question. In this connection, it is added, with reference to FIG. 1, that in each case four processor cores (correspondingly, “CPU” in FIG. 3) are shown for the multi-core processors 7 shown therein by way of example. Of course, the multi-core processors 7 can be structured differently.

(20) Accordingly, the processors 4a and 4b can, e.g., be part of a first multi-core processor and the processor 4c can be part of another multi-core processor in the example of FIG. 3.

(21) FIG. 4 shows, in more detail, an example of another application in order to be able to better explain the data flows and memory access.

(22) In this figure, the representation of the actual main processor 4 is separate from a main memory 21 allocated to the processor 4. In the representations in FIGS. 2 and 3, the relevant main memory has not been shown separately, but shown as part of the processor 4 (more correctly: processor device consisting of the actual processors and required further components such as memory areas, etc.).

(23) The applications 1 and 2, to which memory areas 22 (for application 1) and 23 (for application 2) are respectively allocated, run in the processor 4. The memory areas 22, 23 are managed by a memory management 24 in a known manner.

(24) The data management device 20 (HW I/O manager) has an appropriate configuration 25 which enables it to handle the interfaces 5 or 5a, 5b allocated to it in a defined manner in each case and the data flows associated therewith. In particular, the data management device 20 “knows” which data from which interface 5 must be written into which memory areas 22, 23 in the main memory 21 or must be read from there and transmitted.

(25) In the example shown in FIG. 4, the received data are written into the memory areas 22 (for application 1) and 23 (for application 2) by the data management device 20 via the (receiving) interface 5a, as has already been explained based on FIG. 3. The applications 1 and 2, in turn, have direct access to the memory areas 22 and 23.

(26) Data to be outputted are, in the example shown, written into the memory area 23 by the application 2 and from there read by the data management device 20 and routed to the interface 5b.

(27) FIG. 4 only shows the structure of a highly simplified system. In more complex systems, it is, for example, possible that multiple processor cores (“CPU”) share a common memory management and a common main memory (e.g. in multi-core processors). The data management device 20 can, in turn, be coupled to multiple multi-core processors.