Method for detecting an attempt to breach the integrity of a semiconductor substrate of an integrated circuit from its back face, and corresponding integrated circuit

Abstract

A semiconductor substrate has a front face and a back face. A first contact and a second contact, spaced apart from each other, are located on the front face. An electrically conductive wafer is located on the back face. A detection circuit is configured to detect a thinning of the substrate from the back face. The detection circuit including a measurement circuit that takes a measurement of a resistive value of the substrate between said at least one first contact, said at least one second contact and said electrically conductive wafer. Thinning is detected in response to the measured resistive value.

Claims

1. A method for detecting an attempt to breach the integrity of an integrated circuit which includes a semiconductor substrate doped solely with a first conductivity type and having a front face and a back face, the method comprising: detecting a thinning of the semiconductor substrate from the back face, wherein detecting the thinning comprises: first measuring a resistive value of the semiconductor substrate between a first contact located on the front face, a second contact located on the front face and an electrically conductive wafer located on the back face, wherein the first and second contacts are spaced apart from each other, and wherein the electrically conductive wafer is in direct electrical connection with the back face of the semiconductor substrate.

2. The method according to claim 1, wherein first measuring the resistive value of the substrate comprises: applying a voltage difference between said first contact and said electrically conductive wafer; and measuring, at said second contact, a current resulting from said voltage difference.

3. The method according to claim 1, wherein a space between said first contact and said second contact is greater than or equal to half a thickness of the semiconductor substrate before thinning.

4. The method according to claim 1, wherein first measuring is performed between a first contact group formed by a plurality of first contacts that are distributed over said front face, a second contact group formed by a plurality of second contacts that are distributed over said front face and said electrically conductive wafer.

5. The method according to claim 1, wherein detecting the attempt further comprises, prior to detecting the thinning of the semiconductor substrate, detecting a removal of at least a portion of the electrically conductive wafer.

6. The method according to claim 5, wherein detecting the removal of at least a portion of the electrically conductive wafer comprises: second measuring a resistive value of the semiconductor substrate between said first contact and said electrically conductive wafer.

7. The method according to claim 6, wherein second measuring the resistive value of the semiconductor substrate comprises: applying a voltage difference between said first contact and said electrically conductive wafer; and measuring, at said first contact, a current resulting from said voltage difference.

8. The method according to claim 6: wherein said first contact comprises a first contact group formed by a plurality of first contacts that are distributed over said front face; and wherein second measuring is performed between said first contact group and said electrically conductive wafer.

9. The method according to claim 1, wherein the resistive value of the semiconductor substrate consists essentially of an access resistance for at least one of the first and second contacts, a lateral resistance between the first contact and the second contact, and a vertical resistance between the access resistance and the electrically conductive wafer.

10. An integrated circuit, comprising: a semiconductor substrate doped solely with a first conductivity type and having a front face and a back face; a first contact and a second contact, wherein the first and second contacts are spaced apart from each other and located on the front face; an electrically conductive wafer located on the back face, wherein the electrically conductive wafer is in direct electrical connection with the back face of the semiconductor substrate; and a first detection circuit that is configured to detect a thinning of the semiconductor substrate from the back face, said first detection circuit including: a first measurement circuit that is configured to take a first measurement of a resistive value of the semiconductor substrate between said first contact, said second contact and said electrically conductive wafer.

11. The integrated circuit according to claim 10, wherein the first measurement circuit is configured to apply a voltage difference between said first contact and said electrically conductive wafer and to measure, at said second contact, a current resulting from said voltage difference.

12. The integrated circuit according to claim 10, wherein a space between said first contact and said second contact is greater than or equal to half a thickness of the semiconductor substrate before thinning.

13. The integrated circuit according to claim 10, wherein said first contact comprises a first contact group formed by a plurality of first contacts that are distributed over said front face, wherein said second contact comprises a second contact group formed by a plurality of second contacts that are distributed over said front face, and wherein the first measurement circuit is configured to take the first measurement between the first contact group, the second contact group and said electrically conductive wafer.

14. The integrated circuit according to claim 10, further comprising a second detection circuit that is configured to detect, prior to the operation of detecting the thinning of the semiconductor substrate, a removal of at least a portion of the electrically conductive wafer.

15. The integrated circuit according to claim 14, wherein the second detection circuit comprises a second measurement circuit configured to take a second measurement of a resistive value of the semiconductor substrate between said first contact and said electrically conductive wafer.

16. The integrated circuit according to claim 15, wherein said second measurement circuit is configured to apply a voltage difference between said first contact and said electrically conductive wafer and to measure, at said first contact, a current resulting from this voltage difference.

17. The integrated circuit according to claim 15, wherein said first contact comprises a first contact group formed by a plurality of first contacts that are distributed over said front face, and wherein the second measurement circuit is configured to take said prior measurement between said first contact group and said electrically conductive wafer.

18. The integrated circuit according to claim 10, wherein the integrated circuit is a component of an electronic device.

19. The integrated circuit according to claim 18, wherein the electronic device is a chip card.

20. The integrated circuit according to claim 10, wherein the resistive value of the semiconductor substrate consists essentially of an access resistance for at least one of the first and second contacts, a lateral resistance between the first contact and the second contact, and a vertical resistance between the access resistance and the electrically conductive wafer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Other advantages and features of the invention will become apparent upon examining the detailed description of completely non-limiting embodiments and modes of implementation of the invention and the appended drawings, in which:

(2) FIG. 1 shows a sectional view of an integrated circuit fitted to a chip card;

(3) FIG. 2 shows an exemplary embodiment of the integrated circuit;

(4) FIG. 3 shows an exemplary embodiment of the integrated circuit;

(5) FIG. 4 schematically illustrates the provision of groups of contacts distributed over the front face;

(6) FIG. 5 illustrates steps of a method;

(7) FIG. 6 illustrates steps of a method, and

(8) FIG. 7 illustrates steps of a method.

DETAILED DESCRIPTION

(9) FIG. 1 shows an example of an integrated circuit IC fitted to a chip card CP.

(10) A typical chip card CP is illustrated schematically at the top of FIG. 1. The integrated circuit IC is fitted into the card body CB of the chip card CP, under contacts MC. A section through this assembly is shown at the bottom of FIG. 1.

(11) The integrated circuit IC conventionally comprises a semiconductor substrate surmounted by an interconnect portion (BEOL: back end of line).

(12) The integrated circuit IC is covered with an electrically conductive wafer PL. This wafer is bonded to the back face FR of said substrate by a conductive adhesive layer CA and attaches the substrate to a face of a resin base RES.

(13) The resin base RES bears, on its opposite face, contacts MC configured to make the connections from the integrated circuit IC to a terminal such as a card reader.

(14) The integrated circuit IC is encapsulated in an insulating encapsulation layer Encap.

(15) The insulating encapsulation layer Encap is itself encapsulated in a card body CB.

(16) The connections between the contacts MC and the integrated circuit IC are made by means of wires BW, in a typical flip-chip configuration, with the wires BW being soldered to said contacts MC and to contact pads formed on the final metallization level of the interconnect portion.

(17) The assembly formed by the electrically conductive wafer PL, the adhesive conductive layer CA and the resin RES forms a coating for the integrated circuit IC.

(18) This does not rule out the possibility of using other coatings that are known in the field of integrated circuits, for example, for an application other than a chip card.

(19) FIG. 2 shows an exemplary embodiment of the integrated circuit IC.

(20) The integrated circuit IC includes a semiconductor substrate having a front face FV, a back face FR and contacts PCi which are distributed over the front face FV; only one first contact PC1 and one second contact PC2 are shown here.

(21) Typically, the semiconductor substrate includes n-type semiconductor wells CS that are electrically isolated from the rest of the substrate, which here exhibits p-type conductivity.

(22) The contacts PC1 and PC2 include p.sup.+-type overdoped regions.

(23) For example, to extract confidential data from a memory of the integrated circuit, an attacker needs to thin the substrate in order to get as close as possible to the components of the integrated circuit, which are formed on its front face.

(24) Such thinning may comprise, for example, chemical-mechanical polishing from the rear face and/or machining, for example using a focused ion beam FIB.

(25) To carry out the thinning, the attacker may locally remove a portion of the initial wafer or even the entire initial wafer.

(26) After thinning, the attacker may leave the initial wafer partially removed, redeposit the initial electrically conductive wafer PL or deposit another wafer PL on the back face FR.

(27) The integrated circuit then advantageously also includes first detection circuit that is configured to detect a thinning of the substrate from the back face FR.

(28) The first detection circuit includes here a first measurement circuit MS1 that is configured to take a first measurement of a resistive value of the substrate between the first contact PC1, the second contact PC2 and said electrically conductive wafer PL.

(29) The resistance that will be measured therefore includes an access resistance RAC, a vertical resistance RVT between the access resistance and the electrically conductive wafer PL and a lateral resistance RLT between the two contacts PC1 and PC2.

(30) Although the depiction of the access resistance in FIG. 2 has been intentionally exaggerated for the sake of clarity, this access resistance represents the resistance of the substrate bulk between the front face FV and the adjacent well edges CS.

(31) The first measurement circuit MS1 includes a circuit GT1 that is configured to apply a first voltage V1 to the contact PC1 while the wafer PL is configured to be grounded GND.

(32) The measurement of the resistive value of the substrate will be obtained here by measuring the current I1 at the second contact PC2, this first current I1 resulting from the difference in voltage V1-0.

(33) For this, the first measurement circuit MS1 includes a first current measurement circuit MES1, which is conventional in structure and known per se, that is intended to measure the current I1 and to compare it with at least one threshold.

(34) This threshold corresponds, for example, to a nominal current value obtained for a non-thinned substrate.

(35) Measuring the current is a simple way of measuring the resistive value of the substrate, and because the vertical resistance and the lateral resistance are simultaneously taken into account, the variation in current between a non-thinned substrate and a substrate that has been thinned, even slightly, is substantial.

(36) The two contacts PC1 and PC2 are spaced apart by a distance D.

(37) Although not essential, it is preferable for this distance D to be about the same as the thickness EP of the substrate before thinning. This makes it possible to increase the sensitivity of the measurement between a non-thinned substrate and a thinned substrate.

(38) By way of indication, for a substrate that is 150 micrometers thick, this distance D will advantageously be at least equal to 75 micrometers, for example about 150 micrometers.

(39) By way of example, for a substrate with a nominal thickness EP that is equal to 150 micrometers and a spacing D of 150 micrometers between the contacts PC1 and PC2, what is obtained is a nominal current I1 corresponding to a non-thinned substrate of about 10 microamperes.

(40) Also by way of example, for a thinning by about 40 micrometers, what is obtained is a current I1 that is higher than 100 microamperes.

(41) It is also advantageous for the operation of detecting the attempt to breach the integrity of the integrated circuit to further comprise, prior to the operation of detecting the thinning of the substrate, an operation of detecting a removal of at least a portion of the electrically conductive wafer PL.

(42) This operation of detecting the at least local removal of the wafer may then comprise a prior operation of measuring a resistive value of the substrate between the first contact and the wafer.

(43) In other words, the lateral resistance of the substrate is then not taken into account; only the sum of the access resistance RAC and the vertical resistance RVT of the substrate between the first contact PC1 and the wafer PL is.

(44) If the wafer is, for example, removed locally vertically in line with the first contact, then this measured resistance becomes very high.

(45) In terms of current, if the wafer is, for example, removed locally vertically in line with the first contact PC1, then the measured value of the current becomes very low.

(46) From a hardware point of view, the integrated circuit may include to this end, as illustrated schematically in FIG. 3, a second detection circuit MS2 that is configured to detect, prior to the operation of detecting of the thinning of the substrate, a removal of at least a portion of the electrically conductive wafer PL.

(47) More specifically, it is possible, for example, to provide a switch SW allowing the first current measurement circuit MES1 to be disconnected from the second contact PC2 for the purpose of taking this prior measurement.

(48) The second measurement circuit MS2 then includes the circuit GT1 that is configured to apply the voltage V1 to the first contact PC1, the wafer PL being grounded.

(49) The measurement circuit MS2 also includes a second current measurement circuit MES2, for example with a structure that is analogous to that of the first current measurement circuit MES1, that is configured to measure the current I2 resulting from the difference in voltage V1-0 applied between the contact PC1 and the wafer PL.

(50) The second current measurement circuit MES2 may then compare this current I2 with a second threshold for the purpose of detecting a removal of the wafer PL.

(51) As illustrated in FIG. 4, in order to provide more effective protection from an attempt to breach the integrity of the integrated circuit by thinning the substrate and/or at least locally removing the wafer PL, it is advantageous to provide a first contact group formed by a plurality of first contacts PC1 that are distributed over the front face FV of the integrated circuit and a second contact group formed by a plurality of second contacts PC2 that are distributed over said front face FV.

(52) Although not the only possible configuration, as explained above, all of the first contacts PC1 are electrically connected to one another and all of the second contacts PC2 are electrically connected to one another in the example described here.

(53) The first measurement of the current I1 is then advantageously taken between the first contact group of contacts PC1, the second contact group of contacts PC2 and the electrically conductive wafer PL.

(54) Similarly, the second measurement of the current I2 may advantageously be taken between the first contact group of a plurality of first contacts PC1 and the electrically conductive wafer PL.

(55) Reference is now made more particularly to FIGS. 5 to 7 in order to illustrate implementations of a method according to the invention.

(56) In FIG. 5, after the integrated circuit has been powered up 50, in step 51, the semiconductor wafer PL is removed, at least locally.

(57) If a removal is indeed detected, then an alarm signal may be transmitted.

(58) The term “alarm signal” is understood to mean for example a signal allowing conventional countermeasure means for countering such an attack to be triggered, or the operation of the integrated circuit to be stopped.

(59) If an at least local removal of the conductive wafer PL is not detected, then the method moves on to step 53 in which a thinning of the substrate is detected.

(60) If even minimal thinning of the substrate is detected, then the method returns to step 52 of transmitting the alarm signal.

(61) However, if no thinning of the substrate is detected, then the integrated circuit is considered to be operational.

(62) As already mentioned above and as illustrated in FIG. 6, step 51 of detecting an at least local removal of the wafer PL may comprise an operation of applying 510 the voltage V1 to the contact PC1 and an operation of grounding the wafer PL. The switch SW is open.

(63) Next, the resulting current I2 is measured at the contact PC1 (step 511).

(64) This current I2 is then compared with a threshold TH2 (step 512) in order to determine whether an at least local removal of the wafer PL has taken place.

(65) With regard to step 53, as illustrated in FIG. 7, it may also comprise an operation of applying the voltage V1 to the contact PC1 and an operation of grounding the wafer PL (step 530).

(66) This operation 530 is followed by the operation of measuring the current I1 (step 531) at the second contact PC2 (switch SW closed) then by an operation of comparing this current I1 with another threshold TH1 (step 532).