SEMICONDUCTOR COMPONENT INCLUDING A DIELECTRIC LAYER

Abstract

A semiconductor component that includes at least one dielectric layer and at least one first electrode and one second electrode. A first defect type and a second defect type, which is different from the first defect type, are also present in dielectric layer. The at least two different defect types accumulate at one of the two electrodes as a function of a main operating voltage applied between the first electrode and the second electrode, and of a main operating temperature that is present at characteristic times τ.sub.1 and τ.sub.2, and generate the maximum changes in barrier height δΦ.sub.1 and δΦ.sub.2 at the electrodes. τ.sub.1 and δΦ.sub.1 are associated with the first defect type, and τ.sub.2 and δΦ.sub.2 are associated with the second defect type. τ.sub.1<τ.sub.2 and δΦ.sub.1<δΦ.sub.2 apply.

Claims

1-7. (canceled)

8. A semiconductor component, comprising: at least one dielectric layer; and at least one first electrode and at least one second electrode, wherein at least one first defect type and at least one second defect type, which is different from the first defect type, are present in the dielectric layer, the at least one first defect type and the at least one second defect type accumulating at one of the first and second electrodes, as a function of a main operating voltage applied between the first electrode and the second electrode, and a main operating temperature that is present at characteristic times τ.sub.1 and τ.sub.2, and generating maximum changes in barrier height δΦ.sub.1 and δΦ.sub.2 at the first and second electrodes, τ.sub.1 and δΦ.sub.1 being associated with the first defect type, and τ.sub.2 and δΦ.sub.2 being associated with the second defect type, where τ.sub.1<τ.sub.2 and δΦ.sub.1<δΦ.sub.2 apply.

9. The semiconductor component as recited in claim 8, wherein at least one further, third defect type is present in the dielectric layer, the third defect type accumulating at one of the first and second electrodes as a function of the main operating voltage applied between the first electrode and the second electrode, and of the main operating temperature that is present, at a characteristic time τ.sub.3, and generating a maximum change in barrier height δΦ.sub.3 at the first and second electrodes, where τ.sub.1<τ.sub.2<τ.sub.3 applies, a sequence of the change in barrier height differing from a sequence δΦ.sub.1>δΦ.sub.2>δΦ.sub.3.

10. The semiconductor component as recited in claim 8, wherein the dielectric layer is a polycrystalline oxidic high-k dielectric.

11. The semiconductor component as recited in claim 10, wherein the dielectric layer is a PZT layer or a KNN layer.

12. The semiconductor component as, recited in claim 8, wherein the dielectric layer is a sputtered PZT layer.

13. The semiconductor component as recited in claim 12, wherein the sputtered PZT layer has a PZT deposition temperature of less than 500° C.

14. The semiconductor component as recited in claim 12, wherein the sputtered PZT layer has a composition of Pb.sub.x(Zr.sub.0.52Ti.sub.0.48)O.sub.3, where 1.2≤x≤1.3.

15. The semiconductor component as recited in claim 12, wherein the sputtered PZT layer has a nickel content between 0.1 and 1 atom percent.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0041] FIG. 1A shows the curve of a leakage current measurement for five different dielectric layers.

[0042] FIG. 1B shows the temporal profile of the effective barrier height that results from a leakage current measurement, and the subdivision into the contributions of the defect types that are present.

[0043] FIG. 2A shows the maximum changes in barrier height and characteristic time constants of three exemplary embodiments for the operating state 175° C./−2.5 V by way of example.

[0044] FIG. 2B shows the maximum changes in barrier height and characteristic time constants for one exemplary embodiment for two operating states 175° C./−2.5 V and 100° C./−10 V by way of example.

[0045] FIG. 2C shows the maximum changes in barrier height and characteristic time constants of two exemplary embodiments for the operating state 175° C./−2.5 V by way of example.

[0046] FIG. 2D shows the maximum changes in barrier height and characteristic time constants of two exemplary embodiments for the operating state 175° C./−2.5 V by way of example.

[0047] FIG. 2E shows the maximum changes in barrier height and characteristic time constants of two exemplary embodiments for the operating state 100° C./−10 V by way of example.

[0048] FIGS. 3A through 3D schematically show the movement of different defect types in a dielectric layer along localized defect states, each with an average effective distance a.sub.0.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

[0049] FIG. 1A shows curve 14 of a leakage current measurement of a dielectric layer of a semiconductor component, referred to below as exemplary embodiment 1. Time is logarithmically plotted on X axis 12 in units of seconds, and the leakage current density is logarithmically plotted on Y axis 10 in units of amperes per square centimeter. Exemplary embodiment 1, provided for the leakage current measurement, encompassed a silicon substrate including dielectric passivation layers and a first electrode deposited thereon. This first electrode included a double layer made of PVD platinum 110 nm thick, which was covered by a conductive 100-nm lanthanum nickel oxide buffer layer (referred to below as an LNO layer). This LNO layer was likewise applied via PVD. The dielectric layer situated on the first electrode had a thickness of 1 μm, and was deposited in an RF PVD process at a temperature of 480° C. and with a target composition of Pb.sub.1.3(Zr.sub.0.52Ti.sub.0.48)O.sub.3. The remaining process parameters of the above-described depositions were selected in such a way that the dielectric layer had polycrystalline growth, preferably with a (100) c axis orientation. The second electrode of the semiconductor element, which represented a platinum electrode 110 nm thick, was applied to the dielectric layer via PVD. The semiconductor component corresponding to exemplary embodiment 1 was passivated, and was not subjected to thermal aftertreatment after the passivation and the electrical contacting.

[0050] In addition, FIG. 1A shows curve 16 of a leakage current measurement of a dielectric layer of a further semiconductor component, referred to below as exemplary embodiment 2.

[0051] The production of exemplary embodiment 2 took place analogously to exemplary embodiment 1, except that the components were subjected to thermal aftertreatment after electrical contacting. The thermal aftertreatment was carried out at 450° C. for 40 minutes in a 60 mbar nitrogen atmosphere.

[0052] Furthermore, FIG. 1A shows curve 18 of a leakage current measurement of a dielectric layer of a further semiconductor component, referred to below as exemplary embodiment 3. The production of exemplary embodiment 3 took place analogously to exemplary embodiment 1, except that the components were subjected to thermal aftertreatment after electrical contacting. The thermal aftertreatment was carried out at 500° C. for 40 minutes in a 60 mbar nitrogen atmosphere.

[0053] Moreover, FIG. 1A shows curve 20 of a leakage current measurement of a dielectric layer of a further semiconductor component, referred to below as exemplary embodiment 4. The production of exemplary embodiment 4 took place analogously to exemplary embodiment 1, except that the dielectric layer was deposited with a target composition of Pb.sub.1.2(Zr.sub.0.52Ti.sub.0.48)O.sub.3.

[0054] Furthermore, FIG. 1A shows curve 22 of a leakage current measurement of a dielectric layer of a further semiconductor component, referred to below as exemplary embodiment 5. The production of exemplary embodiment 5 took place analogously to exemplary embodiment 1, except that the dielectric layer was deposited with a target composition of Pb.sub.1.3(Zr.sub.0.52Ti.sub.0.48)O.sub.3Ni.sub.0.005.

[0055] Prior to the measurement of the leakage current curves, all described exemplary embodiments 1, 2, 3, 4, and 5 were covered with passivation layers and electrically contacted via aluminum strip conductors.

[0056] Four of the five exemplary embodiments were measured up to the respective dielectric breakdown 15, 17, 19, and 24. It is apparent that very different leakage current curves 14, 16, 18, 20, and 22 with different breakdown times 17, 15, 19, and 24 result, depending on the production and the composition of a dielectric layer.

[0057] FIG. 1B shows an example of the extraction of model variables based on measured leakage current curve 16 for exemplary embodiment 2, based on FIG. 1A. Once again, time is logarithmically plotted on X axis 32 in units of seconds, and change in barrier height Δϕ is logarithmically plotted on Y axis 30 in units of electron volts. Curve 38 shows the ascertained curve of the change in barrier height Δϕ(t) as a function of time, starting from an output barrier height ϕ.sub.0.

[0058] This curve 38 of change in barrier height Δϕ(t) is ascertained by the following formula (cf. above formula 2.2):

[00016]$\Phi \left(t\right)=\left[\ln \left(K\right)-\ln \left(J_{TED}\left(t\right)\right)\right]k_{B}T$

[0059] The ascertained temporal profile of average effective barrier height ϕ(t) is subsequently numerically adapted to the formula (cf. above formula 3.2):

[00017]$\varphi \left(t\right)={\varphi }_0+{.Math.}_i\Delta {\varphi }_i^{+}\left(t\right)+{.Math.}_i\Delta {\varphi }_i^{-}\left(t\right)$

[0060] Correspondingly different Δϕ.sub.i.sup.+/−(t)'s which describe the curve of Δϕ(t) are obtained from this numerical fit. Thus, in the case shown, Δϕ(t) 38 is described by the curve of Δϕ.sub.a.sup.−(t) 39, the curve of Δϕ.sub.b.sup.−(t) 40, and the curve of Δϕ.sub.c.sup.−(t) 42, together with summation curve Σ.sub.iΔϕ.sub.i.sup.+ 36. According to the following formula (cf. above formula 5.1)

[00018]$\Delta \varphi \left(t\right)={.Math.}_i\delta {\varphi }_i^{+/-}\left(1-e^{\frac{t}{{\tau }_i^{+/-}}}\right)$

the different τ.sub.i.sup.+/−'s and δϕ.sub.i.sup.+/−'s may then be ascertained. In this case, for changes in barrier height Δϕ.sub.i.sup.− 39, 40, and 42 associated with the majority charge carriers, associated characteristic time constants τ.sub.a, τ.sub.b, and τ.sub.c are obtained. These time constants are characterized in FIG. 1B by 47a, 47b, and 47c, respectively, and represent the point in time at which the corresponding change in barrier height changes most greatly. Associated maximum barrier decreases δϕ.sub.i.sup.− for curves Δϕ.sub.i.sup.− 39, 40 are denoted by reference numerals 50 and 51 by way of example. In order to improve clarity, the changes in barrier height for minority charge carriers Δϕ.sup.+ have not been explicitly individually illustrated. Only their summation curve Σ.sub.iΔϕ.sub.i.sup.+ 36 together with individual time constants τ.sub.d, τ.sub.e, and τ.sub.f 49a, 49b, and 49c are shown. A particular characteristic time constant is associated with a defect type a, b, c, d, e, and f that is present in the layer. Accordingly, six different defect types are thus present in this dielectric layer.

[0061] In the case illustrated in FIG. 1B, dielectric breakdown 47 of the dielectric layer takes place via tunneling majority charge carriers corresponding to the following formula (cf. above formula 9.2):

[00019]${\varphi }_{\mathrm{crit}}^{-}={\varphi }_0^{-}+{.Math.}_i{\mathrm{\Delta \varphi }}_i^{-}\left(t_{\mathrm{crit}}\right)={\varphi }_0^{-}+{\mathrm{\Delta \varphi }}_{\mathrm{crit}}^{-},\mathrm{where}{\mathrm{\Delta \varphi }}_{\mathrm{crit}}^{-}={.Math.}_i{\mathrm{\Delta \varphi }}_i^{-}\left(t_{\mathrm{crit}}\right)$

[0062] The previously ascertained curves of Δϕ.sub.a.sup.−(t) 39, Δϕ.sub.b.sup.−(t) 40, and Δϕ.sub.c.sup.−(t) 42 are thus summed, resulting in changes in barrier height Σ.sub.i Δϕ.sup.− 44, corresponding to its curve. If change in barrier height Δϕ.sub.crit.sup.− 52 of the dielectric layer, which is critical for the majority charge carriers, is reached at point in time t.sub.crit 48, this results in a local breakdown of the layer due to the different defect types a, b, and c present which have accumulated at a boundary layer between the dielectric layer and the electrode.

[0063] FIG. 2A shows the measured curves of changes in barrier height Δϕ(t).sup.± for the three exemplary embodiments 1, 2, and 3, together with respective characteristic time constants τ.sub.i.sup.+/− and maximum changes in barrier height δϕ.sup.+/− at a main operating temperature of 175° C. and a main operating voltage of −2.5 V. Time is logarithmically plotted on X axis 62 in units of seconds, and the change in barrier height divided by critical change in barrier height Δϕ.sub.crit.sup.− of the particular exemplary embodiment 1, 2, and 3 is plotted on Y axis 60 without units.

[0064] The curves of Δϕ(t).sup.− 63, 64, 65 for exemplary embodiments 3, 2, and 1 as well as the associated curves of Δϕ(t).sup.+ 66, 67, 68 of exemplary embodiments 3, 2, and 1 are illustrated. The electrical failure of the dielectric layers in the exemplary embodiments takes place in each case at associated points in time 94, 96, and 98 at which the critical decrease in barrier height is reached.

[0065] The defect structure for exemplary embodiment 1 is made up of defect types a, b, c, d, e, and f together with their associated time constants τ.sub.a 72a, τ.sub.b 72b, T.sub.c 72c, τ.sub.d 90a, τ.sub.e 70b, and τ.sub.f 70c. Resulting maximum decreases in barrier height δϕ.sub.b.sup.− 72c, δϕ.sub.c.sup.− 73c, δϕ.sub.d.sup.+ 91a, δϕ.sub.e.sup.+ 71b, and δϕ.sub.f.sup.+ 71c are associated with the different defect types.

[0066] The defect structure for exemplary embodiment 2 is made up of defect types a, b, c, d, e, and f together with their associated time constants τ.sub.a 82a, τ.sub.b 82b, τ.sub.c 82c, τ.sub.d 80a, τ.sub.e 80b, and τ.sub.f 80c. In addition, resulting maximum decreases in barrier height δϕ.sub.a.sup.− 83a, δϕ.sub.b.sup.− 83b, δϕ.sub.c.sup.− 83 c, δϕ.sub.d.sup.+ 81a, δϕ.sub.e.sup.+ 81b, and δϕ.sub.f.sup.+ 81c are associated with the different defect types.

[0067] The defect structure for exemplary embodiment 3 is made up of defect types a, b, c, d, e, and f together with their associated time constants τ.sub.a 92a, τ.sub.b 92b, τ.sub.c 92c, τ.sub.d 70a, τ.sub.e 90b, and τ.sub.f 90c. Once again, resulting maximum decreases in barrier height δϕ.sub.a.sup.− 93a, δϕ.sub.b.sup.− 93b, δϕ.sub.c.sup.− 93c, δϕ.sub.d.sup.+ 71a, δϕ.sub.e.sup.+ 91b, and δϕ.sub.f.sup.+ 91c are associated with the different defect types.

[0068] True activation energies E.sub.A,0,i and charges N.sub.q,i may be ascertained for the different defect types by mathematical fitting to the above-described model and the following equation (cf. above equation 10.1).

[00020]${\tau }_i\left(E;T\right)=\frac{d_i}{C_{0,i}\left(a_0\right)e^{-\frac{E_{A,o,i}}{k_{B}T}}}\frac{1}{\sin h\left(\frac{N_{q,i}{a}_0}{k_{B}T}E\right)}$

[0069] A true activation energy of 0.92 eV with a charge of 1 e results for defect type a. A true activation energy of 0.95 eV with a charge of 3 e results for defect type b. A true activation energy of 0.855 eV with a charge of 4 e results for defect type c. A true activation energy of <0.8 eV with a charge of 1 e results for defect type d. A true activation energy of 1.04 eV with a charge of 2 e results for defect type e. A true activation energy of 1.22 eV with a charge of 2 e results for defect type f. In this way, for example defect type a may be physically joined to hydrogen and/or OH groups, and defect type e may be physically joined to oxygen vacancies and/or lead within the dielectric layer. Due to the different types of production of exemplary embodiments 1, 2, and 3, the maximum decreases in barrier height of defect types a and e, δϕ.sub.a.sup.− and δϕ.sub.e.sup.+, respectively, are changed. For the main operating conditions selected here by way of example, τ.sub.a<τ.sub.b and δϕ.sub.a.sup.−<δϕ.sub.b.sup.− apply for exemplary embodiments 1 and 2 of the semiconductor component. Barrier curve 63 of exemplary embodiment 3 is influenced by relatively large barrier decrease 93a of exemplary embodiment 3, which takes place at a relatively early point in time 92a. This results in an earlier electrical failure at point in time t.sub.crit 98 in comparison to failure points in time t.sub.crit 94 or 96 of exemplary embodiments 1 or 2. To achieve a longer service life of the semiconductor component, barrier decreases that take place early should be correspondingly small. For exemplary embodiments 1 and 2, it is also shown that τ.sub.a<τ.sub.b<τ.sub.c and δϕ.sub.a.sup.−<δϕ.sub.b.sup.−<δϕ.sub.c.sup.−.

[0070] FIG. 2B shows a comparison of the curves of changes in barrier height Δϕ(t).sup.± for exemplary embodiment 2 for two different operating conditions, together with particular characteristic time constants τ.sub.i.sup.+/− and maximum changes in barrier height δϕ.sub.i.sup.+/−. Time is logarithmically plotted on X axis 62 in units of seconds, and the change in barrier height divided by critical change in barrier height Δϕ.sub.crit.sup.− of the particular operating state is plotted on Y axis 60 without units.

[0071] This results in curve Δϕ(t).sup.− 64 for the main operating temperature 175° C. and a main operating voltage of −2.5 V (referred to below as operating condition a), and curve Δϕ(t).sup.− 110 for the main operating temperature 100° C. and a main operating voltage of −10 V (referred to below as operating condition b). Associated curve Δϕ(t).sup.+ 67 for operating condition a and curve Δϕ(t).sup.+ 100 for operating condition b are likewise illustrated.

[0072] The electrical failure of the dielectric layer takes place for operating conditions a and b at points in time 96 and 97, respectively. The defect structure for exemplary embodiment 2 for operating condition a is formed by active defect types a, b, c, d, e, and f together with their associated time constants τ.sub.a 82a, τ.sub.b 82b, τ.sub.c 82c, τ.sub.d 80a, τ.sub.e 80b, and τ.sub.f 80c up to electrical failure, and maximum decreases in barrier height δϕ.sub.a.sup.− 83a, δϕ.sub.b.sup.− 83b, δϕ.sub.c.sup.− 83c, δϕ.sub.d.sup.+ 81a, δϕ.sub.e.sup.+ 81b, and δϕ.sub.f.sup.+ 81c caused by these defect types.

[0073] The defect structure for exemplary embodiment 2 for operating condition b is formed by active defect types a, b, d, and e together with their associated time constants τ.sub.a 170a, τ.sub.b 170b, T.sub.d 101a, and τ.sub.e 101b up to electrical failure, and maximum decreases in barrier height δϕ.sub.a.sup.− 171a, δϕ.sub.b.sup.− 171b, δϕ.sub.d.sup.+ 102a, and δϕ.sub.e.sup.+ 102b caused by these defect types.

[0074] It is apparent that the defect structure and the active defects in a semiconductor component up to electrical breakdown are a function of the selected operating condition. Time shifts 106 result from the main operating temperature and term

[00021]$e^{-\frac{E_{A,0,i}}{k_{B}T}}$

in equation (10.1). Changes 105 in the maximum decreases in barrier height result from changes in the main operating voltage and accompanying changes in Δϕ.sub.crit.sup.±.

[0075] For exemplary embodiment 2, τ.sub.a<τ.sub.b<τ.sub.c and δϕ.sub.a.sup.−<δϕ.sub.b.sup.−<δϕ.sub.c.sup.−, and τ.sub.d<τ.sub.e<τ.sub.f and δϕ.sub.d.sup.+<δϕ.sub.e.sup.+<δϕ.sub.f.sup.+, apply for operating conditions a. In addition, for exemplary embodiment 2 τ.sub.a<τ.sub.b and δϕ.sub.a.sup.−<δϕ.sub.b.sup.−, and τ.sub.d<τ.sub.e and δϕ.sub.d.sup.+<δϕ.sub.e.sup.+, apply for operating conditions b.

[0076] FIG. 2C shows a comparison of the curves of changes in barrier height Δϕ(t).sup.± for the two exemplary embodiments 2 and 4 together with their particular characteristic time constants τ.sub.i.sup.+/− and maximum changes in barrier height δϕ.sub.i.sup.+/− at a main operating temperature of 175° C. and a main operating voltage of −2.5 V. Time is logarithmically plotted on X axis 62 in units of seconds, and the change in barrier height divided by critical change in barrier height Δϕ.sub.crit of exemplary embodiment 2 is plotted on Y axis 60 without units. The change in barrier height in exemplary embodiment 4 has been normalized in such a way that maximum changes in barrier height δϕ.sub.a.sup.− 132a and δϕ.sub.a.sup.− 83a are identical.

[0077] Curve Δϕ(t).sup.− 64 of exemplary embodiment 2 and curve Δϕ(t).sup.− 130 of exemplary embodiment 4 are illustrated. Curve Δϕ(t).sup.+ 67 of exemplary embodiment 2 and curve Δϕ(t).sup.+ 120 of exemplary embodiment 4 are also illustrated. The electrical failure of the dielectric layer of exemplary embodiment 2 takes place at point in time 96 when the critical decrease in barrier height is reached. During the test period it was not possible to subject exemplary embodiment 4 to load to the point of failure, and therefore curve 130 does not reach the value −1.

[0078] The defect structure for exemplary embodiment 2 is formed by defect types a, b, c, d, e, and f together with their associated time constants τ.sub.a 82a, τ.sub.b 82b, τ.sub.c 82c, τ.sub.d 80a, τ.sub.e 80b, and τ.sub.f 80c, and maximum decreases in barrier height δϕ.sub.a.sup.− 83a, δϕ.sub.b.sup.− 83b, δϕ.sub.c.sup.− 83c, δϕ.sub.d.sup.+ 81a, δϕ.sub.e.sup.+ 81b, and δϕ.sub.f.sup.+ 81c caused by these defect types.

[0079] The defect structure for exemplary embodiment 4 is formed by defect types a, c, d, and e together with their associated time constants τ.sub.a 131a, τ.sub.c 131b, τ.sub.d 121a, and τ.sub.e 121b, and maximum decreases in barrier height δϕ.sub.a.sup.− 132a, δϕ.sub.c.sup.− 132b, and δϕ.sub.d.sup.+ 122a caused by these defect types.

[0080] A true activation energy of 0.92 eV with a charge of 1 e results for defect type a. A true activation energy of 0.95 eV with a charge of 3 e results for defect type b. A true activation energy of 0.855 eV with a charge of 4 e results for defect type c. A true activation energy of <0.8 eV with a charge of 1 e results for defect type d. A true activation energy of 1.04 eV with a charge of 2 e results for defect type e. A true activation energy of 1.22 eV with a charge of 2 e results for defect type f. Due to the reduction of the lead content in the sputtered PZT layer of exemplary embodiment 4, it was possible to reduce maximum decreases in barrier height δϕ.sub.b.sup.−, δϕ.sub.c.sup.−, and δϕ.sub.f.sup.+ of defect types b, c, and f associated with lead, in comparison to exemplary embodiment 2. This reduction is denoted by reference numeral 115 by way of example for δϕ.sub.c.sup.− 132b. Maximum decreases in barrier height δϕ.sub.b.sup.− and δϕ.sub.f.sup.+ are so small that they are no longer discernibly present due to the numerical fit to the model. Since τ.sub.a<τ.sub.b<τ.sub.c for defect type b, it may be deduced that τ.sub.b<τ.sub.c and δϕ.sub.b.sup.−<<δϕ.sub.c.sup.−.

[0081] FIG. 2D shows a comparison of the curves of changes in barrier height Δϕ(t).sup.± for the two exemplary embodiments 2 and 5 together with their particular characteristic time constants τ.sub.i.sup.+/− and maximum changes in barrier height δϕ.sub.i.sup.+/− at a main operating temperature of 175° C. and a main operating voltage of −2.5 V. Time is logarithmically plotted on X axis 62 in units of seconds, and the change in barrier height divided by critical change in barrier height Δϕ.sub.crit of particular exemplary embodiment 2 and 5 is plotted on Y axis 60 without units.

[0082] Curve Δϕ(t).sup.− 64 of exemplary embodiment 2 and curve Δϕ(t).sup.− 150 of exemplary embodiment 5 are illustrated. Associated curve Δϕ(t).sup.+ 67 of exemplary embodiment 2 and curve Δϕ(t).sup.+ 140 of exemplary embodiment 5 are also illustrated. The electrical failure of the dielectric layer of exemplary embodiment 2 takes place at point in time 96, and for exemplary embodiment 5 takes place at point in time 99.

[0083] The defect structure for exemplary embodiment 2 is formed by defect types a, b, c, d, e, and f together with their associated time constants τ.sub.a 82a, τ.sub.b 82b, τ.sub.c 82c, τ.sub.d 80a, τ.sub.e 80b, and τ.sub.f 80c, and maximum decreases in barrier height δϕ.sub.a.sup.− 83a, δϕ.sub.b.sup.− 83b, δϕ.sub.c.sup.− 83c, δϕ.sub.d.sup.+ 81a, δϕ.sub.e.sup.+ 81b, and δϕ.sub.f.sup.+ 81c caused by these defect types. The defect structure for exemplary embodiment 5 is formed by defect types a, b, and d together with their associated time constants τ.sub.a 148a, τ.sub.b 148b, and τ.sub.d 145a, and maximum decreases in barrier height δϕ.sub.a.sup.− 149a, δϕ.sub.b.sup.− 149b, and δϕ.sub.d.sup.+ 146a caused by these defect types.

[0084] A true activation energy of 0.92 eV with a charge of 1 e results for defect type a. A true activation energy of 0.95 eV with a charge of 3 e results for defect type b. A true activation energy of 0.855 eV with a charge of 4 e results for defect type c. A true activation energy of <0.8 eV with a charge of 1 e results for defect type d. A true activation energy of 1.04 eV with a charge of 2 e results for defect type e. A true activation energy of 1.22 eV with a charge of 2 e results for defect type f. Due to the additional nickel content in the sputtered PZT layer of exemplary embodiment 5, it was possible to significantly influence maximum decreases in barrier height δϕ.sub.a.sup.− and δϕ.sub.b.sup.−. In addition, it was possible to reduce maximum decreases in barrier height δϕ.sub.e.sup.+ and δϕ.sub.f.sup.+ to the extent that they are no longer discernibly present due to the numerical fit to the model. For the operating conditions 175° C. and −2.5 V, τ.sub.a<τ.sub.b and δϕ.sub.a.sup.−<δϕ.sub.b.sup.− apply for exemplary embodiment 5.

[0085] FIG. 2E shows a comparison of the curves of changes in barrier height Δϕ(t).sup.± for the two exemplary embodiments 2 and 5 at a main operating temperature of 100° C. and a main operating voltage of −10 V, together with particular characteristic time constants τ.sub.i.sup.+/− and maximum changes in barrier height δϕ.sub.i.sup.+/−. Time is logarithmically plotted on X axis 155 in units of seconds, and the change in barrier height divided by critical change in barrier height Δϕ.sub.crit.sup.− of particular exemplary embodiment 2 and 5 is plotted on Y axis 156 without units.

[0086] Curve Δϕ(t).sup.− 110 of exemplary embodiment 2 and curve Δϕ(t).sup.− 169 of exemplary embodiment 5 are illustrated. Associated curve Δϕ(t).sup.+ 100 of exemplary embodiment 2 and curve Δϕ(t).sup.+ 165 of exemplary embodiment 5 are also illustrated. The electrical failure of the dielectric layer of exemplary embodiment 2 takes place at point in time 96c, and for exemplary embodiment 5 takes place at point in time 96d.

[0087] The defect structure for exemplary embodiment 2 is formed by active defect types a, b, d, and e together with their associated time constants τ.sub.a 170a, τ.sub.b 170b, τ.sub.d 161a, and τ.sub.e 161b, and maximum decreases in barrier height δϕ.sub.a.sup.− 171a, δϕ.sub.b.sup.− 171b, δϕ.sub.d.sup.+ 162a, and δϕ.sub.e.sup.+ 162b caused by these defect types.

[0088] The defect structure for exemplary embodiment 5 is formed by defect types a and d together with their associated time constants τ.sub.a 175a and τ.sub.d 158a, and maximum decreases in barrier height δϕ.sub.a.sup.− 176a and δϕ.sub.d.sup.+ 159a caused by these defect types.

[0089] A true activation energy of 0.92 eV with a charge of 1 e results for defect type a. A true activation energy of 0.95 eV with a charge of 3 e results for defect type b. A true activation energy of <0.8 eV with a charge of 1 e results for defect type d. A true activation energy of 1.04 eV with a charge of 2 e results for defect type e. Due to the additional nickel content in the sputtered PZT layer of exemplary embodiment 5, it was possible to significantly influence maximum decrease in barrier height δϕ.sub.a.sup.− 176a. In addition, it was possible to reduce maximum decrease in barrier height W to the extent that it is no longer discernibly present due to the numerical fit to the model.

[0090] For exemplary embodiment 2, τ.sub.a<τ.sub.b and δϕ.sub.a.sup.−<δϕ.sub.b.sup.−, and τ.sub.d<τ.sub.e and δϕ.sub.d.sup.+<δϕ.sub.e.sup.+, apply for the operating conditions 100° C. and −10 V.

[0091] FIG. 3A schematically shows a semiconductor component 200 at a first point in time t.sub.0. Semiconductor component 200 includes a dielectric layer 230 having a layer thickness 208. Dielectric layer 230 may be a PZT layer, for example. In addition, semiconductor component 200 includes a first electrode 202 and an electrode 201 that are situated opposite one another. A boundary layer 203 or 204 is also situated between a particular electrode 201 or 202 and dielectric layer 230. Different defect types are present in dielectric layer 230, which are denoted here by way of example as defect type 212 with a single positive charge 214, and defect types 215 and 217 with a single negative charge 216. Indices + and − denote the number of charge carriers of a defect type in question. Defect pairs or defect accumulations are present due to the necessary charge neutrality in dielectric layer 230. This means that when defects with a negative charge 215 and 217 occur, defects with a positive charge 212 also exist in the material. The different defect types 212, 215, and 217 are situated on localized anomalies 235. At first point in time t.sub.0 illustrated in FIG. 3A, no voltage between the electrodes 201 and 202, and thus also no electrical field, has yet been applied.

[0092] FIG. 3B shows semiconductor component 200 at a second point in time t.sub.1 subsequent to first point in time t.sub.0. A voltage is applied between first electrode 202 and second electrode 201, and thus an electrical field 220 is generated in the dielectric layer 230, at this point in time t.sub.1. The different defect types 212, 215, and 217 now vary as a function of the main operating voltage applied between first electrode 201 and second electrode 202 and a main operating temperature that is present along localized defect states 235. This movement state of defect types 212, 215, and 217 is also referred to as “hopping.” Each defect type moves in the direction of a corresponding electrode, at a different velocity. The particular time required by a defect type to reach a particular boundary layer, associated with an electrode after application of the main operating voltage, from the starting position is referred to as characteristic time x. Localized defect states 235 each have same average effective distance a.sub.0 210. Defect types 212 with a positive charge 214 migrate to the electrode having a negative potential (in this case, first electrode 202) and accumulate in boundary layer 203 there. In contrast, defect types 215 and 217 with negative charge 216 move toward the electrode having a positive potential (in this case, second electrode 201) and accumulate in boundary layer 204 there. Charge carriers of leakage current J.sub.TED, which seek to move from one electrode to the other, must overcome Schottky barriers ϕ(t), which are influenced by boundary layers 203 and 204. These barriers have an output barrier height ϕ.sub.0, and undergo changes in barrier height Δϕ.sub.i due to the defect types that accumulate there, which in the further temporal profile result in a maximum change in barrier height δΦ.sub.i. The defect types in each case create a different change in barrier height ΔΦ.sub.i.

[0093] FIG. 3C shows semiconductor component 200 at a third point in time t.sub.2 subsequent to second point in time. A plurality of the different defect types 212, 215, and 217 have already accumulated at boundary layers 202 and 203 of dielectric layer 230 and resulted in changes in barrier height Δϕ.sub.i there. A critical barrier height ϕ.sub.crit is reached at one of boundary layers 202 or 203 at a fourth point in time t.sub.3 subsequent to the third point in time. As is apparent from FIG. 3D, this now results in a local dielectric breakdown 225 of dielectric layer 230. A semiconductor component 200, which is locally destroyed on a limited surface, remains after t.sub.crit is exceeded. This is followed by even further local dielectric breakdowns 225 under continuing load at t>t.sub.crit, which ultimately results in complete destruction of semiconductor component 200.