Sampling switch circuits

Abstract

A sampling switch circuit, comprising: an input node, connected to receive an input voltage signal to be sampled; a sampling transistor comprising a gate terminal, a source terminal and a drain terminal, the source terminal connected to the input node; a potential divider circuit connected to the input node and a track-control node to provide a track-control voltage signal dependent on the input voltage signal at the track-control node; a hold-control node connected to receive a hold-control voltage signal; an output node connected to the drain terminal of the sampling transistor; and switching circuitry configured to connect the gate terminal of the sampling transistor to the track-control node or to the hold-control node in dependence upon a clock signal.

Claims

1. A sampling switch circuit, comprising: an input node, connected to receive an input voltage signal to be sampled; a sampling transistor comprising a gate terminal, a source terminal and a drain terminal, the source terminal connected to the input node; a potential divider circuit connected to the input node and a track-control node to provide a track-control voltage signal dependent on the input voltage signal at the track-control node; a hold-control node connected to receive a hold-control voltage signal; an output node connected to the drain terminal of the sampling transistor; and switching circuitry configured to connect the gate terminal of the sampling transistor to the track-control node or to the hold-control node in dependence upon a clock signal.

2. The sampling switch circuit as claimed in claim 1, wherein: the potential divider circuit is configured such that, when the gate terminal of the sampling transistor is connected to the track-control node, the sampling transistor is ON and a voltage at the drain terminal of the sampling transistor and/or the output node tracks a voltage at the source terminal of the sampling transistor; and/or when the gate terminal of the sampling transistor is connected to the hold-control node, the sampling transistor is OFF and a voltage at the drain terminal of the sampling transistor and/or at the output node is at least temporarily maintained or held.

3. The sampling switch circuit as claimed in claim 2, wherein the track-control voltage signal has a track-control AC component defined at least by the input voltage signal and a track-control DC component defined at least by the potential divider circuit.

4. The sampling switch circuit as claimed in claim 3, wherein the potential divider circuit is configured to maintain the track-control voltage signal at the track-control node, optionally with the track-control AC component maintained as defined at least by the input voltage signal and the track-control DC component maintained as defined at least by the potential divider circuit, optionally as continuous signals and optionally independently of the clock signal.

5. The sampling switch circuit as claimed in claim 3, wherein the potential divider circuit is connected to a sample node to provide a sample voltage signal at the sample node which has a sample AC component defined at least by the input voltage signal and a sample DC component defined at least by the potential divider circuit, the source terminal of the sampling transistor connected to the sample node and connected to the input node via the sample node.

6. The sampling switch circuit as claimed in claim 5, wherein the potential divider circuit is configured to maintain the sample voltage signal at the sample node, optionally with the sample AC component maintained as defined at least by the input voltage signal and the sample DC component maintained as defined at least by the potential divider circuit, optionally as continuous signals and optionally independently of the clock signal.

7. The sampling switch circuit as claimed in claim 5, wherein the potential divider circuit is configured such that the track-control DC component and the sample DC component are different from one another in voltage level.

8. The sampling switch circuit as claimed in claim 1, wherein: the potential divider circuit is connected to a first reference node and a second reference node, the first reference node connected to receive a first reference voltage signal having a first reference DC component and the second reference node connected to receive a second reference voltage signal having a second reference DC component; and the first reference DC component and the second reference DC component are configured to cause the difference between voltage levels of the track-control DC component and the sample DC component to be greater than or equal to the threshold voltage of the sampling transistor.

9. The sampling switch circuit as claimed in claim 8, wherein the potential divider circuit comprises: a first impedance connected between the input node and the track-control node; a second impedance connected between the track-control node and the first reference node; a third impedance connected between the input node and the sample node; and a fourth impedance connected between the sample node and the second reference node.

10. The sampling switch circuit as claimed in claim 9, wherein: the first impedance is implemented as a resistor or as a resistor connected in series with a capacitor, or as a resistor connected in parallel with a capacitor, or as a capacitor connected in series with a parallel combination of impedances, the parallel combination of impedances comprising a resistor connected in parallel with a capacitor; and/or the second impedance is implemented as a resistor, or as a resistor connected in series with an inductor; and/or the third impedance is implemented as a resistor, or as a resistor connected in parallel with a capacitor; and/or the fourth impedance is implemented as a resistor, or as a resistor connected in series with a parallel combination of impedances, that parallel combination of impedances comprising a resistor connected in parallel with a capacitor, optionally wherein that parallel combination of impedances is connected to the second reference node.

11. The sampling switch circuit as claimed in claim 1, wherein the hold-control voltage signal has a hold-control DC component, and a difference between voltage levels of the hold-control DC component and the sample DC component is less than the threshold voltage of the sampling transistor.

12. The sampling switch circuit as claimed in claim 1, wherein the switching circuitry comprises a first switch connected between the gate terminal of the sampling transistor and the track-control node and a second switch connected between the gate terminal of the sampling transistor and the hold-control node, optionally wherein the first and second switches are implemented with transistors, optionally wherein: the first switch is connected in series with a resistance between the gate terminal of the sampling transistor and the track-control node, optionally wherein that resistance is implemented with one or more transistors; and/or the second switch is connected in series with a resistance between the gate terminal of the sampling transistor and the hold-control node, optionally wherein that resistance is implemented with one or more transistors.

13. The sampling switch circuit as claimed in claim 1, configured to have multiple channels, wherein: each said channel comprises its own said sampling transistor, output node, switching circuitry and clock signal; and for each said channel, the source terminal of the sampling transistor is connected to the input node, the output node is connected to the drain terminal of the sampling transistor, and the switching circuitry is configured to connect the gate terminal of the sampling transistor to the track-control node or to the hold-control node in dependence upon the clock signal.

14. An analogue-to-digital converter, comprising the sampling switch circuit as claimed in claim 1.

15. Integrated circuitry, such an IC chip, comprising the sampling switch circuit as claimed claim 1.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Reference will now be made, by way of example, to the accompanying drawings, of which:

(2) FIG. 1, as mentioned above, is a schematic diagram of a previously-considered sampling switch circuit;

(3) FIG. 2 shows a previously-considered bootstrapped circuit, as a detailed implementation of the FIG. 1 circuit;

(4) FIG. 3 is a schematic diagram of the FIG. 2 circuit for use in an understanding of the precharge/hold phase;

(5) FIGS. 4A and 4B are schematic diagrams of the FIG. 2 circuit for use in an understanding of the tracking phase;

(6) FIG. 5 is a schematic diagram of a sampling switch circuit embodying the present invention;

(7) FIG. 6 shows a simplified circuit model representing the voltage on node A of the circuit of FIG. 5;

(8) FIG. 7 is a schematic diagram equivalent to FIG. 6 but indicating AC and DC power flows;

(9) FIG. 8 shows a simplified circuit model representing the voltage on node B of the circuit of FIG. 5;

(10) FIG. 9 is a schematic diagram showing a simplified circuit model representing the FIG. 5 with a focus on its potential divider circuit;

(11) FIG. 10 is a schematic diagram similar to FIG. 9 but showing a parasitic capacitance explicitly;

(12) FIG. 11 is a schematic diagram equivalent to FIG. 5 but indicating respective power flows;

(13) FIGS. 12 and 13 are schematic diagrams of equivalent circuits useful for better understanding the circuit of FIG. 5;

(14) FIG. 14 is a schematic diagram of a sampling switch circuit embodying the present invention;

(15) FIG. 15 is a schematic diagram of a sampling switch circuit embodying the present invention;

(16) FIG. 16 is a schematic diagram of a sampling switch circuit embodying the present invention;

(17) FIG. 17 is a schematic diagram of a sampling switch circuit embodying the present invention;

(18) FIG. 18 is a schematic diagram of a sampling switch circuit embodying the present invention;

(19) FIG. 19 is a schematic diagram of a sampling switch circuit embodying the present invention;

(20) FIG. 20 is a schematic diagram representing a test bench used to compare operation of the circuit of FIG. 2 with that of FIG. 18;

(21) FIG. 21 is a graph showing the amount of on-resistance variation for the circuits of FIGS. 2 and 18;

(22) FIG. 22 is a graph showing the effective bandwidth (EBW) of the sampling switch for the circuits of FIGS. 2 and 18;

(23) FIG. 23 is a schematic diagram of a sampling switch circuit embodying the present invention, used for simulation;

(24) FIG. 24 is a schematic diagram of clock signals corresponding to FIG. 23;

(25) FIGS. 25 to 27 show waveforms respectively on nodes A (FIG. 25) and G (FIG. 26) for both positive and negative rail circuits, and the output (FIG. 27) for all four phases in relation to a simulation of the FIG. 23 circuit;

(26) FIG. 28 shows an FFT spectrum corresponding to FIG. 27;

(27) FIG. 29 is a schematic diagram of an ADC embodying the present invention; and

(28) FIG. 30 is a schematic diagram of integrated circuitry embodying the present invention.

DETAILED DESCRIPTION OF THE DISCLOSURE

(29) Embodiments of the present invention seek to address the above problems.

(30) In particular, by way of overview and recalling the discussion of FIGS. 2 to 4, in embodiments the precharge phase is rendered unnecessary by removing the bulky capacitor C.sub.B from the switching path. By removing the precharge phase, the maximum operation frequency of the clocking circuit is boosted considerably. Further, the state of devices (transistors) is rendered dependent either on clock signals or the input voltage, rather than on the voltage at the gate of the sampling device M.sub.S. The total capacitance at the gate of the sampling switch M.sub.S is also reduced (e.g. by reducing the number of devices—transistors—connected to that node), which enables the tracking time constant to be enhanced (i.e. reduced).

(31) FIG. 5 is a schematic diagram of a sampling switch circuit 100 embodying the present invention. The sampling switch circuit 100 may be referred to for example as a sampling circuit, a sampler circuit, a sampler front-end circuit, an ADC front-end circuit, a sample-and-hold circuit or a sample and hold switch circuit, and the present disclosure will be understood accordingly. Variants of the sampling switch circuit 100, also embodying the present invention, will be considered later herein. Compared to the sampling switch circuit 10, the need for the fairly large capacitor (i.e., C.sub.B) has been removed and the transistor count has been reduced.

(32) The sampling switch circuit 100 comprises an input node (marked as V.sub.IN), a sampling transistor (sampling switch) M.sub.S, a potential divider circuit 110, a track-control node (node A), a sample node (node B), a hold-control node (node C), switching circuitry 120 and an output node (marked as V.sub.OUT).

(33) The input node is connected to receive an input voltage signal V.sub.IN to be sampled. The sampling transistor M.sub.S comprises a gate terminal, a source terminal and a drain terminal, the source terminal connected to the input node. The potential divider circuit 110 is connected to the input node and the track-control node (node A) to provide a track-control voltage signal dependent on the input voltage signal V.sub.IN at the track-control node. The hold-control node (node C) is connected to receive a hold-control voltage signal, in this case a ground supply voltage signal. The switching circuitry 120 is configured to connect the gate terminal of the sampling transistor (either) to the track-control node (node A) or to the hold-control node (node C) in dependence upon a (sampling) clock signal CLK.

(34) In FIG. 5, the potential divider circuit 110 comprises resistors R.sub.1 to R.sub.4 (in later variants, further components are provided). The resistor R.sub.1 is connected between the input node and node A. The resistor R.sub.2 is connected between node A and a first reference node (marked as V.sub.REF) which is connected to receive a first reference signal V.sub.REF, which in this case is a DC (supply) voltage signal (a DC reference voltage) which may be assumed to be higher in voltage level than the (core) supply voltage V.sub.DD. The third resistor R.sub.3 is connected between the input node and node B, which is connected to the source terminal of the sampling transistor M.sub.S. The fourth resistor R.sub.4 is connected between node B and a second reference node which is connected to receive a second reference signal, which in this case is a ground supply voltage signal.

(35) Thus, the potential divider circuit 110 is connected to the track-control node (node A) to provide a track-control voltage signal which has a track-control AC component defined at least by the input voltage signal V.sub.IN and a track-control DC component defined at least by the potential divider circuit 110. Similarly, the potential divider circuit 110 is connected to the sample node (node B) to provide a sample voltage signal at the sample node (node B) which has a sample AC component defined at least by the input voltage signal V.sub.IN and a sample DC component defined at least by the potential divider circuit 110, the source terminal of the sampling transistor M.sub.S connected to the sample node (node B) and connected to the input node via the sample node (node B).

(36) The switching circuitry 120 comprises transistors M.sub.1 and M.sub.2 which act as switches of the switching circuitry 120 and are controlled at their gate terminals by the clock signal CLK. M.sub.1 is connected with its channel between the gate terminal of M.sub.S (marked as node G′) and node A, and M.sub.2 is connected with its channel between node G′ and node C.

(37) Transistors M.sub.S, M.sub.1 and M.sub.2 are shown as FETs, for example MOSFETS, with M.sub.S and M.sub.2 being NMOS (n-channel) devices and M.sub.1 being a PMOS (p-channel) device. Thus, M.sub.1 connects node A to the gate node G′ of M.sub.S when CLK is low and turns ON the sampling switch M.sub.S (as explained below), while M.sub.2 connects node C to the gate node G′ of M.sub.S and turns OFF the sampling switch M.sub.S when CLK is high.

(38) The output node is connected to the drain terminal of the sampling transistor M.sub.S. A sampling capacitor C.sub.S is connected between the output node and ground.

(39) In order better to appreciate the operation of the circuit 100, the voltages at nodes A and B will be considered in more detail.

(40) First, the voltage on node A (track-control voltage signal) will be considered. FIG. 6 shows a simplified circuit model representing the voltage on node A of the circuit 100. In FIG. 6, R.sub.eqA is the equivalent resistance seen on node A because of the switching activity of transistors M.sub.1, M.sub.2 and the gate capacitance of M.sub.S, i.e., C′.sub.G:
C′.sub.G=C.sub.gsS+C.sub.gdS+C.sub.db1+C.sub.db2  (12)

(41) At first glance, as can be seen in (12), the capacitance on node G′ (C′.sub.G) only involves the gate capacitance of M.sub.S (which is different from C.sub.G in (3)).

(42) The equivalent resistance R.sub.eqA can be represented (approximately on average) as:
R.sub.eqA˜1/(f.sub.s×C′.sub.G)  (13)
where f.sub.s is the sampling frequency (i.e., the frequency of CLK signal). The resistors R.sub.1 and R.sub.2 may advantageously be designed such that:
R.sub.eqA>>R.sub.1∥R.sub.2  (14)
where >> is the “is much larger than” sign and means in parallel.

(43) Equation (14) demonstrates an aspect of the circuit 100 in FIG. 5. It is advantageous to have the resistance values of the resistors R.sub.1 and R.sub.2 small enough to allow enough AC power flowing from the input node and DC power from the reference voltage towards the node A. The concept is schematically shown in FIG. 7, which is equivalent to FIG. 6 but indicating the AC and DC power flows.

(44) According to the circuit of FIG. 6 we have:
V.sub.A=(g.sub.1/Σg.sub.A)×V.sub.IN+(g.sub.2/Σg.sub.A)×V.sub.REF  (15)
where g.sub.1=1/R.sub.1, g.sub.2=1/R.sub.2, g.sub.eqA=1/R.sub.eqA and
Σg.sub.A=g.sub.1+g.sub.2+g.sub.eqA  (16)

(45) The voltage on node B (sample voltage signal) in FIG. 5 can be calculated in a similar equivalent circuit as shown in FIG. 8, where R.sub.eqB is the equivalent impedance seen from the switching activity of the sampling switch M.sub.S and the capacitor C.sub.S.

(46) According to FIG. 8, the voltage at node B can be estimated as:
V.sub.B=g.sub.3/(g.sub.3+Σg.sub.B)×V.sub.IN  (17)
where g.sub.3=1/R.sub.3, g.sub.4=1/R.sub.4, g.sub.eqB=1/R.sub.eqB, and
Σg.sub.B=g.sub.4+g.sub.eqB  (18)

(47) The effective gate-source voltage V.sub.GS over the sampling switch M.sub.S (i.e. V.sub.GS,MS) during the tracking mode or phase can be calculated as the difference between the voltages of nodes A and B:
V.sub.GS,MS=V.sub.A−V.sub.B=(g.sub.1/Σg.sub.A−g.sub.3/(g.sub.3+Σg.sub.B))×V.sub.IN+(g.sub.2/Σg.sub.A)×V.sub.REF  (19)

(48) With the same concept as the bootstrapped switch, i.e. in order to have a linear sampling switch M.sub.S, the first term in (19) (i.e., the input-signal-dependant term) should be designed to be at least approximately equal to zero:
g.sub.1/Σg.sub.A−g.sub.3/(g.sub.3+Σg.sub.B)=0  (20)

(49) In this case, the gate source voltage in (19) is reduced (at least, approximately) to:
V.sub.GS,MS=(g.sub.2/Σg.sub.A)×V.sub.REF  (21)

(50) This gate-source voltage is constant and independent of the input signal V.sub.IN.

(51) It should be noted that in connection with FIGS. 5 to 8 it is assumed that the input signal V.sub.IN is assumed to be DC-connected at the input node, so that it applies both DC and AC components. Thus, for example, equation (17) implicitly includes a DC component term given that it includes V.sub.IN. It would however be possible to AC connect the input signal V.sub.IN at the input node (i.e. via a decoupling capacitor).

(52) The circuit 100 of FIG. 5 also has advantages from the point of view of input impedance matching.

(53) In particular, the potential divider circuit 100, implemented as a resistive network or resistor circuit as explained earlier, offers an equivalent input impedance which can be utilized for the sake of impedance matching in high-speed applications. Reference is made to FIG. 9, which is a schematic diagram showing a simplified circuit model representing the circuit 100 with a focus on the potential divider circuit 110.

(54) The equivalent input impedance Z.sub.IN as seen at the input node may be calculated as:
Z.sub.IN=(R.sub.1+R.sub.2∥R.sub.eqA)∥(R.sub.3+R.sub.4∥R.sub.eqB)  (22)

(55) As the input frequency (f.sub.in) increases, i.e. looking at frequencies of the input signal V.sub.IN, the parasitic capacitance on node B (which is mainly due to the drain-bulk capacitance of the sampling switch, M.sub.S) kicks in or becomes dominant and reduces the effective impedance seen from node B.

(56) Reference is made to FIG. 10, which is a schematic diagram similar to FIG. 9 but showing the parasitic capacitance C.sub.p1 at node B explicitly. Taking account of the parasitic capacitance C.sub.p1 at higher input frequencies, the equivalent input impedance Z.sub.IN as seen at the input node, may be calculated as:
Z.sub.IN=(R.sub.1+R.sub.2∥R.sub.eqA)∥(R.sub.3+R.sub.4∥R.sub.eqB∥(½×π×f.sub.in×C.sub.p1))  (23)

(57) In order to consider reflections in an example design scenario, without losing any generality, it will be assumed in an example application that the resistance designed for the clocking branch (i.e., R.sub.1+R.sub.2∥R.sub.eqA) is higher than the resistance seen from the signal path:
(R.sub.1+R.sub.2∥R.sub.eqA)>>[R.sub.3+R.sub.4∥R.sub.eqB∥(½×π×f.sub.in×C.sub.p1)]  (24)
This means that
Z.sub.IN˜R.sub.3+R.sub.4∥R.sub.eqB∥(½×π×f.sub.in×C.sub.p1))  (25)

(58) At low input frequency, the input impedance in (25) is reduced to:
Z.sub.IN,L˜R.sub.3+R.sub.4∥R.sub.eqB  (26)

(59) And at high input frequency:
Z.sub.IN,H˜R.sub.3  (27)

(60) At low input frequency, the input impedance in (26) is designed in the example application to be equal to the characteristic impedance, Z.sub.0 (e.g., 50 ohms):
Z.sub.IN,L˜R.sub.3+R.sub.4∥R.sub.eqB=Z.sub.0  (28)

(61) In this case, at high input frequencies, the reflection measure/coefficient or S-parameter S.sub.11 can be calculated as:
S.sub.11=20×log.sub.10(|Z.sub.IN,H−Z.sub.0|/(Z.sub.IN,H+Z.sub.0))  (29)

(62) Substituting (27) and (28) into (29) results in:
S.sub.11=20×log.sub.10((R.sub.4∥R.sub.eqB)/(2R.sub.3+R.sub.4∥R.sub.eqB))  (30)

(63) An interesting aspect of the voltage division between R.sub.3 and R.sub.4 relates to the reflection coefficient (i.e., S.sub.11) in (30). If R.sub.4 is much larger than R.sub.3, then most of the input power (V.sub.IN) will pass through the sampling switch M.sub.S, but this degrades the S.sub.11. On the other hand, losing a fraction of the input power can help to boost S.sub.11 according to (30). For example, in 5G applications, where the input signal coming from a LNA (low-noise amplifier) might be prone to a very large blocker (a high power signal in the same frequency range), this voltage division can actually help increase the linear range of an ADC (comprising the circuit 100 at its front end) along with improvement in S.sub.11 at the same time.

(64) The S.sub.11 calculated in (30) was with an assumption made in (24). Thus, the S.sub.11 depends on the design and how power flow from the input node towards the clocking path and the sampling switch (i.e., the signal path) is controlled. This concept is schematically shown in FIG. 11, which is equivalent to FIG. 5 but indicating the respective power flows. Different design scenarios entail different output signal swing, S.sub.11, clocking accuracy (and eventually effective number of bits (ENOB), spurious free dynamic range (SFDR) in an ADC implementation) etc.

(65) The speed of the circuit 100 will now be considered, compared with the bootstrapped circuit 10 of FIG. 2. In the circuit 100, the main capacitor in the clocking path is the gate capacitance of the sampling switch M.sub.S (i.e., C′.sub.G in (12)). On the other hand, in the bootstrapped circuit 10, as mentioned before, the capacitor C.sub.B is in the clocking path which is normally much larger than C′.sub.G.

(66) During the tracking mode/phase, M.sub.1 in FIG. 5 is ON. In this case, the equivalent resistance seen from the capacitance C′.sub.G can be calculated according the equivalent circuit of FIG. 12. According to this circuit, the equivalent time constant can be calculated as follows:
τ.sub.track,2=(R.sub.on,M1+R.sub.1∥R.sub.2)×C′.sub.G  (31)

(67) Similarly, in the holding phase (there is no precharge phase), the equivalent RC time constant can be calculated according to FIG. 13.
τ.sub.hold,2=R.sub.on,M2×C′.sub.G  (32)
Similar to (10), the maximum sampling frequency can be calculated as:
ω.sub.s,max,2=2π×f.sub.s,max,2=1/(τ.sub.hold,2+τ.sub.track,2)  (33)

(68) Substituting (31) and (32) in (33) results in:
ω.sub.s,max,2=2π×f.sub.s,max,2=1/[(R.sub.on,M1+R.sub.on,M2+R.sub.1∥R.sub.2)×C′.sub.G]  (34)

(69) In order to compare the speed of the two structures, (34) divided by (11) gives:
f.sub.s,max,2/f.sub.s,max−[(R.sub.on,M1+R.sub.on,M3)×C.sub.B]/[(R.sub.on,M1+R.sub.on,M2+R.sub.1∥R.sub.2)×C′.sub.G]  (35)

(70) According to FIGS. 7 and 11, the resistors R.sub.1 and R.sub.2 are advantageously designed small enough to allow enough AC power split from the input node and flowing towards the switching path. This means that R.sub.1∥R.sub.2 would be small and in the same order of the on-resistance of the devices (transistors). For simplicity, as an example rule of thumb (without losing any generality), assume R.sub.1∥R.sub.2˜R.sub.on. This means that (35) is reduced to:
f.sub.s,max,2/f.sub.s,max˜[2R.sub.on×C.sub.B]/[3R.sub.on×C′.sub.G]=C.sub.B/(3C′.sub.G)  (36)
where the on-resistance of all devices are also assumed equal to R.sub.on. As explained before, C.sub.B would be designed several times larger than C.sub.G. On the other hand, C′.sub.G is even smaller than C.sub.G (comparing (12) with (3)). Thus, the maximum sampling frequency of circuit 100 is much higher than of the bootstrapped circuit 10 according to (36).

(71) It is desirable to have a well-defined common mode voltage for the input signal passing through the sampling switch M.sub.S. In FIG. 5, this is generated with the first reference signal V.sub.REF (DC reference voltage), the second reference signal (ground) and a DC current passing through the resistors R.sub.1 to R.sub.4 of the potential divider circuit 110. In this case, the common mode voltage can be calculated as:
V.sub.IN,CM˜[(R.sub.4∥R.sub.eqB)/(R.sub.2∥R.sub.eqA+R.sub.1+R.sub.3+R.sub.4∥R.sub.eqB)]×V.sub.REF  (37)

(72) In another circuit arrangement 100A as shown schematically in FIG. 14, being a variation of circuit 100 of FIG. 5, it is possible to generate the common mode voltage with a reference voltage V.sub.IN,CM applied as the second reference signal as shown, and with a decoupling capacitor C.sub.1 placed in series with the resistor R.sub.1 also as shown. This can result in a better definition of the common mode voltage but with the cost of adding the decoupling capacitor C.sub.1.

(73) In another circuit arrangement 100B as shown schematically in FIG. 15, as an alternative to circuit arrangement 100A and being a variation of circuit 100 of FIG. 5, a resistor R.sub.0 may be added to the structure of the circuit 100 of FIG. 5 as shown in FIG. 15 in series with the resistor R.sub.4 (between R.sub.4 and ground) in order to add another degree of freedom in the designing of the common mode voltage. In the arrangement 100B, this resistor R.sub.0 is shunted out with a relatively large capacitor C.sub.0, such that in the equivalent AC model, the circuit 100 in FIG. 5 is obtained. That is, at high frequencies (of the input signal) the capacitor C.sub.0 dominates and effectively the resistor R.sub.0 is bypassed.

(74) FIG. 16 is a schematic diagram of another circuit arrangement 100C, configured to comprise multiple channels arranged for time-interleaved operation. It will be appreciated that such a configuration may be useful as the front-end of a time-interleaved ADC.

(75) For simplicity, the circuit 100 of FIG. 5 has been used as the basis of arrangement 100C, with the input node, nodes A and B, the first and second reference signal nodes and the potential divider circuit 110 being common to (i.e. shared between) the different channels.

(76) Each channel then has its own transistors M.sub.1, M.sub.2 and M.sub.S connected together as in FIG. 5 and controlled by its own clock signal CLK, those components then connected to nodes A and B as in FIG. 5 with the channels effectively connected in parallel as shown, with each having its own output node with a corresponding sampling capacitor C.sub.S. The elements in each channel have been labelled accordingly to identify which of n channels they are in. For example, CLK.sub.1 is the clock signal for channel 1 and CLK.sub.n is the clock signal for channel n. Similarly, M.sub.S,1 belongs to channel 1 whereas M.sub.S,n belongs to channel n.

(77) It will be appreciated that if the clock signals CLK.sub.1 to CLK.sub.n are a set of time-interleaved clock signals then the channels 1 to n will sample the input signal V.sub.IN in a time-interleaved fashion. That is, multiple sampling switches (M.sub.S,1, M.sub.S,2, . . . , M.sub.S,n) are driven with n clocking circuits (switching circuits 120) which are driven with n sampling clocks (CLK.sub.1, CLK.sub.2, . . . CLK.sub.n). As can be seen, the four-transistor per-channel circuit repeats itself with the number of channels and all are powered by node A.

(78) Of course, although the circuit 100 of FIG. 5 has been used as the basis of arrangement 100C, it will be appreciated that any of the other single-channel arrangements disclosed herein (e.g. 100A or 100B described above, or 100D, 100E or 100F, described below) could be used as the basis of a multi-channel arrangement in a similar fashion.

(79) In order to utilize the maximum power of the sampling switch M.sub.S (in other words, having the minimum on-resistance), the gate-source voltage in (21) is preferably designed to be equal to the core supply voltage (i.e., V.sub.DD):
V.sub.GS,MS=(g.sub.2/Σg.sub.A)×V.sub.REF=V.sub.DD  (38)

(80) This means that the reference voltage, V.sub.REF, should preferably be designed such that:
V.sub.REF=Σg.sub.A×V.sub.DD/g.sub.2  (39)

(81) Substituting (38) in (15) results:
V.sub.A=(g.sub.1/Σg.sub.A)×V.sub.IN+V.sub.DD  (40)

(82) This means that the voltage on node A would go beyond the core supply voltage. In this case, the devices M.sub.1 and M.sub.2 in FIG. 5 would experience drain-source and gate-source voltages beyond V.sub.DD which could over-stress the transistors and shorten their life time.

(83) FIG. 17 is a schematic diagram of another circuit arrangement 100D, being a variation of circuit 100 of FIG. 5, configured to resolve this over-stress issue. Transistor M.sub.3 is added to protect M.sub.2 when CLK is low. This guarantees that the drain voltage of M.sub.2 remains below V.sub.DD when it is OFF. Similarly, transistors M.sub.p4, and M.sub.n4 are added to the circuit in order to protect transistors M.sub.p1, M.sub.n1 when CLK is high. The gates of M.sub.p4, and M.sub.n4 are biased with suitable common mode voltages, V.sub.CM3,4. Also, DC voltages V.sub.CM1,2 are added to the sampling clocks (i.e., CLK, and −CLK) through resistors R.sub.5 and decoupling capacitors C.sub.1. It should be noted that these capacitors are added simply to AC couple the clock signal to the gate of transmission gate M.sub.p1,n1, and, contrary to the bootstrap circuit 10 of FIG. 2, they are not switched on/off in the circuit. All the above mentioned voltages, V.sub.CM1-V.sub.CM4, are DC voltages in this example and may be generated from the reference voltage, V.sub.REF (e.g. by potential dividers).

(84) The circuit 100D in FIG. 17 can also be used in a time-interleaved structure equivalent to that shown in FIG. 16 as mentioned earlier.

(85) It is noted that the transmission gates in FIG. 17 (i.e., transistors M.sub.p1,n1 and M.sub.p4,n4) have fairly constant on-resistances when the CLK is low. In this case, the circuit can be simplified.

(86) FIG. 18 is a schematic diagram of another circuit arrangement 100E, being a variation of circuit 100 of FIG. 5, configured as a simplified version of circuit arrangement 100D.

(87) In the circuit 100E of FIG. 18, the gate of transistor M.sub.4 is connected to node B. In this case, when CLK is low, the gate-source voltage over this device is constant similar to the sampling switch, M.sub.S. This removes the need for a transmission gate (M.sub.p4, and M.sub.n4 as in FIG. 17) and also the DC voltages, V.sub.CM3,4.

(88) The circuit 100E in FIG. 18 can also be used in a time-interleaved structure equivalent to that shown in FIG. 16 as mentioned earlier.

(89) At high input frequencies, the amount of the input signal power passing through the sampling switch (through node B in FIG. 18) and also the clocking path (through node A) decreases. This limits the bandwidth of the sampling circuit 100E and eventually of an ADC comprising it.

(90) FIG. 19 is a schematic diagram of another circuit arrangement 100F, being a variation of circuit 100D of FIG. 17, configured in order to compensate for this bandwidth limitation. Two capacitors (C.sub.2, and C.sub.3) have been added to the circuit structure of FIG. 17 (similarly, they could be added to the circuit structure of e.g. FIG. 5 or 18) as shown. C.sub.2 is in parallel with R.sub.1 and C.sub.3 is in parallel with R.sub.3. Inductor L.sub.1 has also been added to the circuit structure, in series with R.sub.2, to increase the impedance seen from the reference branch (i.e., resistor R.sub.2 connected to V.sub.REF) and help capacitor C.sub.2 to increase the signal level on node A.

(91) In this case, the voltage on node A (in s-domain) can be calculated by modifying (15) as follows:
V.sub.A=V.sub.IN×(g.sub.1+sC.sub.2)×(R.sub.2+sL.sub.1)/[1+(g.sub.eqA+g.sub.1+sC.sub.2)×(R.sub.2+sL.sub.1)]+V.sub.REF/[1+(g.sub.eqA+g.sub.1+sC.sub.2)×(R.sub.2+sL.sub.1)]  (41)

(92) On the other hand, the voltage on node B (in s-domain) in FIG. 19 can be calculated by modifying (17) as follows:
V.sub.B=(g.sub.3+sC.sub.3)/(g.sub.3+Σg.sub.B+sC.sub.3)×V.sub.IN  (42)
where Σg.sub.B is defined in (18).

(93) At high input frequencies, i.e., s=∞, equations (41) and (42) are reduced to:
V.sub.A˜V.sub.B˜V.sub.IN  (43)

(94) Comparing the high frequency values of V.sub.B in (43) with (17) suggests that the amount of high frequency “boost” in the signal comparing to its low frequency values can be calculated by dividing (43) by (17):
G=(g.sub.3+Σ.sub.gB)/g.sub.3=1+Σg.sub.B/g.sub.3  (44)

(95) This amount of gain acts as an equalizer that can enhance the bandwidth of the sampler circuit 100F in FIG. 19 and consequently an ADC comprising it.

(96) Of course, C.sub.2, C.sub.3 and L.sub.1 could be employed in a similar fashion in any of circuits 100 and 100A to 100E (or 100G described below).

(97) Depending on the application and the required specifications of the sampling switch circuit in a practical implementation, the reference voltage, V.sub.REF, may need to be designed with a value higher than the core supply voltage (i.e., V.sub.DD), (see equation (39)). IO supply voltages may for example be available any may be used as the reference voltage to generate the constant gate-source voltage over the sampling switch M.sub.S close to V.sub.DD. As another option, the reference voltage could be generated using e.g., a boost DC to DC converter.

(98) FIG. 20 is a schematic diagram representing a test bench used to compare operation of the circuit 100E (FIG. 18) with the circuit 10 (FIG. 2). The “clocking scheme” was thus set up in the tests to simulate the operation of circuits 100E and 10, in a 7 nm FinFet CMOS technology. The on-resistance of the sampling switch M.sub.S was measured and compared between the two “clocking methods” (i.e. circuits 10 and 100E). In the results shown in FIGS. 21 and 22, those that relate to circuit 10 are labelled “conventional” and those that relate to circuit 100E are labelled “proposed”.

(99) FIG. 21 is a graph shows the amount of on-resistance variation (due to the input voltage swing) for the two clocking methods (i.e. circuits 10 and 100E) with respect to the sampling clock frequency. As shown in FIG. 20, the clock frequency is f.sub.s and the duty cycle is 0.25. This means that the tracking time is 0.25/f.sub.s. In a four-phase sampler front-end structure (shown later in FIG. 23) this corresponds to a sampling frequency of 4×f.sub.s. As can be seen in FIG. 21, the performance for circuit 10 very quickly saturates and reaches a relatively large Ron variation with respect to the sampling frequency. On the other hand, the performance for circuit 100 keeps a reasonable performance up to very high sampling frequencies.

(100) It is worth mentioning that the variation shown in FIG. 21 is with respect to the input voltage for different sampling frequencies. Larger variations results in higher harmonic distortion and eventually lower effective number of bits (ENOB), spurious free dynamic range (SFDR) and in total a reduced dynamic performance of an ADC comprising the circuit concerned.

(101) FIG. 22 is a graph showing the effective bandwidth (EBW) of the sampling switch M.sub.S (with respect to the sampling frequency f.sub.s defined in FIG. 20) defined as follows:
EBW=(½π)×1/(R.sub.on,ave×C.sub.S)  (45)
where R.sub.on,ave is the average on-resistance (with respect to the input signal amplitude) and C.sub.S is the sampling capacitor.

(102) As can be seen in the results of FIG. 22, the proposed switching approach (FIG. 18) shows a much better effective bandwidth comparing to the technique of FIG. 2. It is worth mentioning that depending on the required resolution (and ENOB), the effective bandwidth (which represents the RC time constant of the switch M.sub.S) should be several times higher than the sampling clock frequency. In the conventional curve case (i.e., the bootstrapped technique of FIG. 2), the ratio of the effective bandwidth over the sampling frequency (i.e., EBW/f.sub.s) drops below unity for sampling frequencies higher than around 14 GHz while the proposed approach of FIG. 18 keeps the ratio of more than 2 up to more than 30 GHz of sampling frequency.

(103) FIG. 23 is a schematic diagram of another circuit arrangement 100G, equivalent to that of FIG. 16 but based on the circuit of FIG. 18 rather than of FIG. 5, used for further simulation. The circuit 100G is a four-phase configuration of that of FIG. 18 (e.g. for use as a time-interleaved sampler front-end structure), where <3:0> indicates an array of four components connected in parallel channel sub-circuits. As in FIG. 16, the input node, nodes A and B, the first and second reference signal nodes and the potential divider circuit 110 are common to (i.e. shared between) the different channels.

(104) In FIG. 23, CLK<3:0> and CLKN<3:0> are four-phase clocks with duty cycle of 0.25 for CLKN<3:0> and 0.75 for CLK<3:0>. The clock signals CLKN<3:0> are shown in FIG. 24 (CLK<3:0> are the same but inverted). In this case, V.sub.DD=0.9 V, and each clock has a frequency of f.sub.s/4 where f.sub.s is the sampling frequency. In this example simulation, the circuit was designed for f.sub.s=100 GSa/s or 100 GHz (i.e., each clock phase is 25 GHz). Also, the output voltage swing was set to be 0.5 Vpeak-peak differential. The circuit in FIG. 23 was simulated in a fully differential structure (although depicted in single-ended form in FIG. 23).

(105) FIGS. 25 to 27 show the waveforms respectively on nodes A (FIG. 25) and G (FIG. 26) for both positive and negative rail circuits, and the output V.sub.OUT for all four phases (FIG. 27). The circuit was designed (as an example) for a 50 ohms characteristic impedance. Also, the input frequency was set to be around 1 GHz.

(106) The four phase output signals in FIG. 27 were recombined to a single signal and its FFT spectrum was calculated and is shown in FIG. 28. In this example simulation, an ENOB of around 10 bits was found which shows the effectiveness of the proposed technique (FIG. 18) at a high sampling frequency.

(107) In summary, the embodiments disclosed herein enable, removal of the bulky capacitor C.sub.B from the switching path to speed up the clocking (in other words, by removing the precharge phase), removal of the intrinsic delay and controlling all the switches by the clock signals in order to speed up the clocking, providing the power of the clocking path by splitting the power between the clocking path and the input signal path, and introducing equalization and enhancing the bandwidth of the circuit by boosting the input signal (power flowing through the clocking path and the signal path) at high input frequencies.

(108) It is advantageous to remove the precharge phase. The voltage V.sub.IN+V.sub.DD is constantly available (i.e. maintained at node A) which is used during the tracking phase. The number of transistors is significantly reduced (e.g. compare FIG. 5 to FIG. 2) to create reduced parasitic capacitance. Also, the clocking circuitry just deals with one gate capacitance which belongs to the sampling switch M.sub.S. Further, the states of all devices are controlled with the clock directly and the intrinsic delay of FIG. 2 is removed from the structure.

(109) As mentioned above, a sampling switch circuit embodying the present invention may be implemented as part of an ADC, for example as its front-end to generate voltage mode samples V.sub.OUT of a input signal V.sub.IN, at a sample rate defined by a clock signal CLK as described earlier. FIG. 29 is a schematic diagram of such an ADC 1000 embodying the present invention. The ADC 1000 comprises any of the sampling switch circuits 100 and 100A to 100G disclosed herein, indicated as 100 in FIG. 29 for simplicity. The ADC 1000 may in turn output a digital signal, as shown, based on the voltage mode samples V.sub.OUT.

(110) Any of the circuitry disclosed herein may be implemented as integrated circuitry or as an integrated circuit, for example as (or as part of) and IC chip, such as a flip chip. FIG. 30 is a schematic diagram of integrated circuitry 2000 embodying the present invention. The integrated circuitry 2000 may comprise the ADC 1000 and/or any of the sampling switch circuits 100 and 100A to 100G disclosed herein, indicated as 100 in FIG. 30 for simplicity

(111) Integrated circuitry 2000 may be representative of some or all of an IC chip. The present invention extends to integrated circuitry and IC chips as mentioned above, circuit boards comprising such IC chips, and communication networks (for example, internet fiber-optic networks and wireless networks) and network equipment of such networks, comprising such circuit boards.

(112) The present invention may be embodied in many different ways in the light of the above disclosure, within the spirit and scope of the appended claims.