METHOD FOR PRODUCING AN ELECTRO-OPTICAL PHASE SHIFTER BASED ON FERROELECTRIC MATERIALS

Abstract

The present invention relates to producing an electro-optical phase shifter such that it may be integrated into a front-end of line of an electronic-photonic integrated circuit. A conducting bottom layer with a first refractive index is provided. A center layer including a ferroelectric material and with a second refractive index is provided on top of a first region of the conducting bottom layer, such that the center layer is not on top of a second region of the conducting bottom layer. A conducting top layer with a third refractive index is provided on top of the center layer. The second refractive index is lower than the first refractive index and lower than the third refractive index, such that the conducting bottom layer, the center layer, and the conducting top layer form a slot waveguide. A first electrical connector which connects the second region of the conducting bottom layer with an upper layer is provided. Additionally, a second electrical connector which connects the conducting top layer with the upper layer is provided. A first electrode and a second electrode are provided in the upper layer such that the first electrode connects to the second region of the conducting bottom layer via the first electrical connector and the second electrode connects to the conducting top layer via the second electrical connector.

Claims

1. A method for producing an electro-optical phase shifter, comprising the steps: providing a conducting bottom layer with a first refractive index, providing a center layer including a ferroelectric material and with a second refractive index on top of a first region of the conducting bottom layer, such that the center layer is not on top of a second region of the conducting bottom layer, and providing a conducting top layer with a third refractive index on top of the center layer, wherein the second refractive index is lower than the first refractive index and lower than the third refractive index, such that the conducting bottom layer, the center layer, and the conducting top layer form a slot waveguide, and providing a first electrical connector which connects the second region of the conducting bottom layer with an upper layer and a second electrical connector which connects the conducting top layer with the upper layer, and providing a first electrode and a second electrode in the upper layer such that the first electrode connects to the second region (106; 206) of the conducting bottom layer via the first electrical connector and the second electrode connects to the conducting top layer via the second electrical connector.

2. The method according to claim 1, wherein the first electrode and the second electrode are provided in the upper layer such that they are arranged laterally to each other.

3. The method according to claim 2, wherein the center layer is provided such that it includes a template material arranged between the conducting bottom layer and the ferroelectric material, and wherein the template material is selected such that a lattice mismatch between the conducting bottom layer and the ferroelectric material is mitigated.

4. The method according to claim 3, wherein the template material is arranged between the conducting bottom layer and the ferroelectric material by: a cycling annealing approach with a template material thickness smaller than 23 nm, or a reverse grating buffer approach with a template material thickness smaller than 23 nm, or a cycling annealing approach with a template material thickness larger than 50 nm followed by back etching the template material to a thickness smaller than 23 nm.

5. The method according to claim 1, wherein the conducting top layer, the conducting bottom layer, or both are doped or provided as in-situ doped layers.

6. The method according to claim 5, wherein at least one of the conducting top layer and the conducting bottom layer is doped, such that it includes a third region arranged on top or respectively below the center layer, and wherein the third region is doped such that it has a higher doping concentration than another region surrounding the third region.

7. The method according to claim 1, wherein the conducting top layer is provided such that it includes a first region which is arranged on top of the center layer and a second region which is not arranged on top of the center layer.

8. The method according to claim 7, wherein the conducting top layer (179) is doped such that the first region of the conducting top layer has a first doping concentration, the second region of the conducting top layer has a second doping concentration, and the second doping concentration is higher than the first doping concentration, wherein the conducting bottom layer is doped such that the first region of the conducting bottom layer has a first doping concentration, the second region of the conducting bottom layer has a second doping concentration, and the second doping concentration is higher than the first doping concentration, wherein the conducting top layer and the conducting bottom layer are doped such that the first regions of the conducting top layer and the conducting bottom layer have first doping concentrations, the second regions of the conducting top layer and the conducting bottom layer have second doping concentrations, and the second doping concentrations are higher than the first doping concentrations.

9. The method according to claim 1, wherein the conducting bottom layer is structured into a rib waveguide.

10. The method according to claim 1, wherein the conducting bottom layer is provided such that it includes a silicon-on-insulator layer.

11. The method according to claim 1, wherein the ferroelectric material is provided such that it includes barium titanate.

12. The method according to claim 1, wherein at least a region of the conducting top layer which is connected to the second electrode via the second electrical connector is at a same vertical level as the second region of the conducting bottom layer.

13. An electro-optical phase shifter comprising: a conducting bottom layer with a first refractive index, a center layer including a ferroelectric material and with a second refractive index which is arranged on top of a first region of the conducting bottom layer and which is not arranged on top of a second region of the conducting bottom layer, a conducting top layer with a third refractive index which is arranged on top of the center layer, a first electrode and a second electrode arranged in an upper layer, and a first electrical connector which connects the second region of the conducting bottom layer with the first electrode and a second electrical connector which connects the conducting top layer with the second electrode, wherein the second refractive index is lower than the first refractive index and lower than the third refractive index, and wherein the conducting bottom layer, the center layer, and the conducting top layer form a slot waveguide.

14. An electronic-photonic integrated circuit comprising the electro-optical phase shifter according to claim 13.

15. An electronic-photonic integrated circuit according to claim 14, wherein the electro-optical phase shifter is integrated in a front end of line of the electronic-photonic integrated circuit.

16. The method according to claim 1, wherein the center layer is provided such that it includes a template material arranged between the conducting bottom layer and the ferroelectric material, and wherein the template material is selected such that a lattice mismatch between the conducting bottom layer and the ferroelectric material is mitigated.

17. The method according to claim 16, wherein the template material is arranged between the conducting bottom layer and the ferroelectric material by: a cycling annealing approach with a template material thickness smaller than 23 nm, or a reverse grating buffer approach with a template material thickness smaller than 23 nm, or a cycling annealing approach with a template material thickness larger than 50 nm followed by back etching the template material to a thickness smaller than 23 nm.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0096] FIG. 1 shows a first embodiment of an EO phase shifter;

[0097] FIG. 2 shows an embodiment of a method for producing a second embodiment of the EO phase shifter;

[0098] FIGS. 3 to 34 show intermediate processing steps for producing the second embodiment of the EO phase shifter;

[0099] FIG. 35 shows the second embodiment of the EO phase shifter;

[0100] FIG. 36 shows an embodiment of an EPIC including the first embodiment of the EO phase shifter in its FEOL;

[0101] FIG. 37A shows a first alternative process for growing a Si.sub.1-xGe.sub.x layer on a carrier layer;

[0102] FIG. 37B shows a second alternative process for growing a Si.sub.1-xGe.sub.x layer on a carrier layer;

[0103] FIG. 37C shows a third alternative process for growing a Si.sub.1-xGe.sub.x layer on a carrier layer;

[0104] FIG. 38 shows a detail of a third embodiment of the EO phase shifter;

[0105] FIG. 39 shows a detail of a fourth embodiment of the EO phase shifter.

DETAILED DESCRIPTION

[0106] FIG. 1 shows a first embodiment of an EO phase shifter 100. The EO phase shifter 100 comprises a carrier layer 101 including an Si substrate 102, a buried oxide (BOX) layer 104, and a SOI layer 105 arranged on the BOX layer 104. The SOI layer 105 is made of crystalline Si, i.e., c-Si.

[0107] In this embodiment, the SOI layer 105 includes a first region 108 and a second region 106 which are doped with different doping concentrations. The first region 108 has a first doping concentration between 10.sup.13 and 10.sup.18 atoms per cubic centimeter. The second region 106 has a second doping concentration between 10.sup.18 and 10.sup.20 atoms per cubic centimeter. The SOI layer 105 serves as a conducting bottom layer. In particular, the SOI layer 105 is a doped bottom layer. In this embodiment, the SOI layer 105 has a thickness of 220 nm.

[0108] The SOI layer 105 is formed into a rib waveguide with a vertical material stack 171 arranged above a rib part 151 of the rib waveguide, such that the vertical material stack 171 is not above the second region 106 of the SOI layer 105. The vertical material stack 171 forms a center layer of a slot waveguide. The vertical material stack 171 includes a buffer layer 110 made of Si.sub.1-xGe.sub.x. In this embodiment, the thickness of the buffer layer 110 is between a monolayer and 23 nm. In other embodiments, other template materials may be utilized for forming the buffer layer, such as SrTiO.sub.3. Additionally, the center layer includes a ferroelectric material. In this embodiment, the ferroelectric material is BaTiO.sub.3 forming a ferroelectric material layer in form of BaTiO.sub.3 layer 112. In this embodiment, the BaTiO.sub.3 layer 112 has a thickness of 50 nm, In other embodiments, the ferroelectric material layer may also have a thickness between 50 nm and 80 nm. In other embodiments, another ferroelectric material may be included in the center layer.

[0109] A conducting top layer in form of a doped amorphous Si (a-Si) layer 179 is arranged on top of the BaTiO.sub.3 layer 112, such that the vertical material stack 171 is sandwiched between the doped a-Si layer 179 and the SOI layer 105 forming a slot waveguide. The conducting top layer is a doped top layer which includes a first region 114, and a second region 116 which are doped with different doping concentrations. The first region 114 has a first doping concentration between 10.sup.13 and 10.sup.18 atoms per cubic centimeter. The second region 116 has a second doping concentration between 10.sup.18 and 10.sup.20 atoms per cubic centimeter. In this embodiment, the doped a-Si layer 179 has a thickness of 80 nm.

[0110] The second regions 106 and 116 of the SOI layer 105 and the doped a-Si layer 179, respectively, are connected to electrodes 122 and 124 arranged in an upper layer in form of metal layer 192, respectively via electrical connectors in form of electronic vias 118 and 120 made of tungsten (W). The electrodes 122 and 124 are bulk electrodes made of gold (Au). A CMOS-compatible driver voltage may be applied via the electrodes 122 and 124 to the SOI layer 105 and the doped a-Si layer 179, such that a vertical electrical field Ev may be provided between them that allows EO modulation in the ferroelectric material, i.e., in the BaTiO.sub.3 layer 112.

[0111] In this embodiment, the SOI layer 105 and the doped a-Si layer 179 have a refractive index of 3.98 for a wavelength of 590 nm. The refractive index of BaTiO.sub.3 is 2.43 for a wavelength of 590 nm. Thus, the SOI layer 105 and the doped a-Si layer 179 have a higher refractive index than the ferroelectric material arranged in the slot waveguide region such that a field confinement is achieved within the vertical material stack 171. This allows achieving an improved LEOE.

[0112] FIG. 2 shows an embodiment of a method 1000 for producing a second embodiment of a EO phase shifter 200 as shown in FIG. 35. FIGS. 3 to 35 show the processing steps for producing the second embodiment of the EO phase-shifter 200 according to the method 1000.

[0113] FIG. 3 shows step 1100 of the method 1000. In step 1100, a carrier layer is provided. The carrier layer 201 includes a SOI layer 205 arranged on a buried oxide (BOX) layer 204, which itself is arranged on a Si substrate layer 202.

[0114] FIG. 4 shows step 1200 of the method 1000. In step 1200, an oxide layer in form of an SiO.sub.2 layer 226 is deposited on the SOI layer 205. In this embodiment, the SiO.sub.2 layer 226 has a thickness of 10 nm and is made of SiO.sub.2. In other embodiments, the oxide layer may also be made of another oxide.

[0115] FIG. 5 shows steps 1300 and 1400 of the method 1000.

[0116] In step 1300, a resist mask 228 is arranged on the SiO.sub.2 layer 226. The resist mask 228 forms a window 229 for doping a first region 208 of the SOI layer 205.

[0117] In step 1400, the first region 208 of the SOI layer 205 is doped with a first dopant in order to provide the first region 208 with a first doping concentration. In this embodiment, the first doping concentration is between 10.sup.13 and 10.sup.18 atoms per cubic centimeter.

[0118] FIG. 6 shows steps 1500 and 1600 of the method 1000.

[0119] In step 1500, a further resist mask 230 is arranged on a part of the first region 208 of the SOI layer 205. The resist mask 230 forms a window 231 for further doping the first region 208 of the SOI layer 205 in order to generate a second region 206 of the SOI layer 205 with a higher doping concentration.

[0120] In step 1600, the second region 206 of the SOI layer 205 is doped with the first dopant in order to provide the second region 206 with a second doping concentration. In this embodiment, the second doping concentration is between 10.sup.18 and 10.sup.20 atoms per cubic centimeter.

[0121] FIG. 7 shows steps 1700 and 1800 of the method 1000.

[0122] In step 1700, the resist masks 228 and 230 are removed. In this embodiment, the resist masks 228 and 230 are removed by ashing.

[0123] In step 1800, a nitride layer in form of a silicon nitride (Si.sub.3N.sub.4) layer 232 is deposited on the SiO.sub.2 layer 226. In this embodiment, the Si.sub.3N.sub.4 layer 232 has a thickness of 150 nm and is made of Si.sub.3N.sub.4. In other embodiments, the nitride layer may be made of another nitride, such as cobalt nitride (Co.sub.2N or Co.sub.4N.sub.2) or any other nitride.

[0124] FIG. 8 shows steps 1900 and 2000 of the method 1000.

[0125] In step 1900, a further resist mask 234 is arranged on the Si.sub.3N.sub.4 layer 232.

[0126] In step 2000, a first trench 236 is etched into the first region 208 of the SOI layer 205 and a second trench 238 is etched into a region covering partly the first region 208 and partly the second region 206 of the SOI layer 205 in order to form a waveguide structure part 240 in form of a rib waveguide. In this embodiment, etching is performed by reactive-ion etching (RIE). In other embodiments, other dry-etching methods may be used.

[0127] FIG. 9 shows step 2100 of the method 1000. In step 2100, the resist mask 234 is removed by ashing.

[0128] FIG. 10 shows steps 2200 and 2300 of the method 1000.

[0129] In step 2200, a further resist mask 244 is arranged on the structure.

[0130] In step 2300, further etching is performed in order to produce trenches 246, 248, and 249 for defining the waveguide structure. Etching is performed down to the BOX layer 204. Etching around a part of the first region 208 allows to produce a leveling part 252 of the first region 208 of the SOI layer 205 which is not connected to rib waveguide 250. Furthermore, etching is performed such that the second region 206 of the SOI layer 205 is separated from undoped parts of the SOI layer 205. In this embodiment RIE is used for etching. In other embodiments, other dry etching techniques may be used.

[0131] FIG. 11 shows step 2400 of the method 1000. In step 2400, oxide in form of SiO.sub.2 254 is deposited on the structure in order to fill the trenches 236, 238, 246, 248, and 249. In this embodiment, the oxide is SiO.sub.2. In other embodiments, another oxide may be deposited.

[0132] FIG. 12 shows step 2500 of the method 1000. In step 2500, the SiO.sub.2 254 is partly removed to a level 256 of or slightly below an upper end of the Si.sub.3N.sub.4 layer 232. In this embodiment, chemical-mechanical polishing (CMP) selective to the Si.sub.3N.sub.4 is used for removing the SiO.sub.2 254, i.e., only SiO.sub.2 254 is removed while Si.sub.3N.sub.4 is not removed.

[0133] FIG. 13 shows step 2600 of the method 1000. In step 2600, the Si.sub.3N.sub.4 layer 232 and SiO.sub.2 layer 226 above the SOI layer 205 are removed. In this embodiment, the layers 226 and 232 are etched down to the SOI layer 205, in particular by wet etching. Wet etching may be performed using, for example, potassium hydroxide (KOH), hydrofluoric acid (HF), bor fluoride (BF.sub.6), or bor chloride (BCl.sub.3). Preferably, KOH or HF are used for wet etching.

[0134] FIG. 14 shows step 2700 of the method 1000. In step 2700, an oxide layer in form of an SiO.sub.2 layer 258 is deposited on the structure. In this embodiment, the oxide layer is made of SiO.sub.2. In other embodiments, the oxide layer may be made of any other oxide.

[0135] FIG. 15 shows steps 2800 and 2900 of the method 1000.

[0136] In step 2800, a further resist mask 260 is arranged on the SiO.sub.2 layer 258.

[0137] In step 2900, a trench 262 is etched down to the first region 208 of a rib part 251 of the rib waveguide 250. In this embodiment, wet etching is used for etching the trench 262.

[0138] FIG. 16 shows step 3000 of the method 1000. In step 3000, the resist mask 260 is removed. In this embodiment, ashing is performed for removing the resist mask 260.

[0139] FIG. 17 shows step 3100 of the method 1000. In step 3100, an Si.sub.1-xGe.sub.x region 210 is grown on the rib part 251 of the rib waveguide 250 by selective epitaxy. In other embodiment, other methods for growing the Si.sub.1-xGe.sub.x region may be used, e.g., one of the methods presented in FIG. 37A, FIG. 37B, or FIG. 37C. In yet other embodiments, a template layer made from another material, e.g., STO, may be grown on the rib part in order to reduce a lattice mismatch between the rib waveguide and a ferroelectric material layer to be deposited onto the template layer.

[0140] FIG. 18 shows steps 3200, 3300, and 3400 of the method 1000.

[0141] In step 3200, a ferroelectric material layer in form of a BaTiO.sub.3 layer 264 is deposited on the structure. In this embodiment, the ferroelectric material layer is made of BaTiO.sub.3. In other embodiments, the ferroelectric material layer may also be made of another ferroelectric material, such as LiNbO.sub.3.

[0142] In step 3300, an oxide layer in form of SiO.sub.2 layer 266 is deposited on the BaTiO.sub.3 layer 264. In this embodiment, the oxide layer is made of SiO.sub.2. In other embodiments, the oxide layer may be made of another oxide.

[0143] In step 3400, a nitride layer in form of Si.sub.3N.sub.4 layer 268 is deposited on the SiO.sub.2 layer 266. In this embodiment, the nitride layer is made of Si.sub.3N.sub.4. In other embodiments, the nitride layer may be made of another nitride, such as cobalt nitride (CoN or Co.sub.3N.sub.2).

[0144] FIG. 19 shows steps 3500 and 3600 of the method 1000.

[0145] In step 3500, a resist mask 270 is deposited on the Si.sub.3N.sub.4 layer 268.

[0146] In step 3600, etching is performed down to the SiO.sub.2 layer 258 by endpoint around the rib part 251 of the waveguide 250 for producing a vertical material stack 271 above the rib part 251 of the waveguide 250 including the BaTiO.sub.3 layer 212. In this embodiment RIE is used for etching. In other embodiments, other dry etching techniques may be used for etching. Etching is performed until an endpoint is detected. The endpoint may be detected, for example, based on a change of etching parameters, e.g., a change in partial pressure of reactants.

[0147] FIG. 20 shows steps 3700 and 3800 of the method 1000.

[0148] In step 3700, the resist mask 270 is removed from the vertical material stack 271 above the rib part 251 of the waveguide 250. In this embodiment, ashing is performed for removing the resist mask 270.

[0149] In step 3800, oxide in form of SiO.sub.2 272 is deposited over the structure. In other embodiments, another oxide may be deposited instead of SiO.sub.2.

[0150] FIG. 21 shows step 3900 of the method 1000. In step 3900, the SiO.sub.2 272 is partly removed to a level 274 of or slightly below an upper end of the Si.sub.3N.sub.4 layer 268. In this embodiment, CMP selective to the Si.sub.3N.sub.4 is used for removing the SiO.sub.2 272.

[0151] FIG. 22 shows steps 4000 and 4050 of the method 1000.

[0152] In step 4000, the Si.sub.3N.sub.4 layer 268 is removed. In this embodiment, the Si.sub.3N.sub.4 layer is removed by wet etching.

[0153] In step 4050, the remaining part of the SiO.sub.2 layer 266, i.e., the part of the SiO.sub.2 layer 266 above the BaTiO.sub.3 layer 212, is removed by wet etching.

[0154] FIG. 23 shows steps 4100 and 4200 of the method 1000.

[0155] In step 4100, a resist mask 276 is arranged on the structure. The resist mask 276 includes two trenches 277 and 278 which are arranged over the first region 208 of the SOI layer 205 which forms the leveling part 252 and over the second region 206 of the SOI layer 205. In other embodiments, the trenches 277 and 278 may be provided, e.g., by RIE down to the SiO.sub.2 layer 272 by endpoint (not shown).

[0156] In step 4200, etching is performed down to the SOI layer 205 in order to provide a first trench 277 to the first region 208 of the SOI layer 205 forming the leveling part 252 and a second trench 278 to the second region 206 of the SOI layer 205. In this embodiment, wet etching is used.

[0157] FIG. 24 shows step 4300 of the method 1000. In step 4300, the resist mask 276 is removed. In this embodiment, ashing is performed to remove the resist mask 276.

[0158] FIG. 25 shows step 4400 of the method 1000. In step 4400, a conducting top layer in form of an in-situ doped poly-Si layer 279 is deposited on the structure. In this embodiment, the conducting top layer is made of in-situ doped poly-Si. In other embodiments, the conducting top layer may be made of another conducting material, e.g., in-situ doped Si.sub.1-xGe.sub.x. The method may also include a doping step instead of depositing in-situ doped conducting material. The in-situ doped poly-Si is doped with a second dopant. In particular, if the first region 208 and second region 206 of the SOI layer 205 are n-doped, the in-situ doped poly-Si layer 279 is p-doped and vice versa. The p-doped region, i.e., the region which is p-doped, may be doped with, for example, boron atoms. The n-doped region, i.e., the region which is n-doped, may be doped with, for example, phosphorus atoms or arsenic atoms. Alternatively. other dopants may be used for doping the n-doped region and/or the p-doped region.

[0159] Since the trenches 277 and 278 extend down to the leveling part 252 and the second region 206, the in-situ doped poly-Si layer 279 is arranged on a similar level with the second region 206.

[0160] FIG. 26 shows steps 4500 and 4600 of the method 1000.

[0161] In step 4500, a resist mask 280 is arranged on the structure.

[0162] In step 4600, parts of the in-situ doped poly-Si layer 279 which are not above the leveling part 252 or the rib part 251 of the rib waveguide 250 are removed, such that in-situ doped poly-Si layer 214 is produced. In this embodiment, RIE is used for removing them. In other embodiments, any other dry etching technique may be used for removing them.

[0163] FIG. 27 shows step 4700 of the method 1000. In step 4700, oxide in form of SiO.sub.2 281 is deposited on the structure. In this embodiment, the oxide is SiO.sub.2 281. In other embodiments, any other oxide may be deposited instead.

[0164] FIG. 28 shows steps 4800 and 4900 of the method 1000.

[0165] In step 4800, a resist mask 282 is arranged on the structure.

[0166] In step 4900, parts of the resist mask 282 above the leveling part 252 and the second region 206 of the SOI layer 205 are removed. In this embodiment, RIE is used for removing them. In other embodiments, any other dry etching technique may be used for removing them. In yet other embodiments, the resist mask may be provided with corresponding trenches above the leveling part 252 and the second region 206 of the SOI layer 205.

[0167] FIG. 29 shows step 5000 of the method 1000. In step 5000, the SiO.sub.2 281 is removed using the resist mask 282, i.e., the SiO.sub.2 281 is removed at regions at which it is not below the resist mask 282. In this embodiment, wet etching is performed for removing the SiO.sub.2 281. The wet etching is performed down to in-situ doped poly Si layer 214 and the second region 206 of the SOI layer 205, e.g., by endpoint.

[0168] FIG. 30 shows step 5100 of the method 1000. In step 5100, the resist mask 282 is removed. In this embodiment, ashing is used for removing the resist mask 282.

[0169] FIG. 31 shows step 5200 of the method 1000. In step 5200, regions of the in-situ doped poly-Si layer 214 which are not covered by SiO.sub.2 281 and the second region 206 of the SOI layer 205 are doped by a silicide in form of cobalt silicide (CoSi) forming contacting layers 286 and 284. In other embodiments, the silicide used for doping may be another silicide, such as nickel silicide (NiSi).

[0170] FIG. 32 shows step 5300 of the method 1000. In step 5300, an oxide layer in form of SiO.sub.2 layer 288 is deposited on the structure and CMP is performed to bring the oxide layer to an even level 289. In this embodiment, the oxide layer is made of SiO.sub.2. In other embodiments, the oxide layer may be made of another oxide.

[0171] FIG. 33 shows step 5400 of the method 1000. In step 5400, a first part of a first connector in form of electronic vias 220 and a first part of a second connector in form of electronic vias 218 are implanted into the SiO.sub.2 layer 288 between a top surface of the SiO.sub.2 layer 288 and the contacting layers 284 and 286. In this embodiment, the electronic vias 220 and 218 are made of tungsten (W). In other embodiments, the first parts of the connectors may be made of another conducting material.

[0172] Due to the leveling part 252, the contacting layers 284 and 286 are on a similar level. This allows to contact the in-situ doped poly-Si layer 279 and the second region 206 on a similar level via the first connectors 220 to a higher lying layer.

[0173] FIG. 34 shows steps 5500 and 5600 of the method 1000.

[0174] In step 5500, a further oxide layer in form of SiO.sub.2 layer 290 is deposited on the structure. In this embodiment, the oxide layer is made of SiO.sub.2. In other embodiments, the oxide layer may also be made of another oxide.

[0175] In step 5600, a second part of the first connector in form of electronic vias 221 and a second part of the second connector in form of electronic vias 219 are implanted into the SiO.sub.2 layer 290 extending between a surface of the SiO.sub.2 layer 290 and the first parts of the electronic connectors, i.e., electronic vias 220 and 219. In this embodiment the second parts of the connectors are made of tungsten. In other embodiments, they may be made of another conducting material. Instead of providing second parts of the connectors, the first parts of the connectors may also be longer.

[0176] FIG. 35 shows step 5700 of the method 1000 which finally provides the second embodiment of the EO phase-shifter 200. In step 5700, electrodes in form of gold (Au) electrodes 222 and 224 are arranged on top of the second electronic vias 221 in an upper layer in form of metal layer 292. In this embodiment, the electrodes are metal electrodes made of Au. In other embodiments, the electrodes may also be made of another conducting material, in particular a metal.

[0177] The EO phase-shifter 200 comprises a conducting bottom layer in form of the SOI layer 205, a center layer in form of the vertical material stack 271, a conducting top layer in form of the doped poly-Si layer 214, first electrode 222, second electrode 224, first electrical connector in form of electronic vias 220 and 221, and second electrical connector in form of electronic vias 218 and 219.

[0178] The SOI layer 205 has a first refractive index of 3.98 at a wavelength of 598 nm. The doped poly-Si layer 214 has a third refractive index, which is identical to the first refractive index in this case as both are made of Si. The vertical material stack 271 includes a ferroelectric material in form of BaTiO.sub.3 and a template material in form of Si.sub.1-xGe.sub.x region 210. The vertical material stack 271 has a second refractive index. The refractive index of BaTiO.sub.3 is 2.43 at a wavelength of 598 nm. In this embodiment, the Si.sub.1-xGe.sub.x has x=0.89 such that its refractive index is 5.40 at a wavelength of 598 nm. The thickness of the template material, i.e., below 23 nm and the ferroelectric material, i.e., between 50 nm and 80 nm, are chosen such that the second refractive index is lower than the first refractive index and lower than the third refractive index. The SOI layer 205, the vertical material stack 271, and the doped poly-Si layer 214 thus form a slot waveguide.

[0179] The vertical material stack 271 is arranged on top of the first region 208 of the SOI layer 205, in particular, above the rib of the rib waveguide 250. The vertical material stack 271 is thus not arranged on top of the second region 206 of the SOI layer 205. The doped poly-Si layer 214 is arranged on top of the vertical material stack 271.

[0180] The first electrode 222 and the second electrode 224 are arranged in an upper layer in form of the metal layer 292, such that the metal layer 292 is arranged above the SOI layer 205 and above the doped poly-Si layer 214. The first electronic vias 220 and 221 connect the second region 206 of the SOI layer 205 with the first electrode 222 and the second electronic vias 218 and 219 connect the doped poly-Si layer 214 with the second electrode 224.

[0181] The EO phase shifter 200 may be connected to a power source, in particular, the electrodes 222 and 224 may be connected to a power source. The power source may also be included in the EO phase shifter (not shown). A CMOS compatible driver voltage, e.g., 2 V, may be applied to the electrodes 222 and 224 for generating a vertical electric field between the doped poly-Si layer 214 and the first region 208 of the SOI layer 205 through the vertical material stack 271 in order to induce the LEOE in the BaTiO.sub.3 layer 212 such that EO modulation may be performed.

[0182] In other embodiments, the EO phase-shifter may be used as an EO modulator configured for intensity modulation, e.g., by implementing the EO phase-shifter, for example, in an interferometer, e.g., a Mach-Zehnder-interferometer, or a resonator, e.g., a Fabry-Perot-resonator or a ring resonator to form an EO modulator.

[0183] In other embodiments, at least one of the conducting top layer and the conducting bottom layer may be doped, such that it includes a third region arranged on top or respectively below the center layer. The third region may be doped such that it has a higher doping concentration than another region surrounding the third region, e.g., the first region. The third doping concentration may be, for example, between 10.sup.18 and 10.sup.20 atoms per cubic centimeter in the conducting top layer and/or in the conducting bottom layer. The third region may, for example, have the same doping concentration as the second region.

[0184] The configurations of the EO phase shifters 100 and 200 presented in FIGS. 1 and 35 allow an integration in the FEOL of an EPIC.

[0185] FIG. 36 shows a cross sectional view of an embodiment of an EPIC 300 comprising the embodiment of the phase-shifter 100. In this embodiment, the phase shifter 100 is integrated in the FEOL. Identical features are referred to using identical reference numerals for FIGS. 1 and 36. In other embodiments, the phase-shifter 200 of FIG. 35 may be integrated into the EPIC 300.

[0186] The EPIC 300 has a FEOL 350 and a BEOL 340. The FEOL 350 is fabricated with a FEOL technology. The FEOL 350 comprises a Si photonic integrated circuit (PIC) region 320 and an electronic integrated circuit (EIC) region 330. The Si PIC region 320 comprises a Ge photodiode 310, Si waveguides 312 and the EO phase shifter 100. Impinging light signals 314 may be received and transmitted light signals 316 may be transmitted from the EPIC 300. The EIC region 330 comprises a SiGe heterojunction bipolar transistor (SiGe:C HBT) 332, an n-channel metal-oxide-semiconductor (NMOS) 334 and a p-channel metal-oxide-semiconductor (PMOS) 336 which form a Bi-CMOS. The BEOL 340 comprises an interconnect stack 342 with several metal planes 344 and 346.

[0187] An integration of the EO phase shifter 100 of FIG. 1 into the EPIC 300 allows an integration in the FEOL 350. This allows reducing losses for optical coupling the FEOL with the EO phase-shifter as the EO-phase shifter is integrated in the FEOL 350 and not in the BEOL 340 as for the prior art. Furthermore, the EO phase shifter 100 may be connected to any of the metal planes, e.g., metal planes 344 and 346, above the FEOL in the BEOL.

[0188] FIG. 37A shows a cycling annealing approach for providing a Si.sub.1-xGe.sub.x layer 410 with a thickness smaller than 23 nm on a carrier layer 401. In this embodiment, the carrier layer 401 includes a Si substrate 402, a BOX layer 404, and a SOI layer 405. In other embodiments, another template material than Si.sub.1-xGe.sub.x may be used, e.g., SrTiO.sub.3.

[0189] FIG. 37B shows a reverse grating buffer approach for providing a Si.sub.1-xGe.sub.x layer 410 with a thickness smaller than 23 nm on a Ge layer 409 arranged on the carrier layer 401 shown in FIG. 37A. In other embodiments, another template material than Si.sub.1-xGe.sub.x may be used, e.g., SrTiO.sub.3.

[0190] FIG. 37C shows a cycling annealing approach for providing a Si.sub.1-xGe.sub.x layer 410 with thickness larger than 50 nm followed by back etching the Si.sub.1-xGe.sub.x layer 410 to a thickness smaller than 23 nm. In other embodiments, another template material than Si.sub.1-xGe.sub.x may be used, e.g., SrTiO.sub.3.

[0191] FIG. 38 shows a detail of a third embodiment of an EO phase shifter 500. The detail essentially includes the layers that form a slot waveguide. Only a layer stack is shown without the structure around the layer stack.

[0192] The EO phase shifter 500 comprises a carrier layer 501 including an Si substrate 502, a BOX layer 504, and a SOI layer 505 arranged on the BOX layer 504. The SOI layer 505 is made of c-Si. In this embodiment, the SOI layer 505 includes a first region 508 which is doped with a first doping concentration between 10.sup.13 and 10.sup.18 atoms per cubic centimeter. The SOI layer 505 serves as a conducting bottom layer.

[0193] A vertical material stack 571 forms a center layer of the slot waveguide. The vertical material stack 571 includes a buffer layer 510 made of Si.sub.1-xGe.sub.x. Additionally, the center layer includes a ferroelectric material. In this embodiment, the ferroelectric material is BaTiO.sub.3 forming a ferroelectric material layer in form of BaTiO.sub.3 layer 512.

[0194] A conducting top layer in form of a doped a-Si layer 579 is arranged on top of the BaTiO.sub.3 layer 512, such that the vertical material stack 571 is sandwiched between the doped a-Si layer 579 and the SOI layer 505 forming a slot waveguide. The conducting top layer is a doped top layer which includes a first region 514 which is doped with a first doping concentration between 10.sup.13 and 10.sup.18 atoms per cubic centimeter.

[0195] An insulating layer 588 is arranged on top of the doped a-Si layer 579. Electrodes are connected to the conducting top layer and the conducting bottom layer in non-shown parts of the EO phase shifter 500.

[0196] A driver voltage, e.g., CMOS-compatible driver voltage, may be applied via the electrodes to the SOI layer 505 and the doped a-Si layer 579, such that a vertical electrical field Ev may be provided between them that allows EO modulation in the ferroelectric material, i.e., in the BaTiO.sub.3 layer 512.

[0197] FIG. 39 shows a detail of a fourth embodiment of an EO phase shifter 600. The fourth embodiment of the EO phase shifter 600 is similar to the third embodiment of the EO phase shifter 500. Reference signs 5xx and 6xx regard same layers or regions, respectively.

[0198] In contrast to the EO phase shifter 500, the EO phase shifter 600 additionally includes third regions 611 with a third doping concentration between 10.sup.18 and 10.sup.20 atoms per cubic centimeter in the conducting bottom layer in form of the SOI layer 605 arranged in between first regions 608 with a first doping concentration between 10.sup.13 and 10.sup.18 atoms per cubic centimeter. The first regions 608 and the third regions 611 are doped with dopants of a same type, i.e., such that they become p-doped or n-doped regions. In this embodiment, the third regions 611 and the first regions 608 are n-doped regions. Furthermore, the EO phase shifter 600 includes third regions 615 with a third doping concentration between 10.sup.18 and 10.sup.20 atoms per cubic centimeter in the conducting top layer in form of the doped a-Si layer 679 arranged in between first regions 614 with a first doping concentration between 10.sup.13 and 10.sup.18 atoms per cubic centimeter. The first regions 614 and the third regions 615 are doped with dopants of a same type. In this embodiment, the third regions 615 and the first regions 614 are p-doped regions.

[0199] In other embodiments, the third regions and first regions may also have other doping concentrations, e.g., each of the third regions, i.e., between the conducting top layer and the conducting bottom layer as well as between different third regions in the same layer, may have a different doping concentration. Also only one of the conducting top layer and the conducting bottom layer may include one or more third regions. The third regions may, for example, have the same doping concentration as the second regions (not shown).

[0200] As for the third embodiment of the EO phase shifter 500, a driver voltage, e.g., CMOS-compatible driver voltage, may be applied via the electrodes to the SOI layer 605 and the doped a-Si layer 679, such that a vertical electrical field Ev may be provided between them that allows EO modulation in the ferroelectric material, i.e., in the BaTiO.sub.3 layer 612.

[0201] In summary, the present invention relates to producing an electro-optical phase shifter such that it may be integrated into a front-end of line of an electronic-photonic integrated circuit. A conducting bottom layer with a first refractive index is provided. A center layer including a ferroelectric material and with a second refractive index is provided on top of a first region of the conducting bottom layer, such that the center layer is not on top of a second region of the conducting bottom layer. A conducting top layer with a third refractive index is provided on top of the center layer. The second refractive index is lower than the first refractive index and lower than the third refractive index, such that the conducting bottom layer, the center layer, and the conducting top layer form a slot waveguide. A first electrical connector which connects the second region of the conducting bottom layer with an upper layer is provided. Additionally, a second electrical connector which connects the conducting top layer with the upper layer is provided. A first electrode and a second electrode are provided in the upper layer such that the first electrode connects to the second region of the conducting bottom layer via the first electrical connector and the second electrode connects to the conducting top layer via the second electrical connector. This method allows integrating the EO phase-shifter in the front-end of line of an electronic-photonic integrated circuit.