ONE DIRECTION-SHIFT REGISTER ALIASING TABLE CIRCUIT SUITABLE FOR USE IN MICROPROCESSORS

Abstract

Disclosed are hardware configurations of the Register Aliasing Table (RAT) which are suitable for use in structures such as modern microprocessor, microcontroller, CPU etc. that use pipe line technique, perform multi-command operations, prevents Write After Read (WAR), Write After Write (WAW), Read After Write(RAW) dependencies. The Register Aliasing Table provides a circuit which consumes less energy, uses less space and has low latency compared to the applications in the state of the art.

Claims

1. Register aliasing table which is suitable for use in structures such as modern microprocessor, microcontroller, CPU etc. that use pipe line technique, perform multi-command operations, prevents write after read, write after write, read after write risks, wherein the register aliasing table comprises: a pre-determined number of adjacently ordered printer drivers which are adapted to be activated during writing process, a pre-charge block ordered side by side with same number of buses connected to the printer drivers which are adapted to ensure the buses to wait in a stable manner when reading or writing is not performed, a SRAM cell block which comprises cell groups that are interconnectedly arranged with each other such that they have the same number of columns connected to the pre-charge blocks with the same number of buses and have another number of rows determined previously, a second decoder which determines the row in which the information in the cell group will be copied and is adapted for executing the commands that informs about which row will be referred for information to perform the process, has an outlet that is connected to each row of SRAM cell block, sense amplifiers which are connected to SRAM cell block in proportion with the number of columns via buses, are arranged adjacent to each other in proportion with the number of adapted columns for bringing the low output to a level that can be read, multiplexers which are connected to the sense amplifiers in proportion with the number of columns via buses, are arranged adjacent to each other in proportion with the number of adapted columns for selecting from which 7-bit SRAM cell group will the output required for reading be taken, a first decoder which determines in which cell group in the SRAM cell block, the reading and writing operations will be performed and determines which of said peripheral units arranged adjacent to each other will operate during operations.

2. Register aliasing table circuit according to claim 1, comprising 32 pieces of 7-bit cell groups, 7-bit 5×32 decoder, 32 pieces of 7-bit printer drivers, 32 pieces of 7-bit pre-charge blocks, 32 pieces of 7-bit sense amplifiers and 32 pieces of 7-bit multiplexers.

3. Register aliasing table circuit according to claim 1, comprising cells with operational amplifier for transferring the data to the cell that is one below the same when the jump command is received.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0008] Rename circuit realized for reaching the aim of this invention is illustrated in the accompanying figures, in which;

[0009] FIG. 1. Is a schematic view of the register aliasing table circuit.

[0010] FIG. 2. Is a schematic view of a cell.

[0011] The parts in the figure are enumerated one by one and the parts correspond to these numbers are given in the following.

[0012] 1. Rename circuit

[0013] 2. First decoder

[0014] 3. Printer driver

[0015] 4. Pre-charge block

[0016] 5. SRAM cell block [0017] 51. Cell

[0018] 6. Second decoder

[0019] 7. Sense amplifier

[0020] 8. Multiplexer

[0021] The inventive one direction-shift register aliasing table circuit suitable for use in microprocessors (1) mainly comprises the following elements; [0022] A pre-determined number of adjacently ordered printer driver (3) which are adapted to be activated during writing process, [0023] pre-charge block (4) ordered side by side with same number of buses connected to the printer drivers (3) which are adapted to ensure the buses to wait in a stable manner when reading or writing is not performed, [0024] SRAM cell block (5) which consists of cell (5) groups that are interconnectedly arranged with each other such that they have the same number of columns connected to the pre-charge blocks (4) with the same number of buses and have another number of rows determined previously, [0025] A second decoder (6) which determines the row in which the information in the cell (51) group will be copied and is adapted for executing the commands that informs about which row will be referred for information to perform the process, has an outlet that is connected to each row of SRAM cell block (4), [0026] The sense amplifiers (7) which are connected to SRAM cell block (5) in proportion with the number of columns via buses, are arranged adjacent to each other in proportion with the number of adapted columns for bringing the low output to a level that can be read, [0027] Multiplexers (8) which are connected to the sense amplifiers (7) in proportion with the number of columns via buses, are arranged adjacent to each other in proportion with the number of adapted columns for selecting from which 7-bit SRAM cell (5) group will the output required for reading be taken, [0028] A first decoder (2) which determines in which cell (51) group in the SRAM cell block (5), the reading and writing operations will be performed and determines which of said peripheral units arranged adjacent to each other will operate during operations.

[0029] In the inventive register aliasing table circuit (1), the first decoder (2) determines in which cell (51) group in the SRAM cell block (5), the reading and writing operations will be performed. The SRAM cell block (5) consists of cells (5) comprising transistors that store data in the circuit (1). In a preferred embodiment of the invention, 32 cells (5) with 7-bit and 5×32 decoders (2) with 7-bit are used. The decoder has 32 buses in this application. All of these buses are 7 bits.

[0030] The printer driver (3) is activated, when writing process will be carried out. The printer driver (3) is activated, when writing process will be carried out. In a preferred embodiment of the invention, 32 pieces of 7-bit printer driver (3) is used.

[0031] The pre-charge block (4) provides the voltage in the buses to be stable during the first half of each hour pulse of the microprocessor in the circuit (1) (namely when reading and writing process is not carried out). In a preferred embodiment of the invention, 32 pieces of 7-bit pre-charge blocks are used.

[0032] The sense amplifiers (7) provide to realize the reading process faster by detecting the voltage changes in the data paths in the circuit (1). In a preferred embodiment of the invention, 32 pieces of 7-bit sense amplifiers (7) are used.

[0033] The multiplexers (8) determined which groups of cells (51) will be chosen. When reading is performed, the information of the cell (51) chosen from the group in the row are printed. In a preferred embodiment of the invention, 32 pieces of 7-bit multiplexers are used.

[0034] The second decoder (6) enables the data to be transferred to the row below by the row which is in process at that time among the rows consisting of the cell (51) groups for copying the data when a jump command is received in order to perform an execution based on estimation when a conditional command according to the pipeline operation technique is received. Therefore, the data required to be copied remain on the previous row, and the reading and writing operations continue from the new row where the copy is received. In case it is required to return to the copied data, the second decoder (6) provides the performance of reading and writing operations over the data by returning back to the previous row. For example; If the second decoder (6) shows the row 0 and the copy command is received, then all data is copied to row 1 and from now on the operations will be made over row 1. If you require returning, row 0 is shown again. Therefore, only 1 bit shifting is performed in the copying process and only the row is changed in case it is required to return to the copy.

[0035] The first decoder (2) similar to determining in which cell (51) group in the SRAM cell block (5), the reading and writing operations will be performed, also determines which of the units arranged adjacently among the peripheral units (printer driver (3), pre-charge block (4), sense amplifier (7) will operate. Only the unit among the peripheral units in the relevant column operates depending on the cell groups where reading and writing processes will be performed. Therefore, power consumption can be reduced.

[0036] In the inventive circuit (1), the cells (51) comprise an operational amplifier which enables the data in the cell (51) to be transferred to the cell (51) below when a further jump command is received to a normal SRAM cell. The output (OUT) pin of each cell is connected to the (IN) pin of the cell that is below. The output of the cell on the bottom row is connected to the input pin of the cell which is on the top row. Therefore, all the cells (51) are connected to each other and form the rows and columns of the cell block (5). Therefore, hardware which allows for working in a circular structure in the inventive circuit (1) is formed. When the data in the bottom row is copied, the information copied from the upper rows can be added to anyone that is not required anymore.