METHOD AND SYSTEM FOR COMPREHENSIVELY EVALUATING RELIABILITY OF MULTI-CHIP PARALLEL IGBT MODULE

Abstract

A method and a system for comprehensively evaluating reliability of a multi-chip parallel IGBT module are provided. The method includes: establishing a gate-emitter voltage reliability model of the multi-chip parallel IGBT module, performing a chip fatigue failure test, and selecting a gate-emitter voltage as a failure characteristic quantity; establishing a transconductance reliability model of the multi-chip parallel IGBT module, performing a bonding wire shedding failure test, and selecting a transmission characteristic curve of the module as a failure characteristic quantity; using a Pearson correlation coefficient to characterize a degree of health of the IGBT module, and respectively calculating degrees of health PPMCC.sub.C and PPMCC.sub.B in different degrees of chip fatigue and bonding wire shedding failure states; and comprehensively evaluating the reliability of the multi-chip parallel IGBT module according to PPMCC.sub.C and PPMCC.sub.B.

Claims

1. A method for comprehensively evaluating reliability of a multi-chip parallel insulated gate bipolar transistor (IGBT) module, comprising: Step (1) of establishing a gate-emitter voltage reliability model of the multi-chip parallel IGBT module, implementing a chip fatigue failure test based on the gate-emitter voltage reliability model, and selecting a gate-emitter voltage as a failure characteristic quantity; Step (2) of establishing a transconductance reliability model of the multi-chip parallel IGBT module, implementing a bonding wire shedding failure test based on the transconductance reliability model, and selecting a transmission characteristic curve of the module as a failure characteristic quantity; Step (3) of defining a degree of health of the IGBT module, using a Pearson correlation coefficient to characterize the degree of health, and calculating a degree of health PPMCC.sub.C in different degrees of chip fatigue failure states and a degree of health PPMCC.sub.B in different degrees of bonding wire shedding failure states; and Step (4) of comprehensively evaluating the reliability of the multi-chip parallel IGBT module according to PPMCC.sub.C and PPMCC.sub.B.

2. The method for comprehensively evaluating the reliability of the multi-chip parallel IGBT module according to claim 1, wherein Step (3) specifically comprises: Step (3.1) of adopting the degree of health to characterize the reliability of the IGBT module, wherein when the module has no chip fatigue failure and no bonding wire shedding failure, the degree of health is maximum, when the IGBT module is in a healthy initial state without chip fatigue failure, a gate-emitter voltage eigenvector is {right arrow over (x)}, and when i chips fail in the IGBT module, a gate-emitter voltage eigenvector is {right arrow over (y)}.sub.i; and when the IGBT module is in the healthy initial state without bonding wire shedding failure, a transmission characteristic curve eigenvector of the IGBT module is {right arrow over (m)}, and when p bonding wires shed in the IGBT module, a transmission characteristic curve eigenvector of the IGBT module is n.sub.p; Step (3.2) of obtaining the linear correlation PPMCC.sub.C between the gate-emitter voltage in a chip fatigue failure state and a healthy state based on the gate-emitter voltage eigenvector {right arrow over (x)} and the gate-emitter voltage eigenvector {right arrow over (y)}.sub.i, wherein the greater the PPMCC.sub.C, the higher the correlation between the two, the higher the degree of health of chips, and the stronger the reliability; and Step (3.3) of obtaining the linear correlation PPMCC.sub.B between the transmission characteristic curve in a bonding wire shedding failure state and the healthy state based on the transmission characteristic curve eigenvector {right arrow over (m)} of the IGBT module and the transmission characteristic curve eigenvector n.sub.p of the IGBT module, wherein the greater the PPMCC.sub.B, the greater the correlation between the two, the higher the degree of health of bonding wires, and the higher the reliability of the module.

3. The method for comprehensively evaluating the reliability of the multi-chip parallel IGBT module according to claim 2, wherein the linear correlation between the gate-emitter voltage in the chip fatigue failure state and the healthy state is obtained from ${\mathrm{PPMCC}}_C=r\left(\stackrel{.fwdarw.}{x},{\stackrel{.fwdarw.}{y}}_l\right)=\frac{{.Math.}_{j=1}^h\left(x_j-\stackrel{-}{x}\right)\left(y_{\mathrm{ij}}-{\stackrel{-}{y}}_i\right)}{\sqrt{{.Math.}_{j=1}^h{\left(x_j-\stackrel{-}{x}\right)}^2\sqrt{{.Math.}_{j=1}^h{\left(y_{\mathrm{ij}}-{\stackrel{-}{y}}_i\right)}^2}}},$ where h represents a number of selected samples, x.sub.j represents an observed value of a point j corresponding to the gate-emitter voltage eigenvector {right arrow over (x)} without chip failure, x represents a mean of observed values of the eigenvector {right arrow over (x)}, y.sub.ij represents an observed value of the point j corresponding to the gate-emitter voltage eigenvector {right arrow over (y)}.sub.i when i chips fail, and y.sub.i represents a mean of observed values of the eigenvector {right arrow over (y)}.sub.i.

4. The method for comprehensively evaluating the reliability of the multi-chip parallel IGBT module according to claim 3, wherein the linear correlation between the transmission characteristic curve in the bonding wire shedding failure state and the healthy state is obtained from ${\mathrm{PPMCC}}_B=r\left(\stackrel{.fwdarw.}{m},\stackrel{.fwdarw.}{n_p}\right)=\frac{\underset{q=1}{\overset{l}{.Math.}}\left(m_q-\stackrel{\_}{m}\right)\left(n_{pq}-{\stackrel{\_}{n}}_p\right)}{\sqrt{\underset{q=1}{\overset{l}{.Math.}}{\left(m_p-\stackrel{\_}{m}\right)}^2}\sqrt{\underset{q=1}{\overset{l}{.Math.}}{\left(n_{pq}-{\stackrel{\_}{n}}_p\right)}^2}},$ where l represents a number of selected samples, m.sub.q represents an observed value of a point q corresponding to the transmission characteristic curve eigenvector {right arrow over (m)} of the module without bonding wire shedding, m represents a mean of observed values of the eigenvector {right arrow over (m)}, n.sub.pq represents an observed value of the point q corresponding to the transmission characteristic curve eigenvector {right arrow over (n)}.sub.p of the module when p bonding wires shed, and n.sub.p represents a mean of observed values of the eigenvector n.sub.p.

5. The method for comprehensively evaluating the reliability of the multi-chip parallel IGBT module according to claim 4, wherein Step (4) specifically comprises: performing a weighted summation on the linear correlation PPMCC.sub.C between the gate-emitter voltage in the chip fatigue failure state and the healthy state and the linear correlation PPMCC.sub.B between the transmission characteristic curve in the bonding wire shedding failure state and the healthy state to obtain an overall degree of health of the module, and evaluating the reliability of the multi-chip parallel IGBT module from the overall degree of health of the module, wherein the overall degree of health of the module reflects the overall degree of health of the module in terms of a chip health state of the module and a bonding wire health state of the module.

6. The method for comprehensively evaluating the reliability of the multi-chip parallel IGBT module according to claim 5, wherein the overall degree of health of the module is obtained from PPMCC.sub.H=a*PPMCC.sub.C+b*PPMCC.sub.B, where a represents a proportion of failures caused by the chip fatigue failure in the IGBT module, and b represents a proportion of failures caused by the bonding wire shedding failure in the IGBT module.

7. A system for comprehensively evaluating reliability of a multi-chip parallel IGBT module, comprising: a first failure characteristic quantity acquisition module, used to establish a gate-emitter voltage reliability model of the multi-chip parallel IGBT module, implement a chip fatigue failure test based on the gate-emitter voltage reliability model, and select a gate-emitter voltage as a failure characteristic quantity; a second failure characteristic quantity acquisition module, used to establish a transconductance reliability model of the multi-chip parallel IGBT module, implement a bonding wire shedding failure test based on the transconductance reliability model, and select a transmission characteristic curve of the module as a failure characteristic quantity; a health degree calculation module, used to define a degree of health of the IGBT module, use a Pearson correlation coefficient to characterize the degree of health, and calculate a degree of health PPMCC.sub.C in different degrees of chip fatigue failure states and a degree of health PPMCC.sub.B in different degrees of bonding wire shedding failure states; and a reliability evaluation module, used to comprehensively evaluate the reliability of the multi-chip parallel IGBT module according to PPMCC.sub.C and PPMCC.sub.B.

8. The system for comprehensively evaluating the reliability of the multi-chip parallel IGBT module according to claim 7, wherein the health degree calculation module comprises: a health parameter definition module, used to adopt the degree of health to characterize the reliability of the IGBT module, wherein when the module has no chip fatigue failure and no bonding wire shedding failure, the degree of health is maximum, when the IGBT module is in a healthy initial state without chip fatigue failure, a gate-emitter voltage eigenvector is {right arrow over (x)}, and when i chips fail in the IGBT module, a gate-emitter voltage eigenvector is {right arrow over (y)}.sub.i; and when the IGBT module is in the healthy initial state without bonding wire shedding failure, a transmission characteristic curve eigenvector of the IGBT module is {right arrow over (m)}; and when p bonding wires shed in the IGBT module, a transmission characteristic curve eigenvector of the IGBT module is n.sub.p; a chip health calculation module, used to obtain the linear correlation PPMCC.sub.C between the gate-emitter voltage in a chip fatigue failure state and a healthy state based on the gate-emitter voltage eigenvector {right arrow over (x)} and the gate-emitter voltage eigenvector {right arrow over (y)}.sub.i, wherein the greater the PPMCC.sub.C, the higher the correlation between the two, the higher the degree of health of chips, and the stronger the reliability; and a bonding wire health calculation module, used to obtain the linear correlation PPMCC.sub.B between the transmission characteristic curve in a bonding wire shedding failure state and the healthy state based on the transmission characteristic curve eigenvector {right arrow over (m)} of the IGBT module and the transmission characteristic curve eigenvector {right arrow over (n)}.sub.p of the IGBT module, wherein the greater the PPMCC.sub.B, the greater the correlation between the two, the higher the degree of health of bonding wires, and the higher the reliability of the module.

9. The system for comprehensively evaluating the reliability of the multi-chip parallel IGBT module according to claim 8, wherein the reliability evaluation module is used to perform a weighted summation on the linear correlation PPMCC.sub.C between the gate-emitter voltage in the chip fatigue failure state and the healthy state and the linear correlation PPMCC.sub.B between the transmission characteristic curve in the bonding wire shedding failure state and the healthy state to obtain an overall degree of health of the module, and evaluate the reliability of the multi-chip parallel IGBT module from the overall degree of health of the module, wherein the overall degree of health of the module reflects the overall degree of health of the module in terms of a chip health state of the module and a bonding wire health state of the module.

10. A computer-readable storage medium stored with a computer program, characterized in that when the computer program is executed by a processor, the steps of the method according to any one of claim 1 are implemented.

11. A computer-readable storage medium stored with a computer program, characterized in that when the computer program is executed by a processor, the steps of the method according to any one of claim 2 are implemented.

12. A computer-readable storage medium stored with a computer program, characterized in that when the computer program is executed by a processor, the steps of the method according to any one of claim 3 are implemented.

13. A computer-readable storage medium stored with a computer program, characterized in that when the computer program is executed by a processor, the steps of the method according to any one of claim 4 are implemented.

14. A computer-readable storage medium stored with a computer program, characterized in that when the computer program is executed by a processor, the steps of the method according to any one of claim 5 are implemented.

15. A computer-readable storage medium stored with a computer program, characterized in that when the computer program is executed by a processor, the steps of the method according to any one of claim 6 are implemented.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0033] FIG. 1 is a schematic flowchart of a method for comprehensively evaluating reliability of a multi-chip parallel IGBT module according to an embodiment of the disclosure.

[0034] FIG. 2 is a gate-emitter equivalent resistor-capacitor (RC) circuit according to an embodiment of the disclosure.

[0035] FIG. 3 is a principle diagram of a test circuit according to an embodiment of the disclosure.

[0036] FIG. 4 is a gate voltage V.sub.GE under different chip failures according to an embodiment of the disclosure.

[0037] FIG. 5 is a transmission characteristic curve u.sub.GE-i.sub.C under different bonding wire failures according to an embodiment of the disclosure.

DETAILED DESCRIPTION OF DISCLOSED EMBODIMENTS

[0038] In order for the objectives, technical solutions, and advantages of the disclosure to be clearer, the following further describes the disclosure in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the disclosure, but not to limit the disclosure. In addition, the technical features involved in the various embodiments of the disclosure described below may be combined with each other as long as there is no conflict therebetween.

[0039] In the example of the disclosure, “first”, “second”, etc. are used to distinguish different objects and are not necessarily used to describe a specific order or sequence.

[0040] FIG. 1 shows a schematic flowchart of a method for comprehensively evaluating reliability of a multi-chip parallel IGBT module according to an embodiment of the disclosure, which implements the identification of chip fatigue and bonding wire shedding failures in the multi-chip parallel IGBT module to perform health state monitoring and reliability evaluation.

[0041] The method shown in FIG. 1 includes the following steps.

[0042] In Step S1, a gate-emitter voltage reliability model of the multi-chip parallel IGBT module is established, a chip fatigue failure test is implemented in a test circuit, and a gate-emitter voltage is selected as a failure characteristic quantity.

[0043] Further, Step S1 may be implemented as follows.

[0044] A gate-emitter equivalent RC circuit in the embodiment of the disclosure is shown in FIG. 2. According to the gate-emitter equivalent RC circuit, during a turn-on process, a rising process of a gate voltage V.sub.GE is:

[00003]$V_{\mathrm{GE}}\left(t\right)=\left(V_{\mathrm{GG}\left(\mathrm{ON}\right)}-V_{\mathrm{GG}\left(\mathrm{OFF}\right)}\right)\left(1-e^{-\left[\frac{t}{R_G{C}_{\mathrm{ies}}}\right]}\right)+V_{\mathrm{GG}\left(\mathrm{OFF}\right)}$

[0045] where t is time; R.sub.G is a total gate resistance, R.sub.G=R.sub.G(int)+R.sub.G(ext), R.sub.G(int) is an internal gate resistance, and R.sub.G(ext) is an external gate resistance; C.sub.ies is a total gate input capacitance, C.sub.ies=C.sub.GE+C.sub.GC, V.sub.GG(ON) represents a turn-on voltage of a gate drive power supply, V.sub.GG(OFF) represents a turn-off voltage of the gate drive power supply, C.sub.GE represents a gate-emitter capacitance, and C.sub.GC represents a gate-collector capacitance.

[0046] A principle diagram of a test circuit is shown in FIG. 3. A direct current bus power supply voltage of the test circuit is 1800 V, and a load is an inductive load of 400 μH. When a chip of the IGBT module fails, the total gate input capacitance C.sub.ies of the IGBT module decreases, and a total internal gate resistance R.sub.G(int),total of the IGBT module increases, and a trajectory of V.sub.GE changes. In the test circuit, the gate voltage V.sub.GE under different chip failures is measured as the characteristic quantity of chip failure monitoring. Taking a DIM800NSM33-F IGBT module as an example, the chip fatigue failure test is performed on the states of “healthy”, “1 chip failure”, and “2 chip failures”. FIG. 4 shows the gate-emitter voltage V.sub.GE under different chip failures.

[0047] In Step S2, a transconductance reliability model of the multi-chip parallel IGBT module is established, a bonding wire shedding failure test is implemented in a test circuit, and a transmission characteristic curve of the module is selected as a failure characteristic quantity.

[0048] Further, Step S2 may be implemented as follows.

[0049] A horizontal axis of the transmission characteristic curve of the IGBT module is a gate-emitter voltage u.sub.GE, and a vertical axis is a collector current i.sub.c. According to the working principle of the IGBT chip, when the IGBT chip works in an active area, a control equation of the collector current i.sub.c is:

[00004]$i\frac{{\mu }_{\mathrm{ni}}{C}_{\mathrm{OX}}Z}{2{L\left(1-{\alpha }_{\mathrm{pnp}}\right)}_{{{\mathrm{GE}}_{{\mathrm{GE}\left(\mathrm{th}\right)}^2}}_{{\mathrm{GE}}_{{{\mathrm{GE}\left(\mathrm{th}\right)}^2}_c}}}}$

[0050] where μ.sub.ni is an electron migration speed, C.sub.OX is an oxide layer capacitance, Z and L are a length and a width of an internal gate-emitter of a metal-oxide-semiconductor field-effect transistor (MOSFET), α.sub.pnp is a current gain of a PNP transistor, U.sub.GE(th) is a threshold voltage of the IGBT chip, and the above parameters are all determined by the structure and the material of the chip.

[0051] When the rate of change of the collector current i.sub.c and a gate current i.sub.G is relatively small, the parasitic resistance and all parasitic inductances may be ignored, and u.sub.G may be approximated as:

u.sub.GE=u.sub.i−i.sub.cR.sub.w

[0052] where u.sub.i is a gate drive voltage of the IGBT module, and a parameter R.sub.w is a bonding wire equivalent resistance.

[0053] When a bonding wire in the IGBT module sheds, the bonding wire equivalent resistance R.sub.w increases, thereby causing the transmission characteristic curve of the module to change.

[0054] The transmission characteristic curve obtained according to the test circuit measuring the collector current and the gate-emitter voltage is used as the characteristic quantity of bonding wire failure monitoring. Taking a DIM800NSM33-F IGBT module as an example, there are 8 bonding wires on one chip of the module, and a bonding wire state is that i (where i=0, 1, 2, . . . , 8) bonding wires shed. FIG. 5 shows the transmission characteristic curve of the IGBT module in different bonding wire failure states in the test circuit.

[0055] In Step S3, a degree of health of the IGBT module is defined, a Pearson correlation coefficient is used to characterize the degree of health, and the degrees of health, that is PPMCC.sub.C and PPMCC.sub.B, in different degrees of chip fatigue failure and bonding wire shedding failure states are respectively calculated.

[0056] The degree of health of the IGBT module in a healthy state may be defined as 1, that is, PPMCC.sub.H=1.

[0057] Further, Step S3 may be implemented as follows.

[0058] In Step S3.1, the reliability of the IGBT module is characterized by the degree of health. The greater the degree of health, the higher the reliability of the module. When the module has no chip fatigue failure and no bonding wire shedding failure, the degree of health is maximum, and the value may be set to 1. When the IGBT module is in a healthy initial state without chip fatigue failure, a gate-emitter voltage eigenvector is {right arrow over (x)}. When i chips fail in the module, an eigenvector is {right arrow over (y)}.sub.i. A Pearson correlation coefficient PPMCC.sub.C may reflect a linear correlation between the gate-emitter voltage in the chip fatigue failure state and the healthy state of the module. The greater the PPMCC.sub.C, the higher the correlation between the two, the higher the degree of health of chips, and the stronger the reliability. When the IGBT module is in the healthy initial state without bonding wire shedding failure, a transmission characteristic curve eigenvector of the module is {right arrow over (m)}. When p bonding wires fail in the module, an eigenvector is {right arrow over (n)}.sub.p. A Pearson correlation coefficient PPMCC.sub.B may reflect a linear correlation between the transmission characteristic curve in the bonding wire shedding failure state and the healthy state. The greater the PPMCC.sub.B, the greater the correlation between the two, the higher the degree of health of bonding wires, and the more reliable the module.

[0059] In Step S3.2, PPMCC.sub.C is used to characterize the degree of health of the module affected by the chip fatigue failure. With reference to the initial health state, the Pearson correlation coefficient is used to characterize the degree of health, that is, PPMCC.sub.C=1. The degree of health of the module when there is the chip fatigue failure in the module is expressed by PPMCC.sub.C, and the calculation method is:

[00005]${\mathrm{PPMCC}}_c=r\left(\stackrel{.fwdarw.}{x},\stackrel{.fwdarw.}{y_l}\right)=\frac{{.Math.}_{j=1}^h\left(x_j-\stackrel{-}{x}\right)\left(y_{\mathrm{ij}}-{\stackrel{-}{y}}_i\right)}{\sqrt{{.Math.}_{j=1}^h{\left(x_j-\stackrel{-}{x}\right)}^2\sqrt{{.Math.}_{j=1}^h{\left(y_{\mathrm{ij}}-{\stackrel{-}{y}}_i\right)}^2}}}$

[0060] where h represents a number of selected samples, x.sub.j represents an observed value of a point j corresponding to the gate-emitter voltage eigenvector {right arrow over (x)} without chip failure, x represents a mean of observed values of the eigenvector {right arrow over (x)}, y.sub.ij represents an observed value of the point j corresponding to the gate-emitter voltage eigenvector {right arrow over (y)}.sub.i when i chips fail, and y.sub.i represents a mean of observed values of the eigenvector {right arrow over (y)}.sub.i.

[0061] PPMCC.sub.C is calculated according to the above method according to the gate voltage V.sub.GE under different chip fatigue failures obtained in the test, and the calculation result is shown in Table 1.

TABLE-US-00001 TABLE 1 PPMCC.sub.C in different chip fatigue failure states Number of IGBT chip failures PPMCC.sub.C 0 1 1 0.952 2 0.917

[0062] The PPMCC.sub.B is used to characterize the degree of health of the module affected by the bonding wire shedding failure. With reference to the initial health state, the Pearson correlation coefficient is used to characterize the degree of health, that is, PPMCC.sub.B=1. The degree of health of the module when there is the bonding wire failure in the module is expressed by PPMCC.sub.B, and the calculation method is:

[00006]$PPMC{C}_B=r\left(\stackrel{.fwdarw.}{m},\stackrel{.fwdarw.}{n_p}\right)=\frac{{\Sigma }_{q=1}^l\left(m_q-\stackrel{-}{m}\right)\left(n_{pq}-{\stackrel{-}{n}}_p\right)}{\sqrt{{{\Sigma }_{q=1}^l\left(m_p-\stackrel{-}{m}\right)}^2}\sqrt{{.Math.}_{q=1}^l{\left(n_{\mathrm{pq}}-{\stackrel{-}{n}}_p\right)}^2}}$

[0063] where l represents a number of selected samples, m.sub.q represents an observed value of a point q corresponding to the transmission characteristic curve eigenvector {right arrow over (m)} of the module without bonding wire shedding, m represents a mean of observed values of the eigenvector {right arrow over (m)}, n.sub.pq represents an observed value of the point q corresponding to the transmission characteristic curve eigenvector {right arrow over (n)}.sub.p of the module when p bonding wires shed, and n.sub.p represents a mean of observed values of the eigenvector n.sub.p.

[0064] The PPMCC.sub.B is calculated according to the above method according to the transmission characteristic curve under different bonding wire failures obtained in the test, and the calculation result is shown in Table 2.

TABLE-US-00002 TABLE 2 PPMCC.sub.B in different bonding wire shedding failure states Number of IGBT bonding wire failures Gate current PPMCC.sub.B 0 1 1 0.993 2 0.984 3 0.976 4 0.965 5 0.957 6 0.948 7 0.940 8 0.925

[0065] In Step S4, the reliability of the multi-chip parallel IGBT module is comprehensively evaluated according to PPMCC.sub.C and PPMCC.sub.B.

[0066] Further, Step S4 may be implemented as follows.

[0067] In Step S4.1, PPMCC.sub.H is defined as an overall degree of health of the module. The overall degree of health of the module may reflect a chip health state of the module and a bonding wire health state of the module. The overall degree of health of the module PPMCC.sub.H is related to the degree of health of chips PPMCC.sub.C and the degree of health of bonding wires PPMCC.sub.B, that is, PPMCC.sub.H=f(PPMCC.sub.C, PPMCC.sub.B). When there is no chip fatigue failure and no bonding wire shedding failure in the IGBT module, the overall degree of health of the module is defined as 1, that is, PPMCC.sub.H=1.

[0068] In Step S4.2, 20% of module failures in the IGBT module are caused by the chip fatigue failure, and 80% of module failures are caused by the bonding wire shedding failure. The overall degree of health of the module is jointly measured by the degree of health of the module PPMCC.sub.C affected by the chip fatigue failure of the module and the degree of health of the module PPMCC.sub.B affected by the bonding wire shedding failure. The calculation method of the module reliability comprehensive indicator PPMCC.sub.H is:

PPMCC.sub.H=0.2*PPMCC.sub.C+0.8*PPMCC.sub.B

[0069] The module reliability comprehensive indicator PPMCC.sub.H is affected by the chip health state and the bonding wire health state of the module at the same time, which can more comprehensively reflect the overall degree of health of the module. When the module is in a completely healthy state, that is, there is no chip fatigue failure and no bonding wire shedding failure, the module reliability comprehensive indicator is PPMCC.sub.H=1. With the aging of the module and the occurrence of the chip fatigue and bonding wire shedding failures, the module reliability comprehensive indicator PPMCC.sub.H gradually decreases, and the reliability of the module gradually decreases. Therefore, the reliability of the module may be comprehensively evaluated through the module reliability comprehensive indicator PPMCC.sub.H. The greater the PPMCC.sub.H, the higher the reliability of the module.

[0070] The disclosure also provides a system for comprehensively evaluating reliability of a multi-chip parallel IGBT module, which includes the following.

[0071] A first failure characteristic quantity acquisition module is used to establish a gate-emitter voltage reliability model of the multi-chip parallel IGBT module, implement a chip fatigue failure test based on the gate-emitter voltage reliability model, and select a gate-emitter voltage as a failure characteristic quantity.

[0072] A second failure characteristic quantity acquisition module is used to establish a transconductance reliability model of the multi-chip parallel IGBT module, implement a bonding wire shedding failure test based on the transconductance reliability model, and select a transmission characteristic curve of the module as a failure characteristic quantity.

[0073] A health degree calculation module is used to define a degree of health of the IGBT module, use a Pearson correlation coefficient to characterize the degree of health, and calculate a degree of health PPMCC.sub.C in different degrees of chip fatigue failure states and a degree of health PPMCC.sub.B in different degrees of bonding wire shedding failure states.

[0074] A reliability evaluation module is used to comprehensively evaluate the reliability of the multi-chip parallel IGBT module according to PPMCC.sub.C and PPMCC.sub.B.

[0075] Further, the health degree calculation module includes the following.

[0076] A health parameter definition module is used to adopt the degree of health to characterize the reliability of the IGBT module. When the module has no chip fatigue failure and no bonding wire shedding failure, the degree of health is maximum. When the IGBT module is in a healthy initial state without chip fatigue failure, a gate-emitter voltage eigenvector is {right arrow over (x)}. When i chips fail in the IGBT module, a gate-emitter voltage eigenvector is {right arrow over (y)}.sub.i. When the IGBT module is in the healthy initial state without bonding wire shedding failure, a transmission characteristic curve eigenvector of the IGBT module is {right arrow over (m)}. When p bonding wires shed in the IGBT module, a transmission characteristic curve eigenvector of the IGBT module is n.sub.p.

[0077] A chip health calculation module is used to obtain the linear correlation PPMCC.sub.C between the gate-emitter voltage in a chip fatigue failure state and a healthy state based on the gate-emitter voltage eigenvector x and the gate-emitter voltage eigenvector {right arrow over (y)}.sub.i. The greater the PPMCC.sub.C, the higher the correlation between the two, the higher the degree of health of chips, and the stronger the reliability.

[0078] A bonding wire health calculation module is used to obtain the linear correlation PPMCC.sub.B between the transmission characteristic curve in a bonding wire shedding failure state and the healthy state based on the transmission characteristic curve eigenvector {right arrow over (m)} of the IGBT module and the transmission characteristic curve eigenvector n.sub.p of the IGBT module. The greater the PPMCC.sub.B, the greater the correlation between the two, the higher the degree of health of bonding wires, and the higher the reliability of the module.

[0079] Further, the reliability evaluation module is used to perform a weighted summation on the linear correlation PPMCC.sub.C between the gate-emitter voltage in the chip fatigue failure state and the healthy state and the linear correlation PPMCC.sub.B between the transmission characteristic curve in the bonding wire shedding failure state and the healthy state to obtain an overall degree of health of the module, and evaluate the reliability of the multi-chip parallel IGBT module from the overall degree of health of the module. The overall degree of health of the module reflects the overall degree of health of the module in terms of a chip health state of the module and a bonding wire health state of the module.

[0080] For the specific implementation of each module, reference may be made to the description of the foregoing embodiment of the method, which will not be repeated in the embodiment of the disclosure.

[0081] It should be noted that according to implementation requirements, each step/component described in the disclosure may be split into more steps/components or two or more steps/components or partial operation of a step/component may be combined into a new step/component to implement the objective of the disclosure.

[0082] Persons skilled in the art may easily understand that the above are only preferred embodiments of the disclosure and are not intended to limit the disclosure. Any modification, equivalent replacement, improvement, etc., made within the spirit and principle of the disclosure should be included in the protection scope of the disclosure.