Phase/frequency tracking transceiver

Abstract

A radio frequency (RF) transceiver includes a reference signal source to generate a reference signal, a local RF source to generate a local RF signal and a mixed-signal phase/frequency detector to compare the reference signal to the local RF signal, and to generate a difference signal from the comparison, wherein the difference signal comprises a modulation component and an error component. The transceiver also includes a receiver front end to receive and downconverts an angle-modulated RF signal to a baseband signal, a quadrature modulator configured to angle-modulate the reference signal source with the baseband signal.

Claims

1. A radio frequency (RF) transceiver, comprising: a reference signal source configured to generate a reference signal; a local RF source configured to generate a local RF signal; and a mixed-signal phase/frequency detector configured to compare the reference signal to the local RF signal, and to generate a difference signal from the comparison, wherein the difference signal comprises a modulation component and an error component.

2. The RF transceiver of claim 1, further comprising a receiver front end configured to receive and downconvert an angle-modulated RF signal to a baseband signal; a quadrature modulator coupled with the receiver front end and the reference signal source, wherein the quadrature modulator is configured to angle-modulate the reference signal source with the baseband signal; and a limiter coupled with the quadrature modulator to limit the angle-modulated reference signal.

3. The RF transceiver of claim 2, wherein the mixed-signal phase/frequency detector comprises a fractional-N, delta-sigma phase/frequency detector (ΔΣ-PFD) configured to frequency divide the local RF signal, wherein the difference signal is derived from comparing zero crossings of the angle-modulated reference signal and zero crossings of the frequency divided local RF signal, and wherein the modulation component comprises a digitized baseband signal and the error component comprises a fractional control sequence.

4. The RF transceiver of claim 3, wherein the local RF source comprises a digitally-controlled oscillator (DCO), the RF transceiver further comprising: an adder coupled with the ΔΣ-PFD, configured to generate a digital frequency error from a difference between the fractional control sequence and a fractional control number; an accumulator coupled with the adder, configured to generate a digital phase error from the digital frequency error; and a digital loop filter (DLF) configured to select the digital phase error, wherein the digital phase error is adapted to phase-lock the DCO to the reference signal.

5. The RF transceiver of claim 4, further comprising a digital demodulator coupled with the ΔΣPFD, the digital demodulator configured to decode the digitized baseband signal to recover a stream of received data bits.

6. The RF transceiver of claim 1, further comprising: a quadrature modulator without a modulation input, coupled with the reference signal source, wherein the reference signal is passed through the quadrature modulator without modulation, and wherein the local RF source comprises a digitally-controlled oscillator (DCO) configure to be angle-modulated by a digitized baseband signal.

7. The RF transceiver of claim 6, wherein the mixed-signal phase/frequency detector comprises a fractional-N, delta-sigma phase/frequency detector (ΔΣ-PFD), configured to frequency divide the angle-modulated local RF signal, wherein the difference signal is derived from comparing zero crossings of the reference signal and zero crossings of the frequency divided, angle-modulated local RF signal, and wherein the modulation component comprises the digitized baseband signal and the error component comprises a fractional control sequence.

8. The RF transceiver of claim 7, further comprising: a first adder coupled with the ΔΣ-PFD, configured to generate a digital frequency error from a difference between the fractional control sequence and a fractional control number; an accumulator coupled with the first adder, configured to generate a digital phase error from the digital frequency error; and a digital loop filter (DLF) configured to select the digital phase error, wherein the digital phase error is adapted to phase-lock the DCO to the reference signal.

9. The RF transceiver of claim 8, further comprising a digital modulator coupled with the first adder and with a second adder coupled between the DLF and the DCO, the digital modulator configured to encode a sequence of transmit data bits into the digitized baseband signal, wherein the digitized baseband signal from the ΔΣ-PFD is canceled in the first adder by the digitized baseband signal from the digital modulator, and wherein the digitized baseband signal from the digital modulator is added to the digital phase error signal in the second adder to modulate the DCO with the digitized baseband signal.

10. The RF transceiver of claim 9, further comprising a power amplifier (PA) coupled with the DCO, to amplify the signal from the digital baseband modulated DCO.

11. A method in a radio frequency transceiver, comprising: comparing a reference signal from a reference source to a local radio frequency (RF) signal in a mixed-signal phase/frequency detector; generating a difference signal from the comparison, the difference signal comprising a modulation component and an error component; and phase-locking the local RF signal to the reference signal with the error component to perform angle demodulation for RF receiving and angle modulation for RF transmitting.

12. The method of claim 11, further comprising: receiving and downconverting an angle-modulated RF signal to a baseband signal in a receiver front end; and angle-modulating the reference source with the baseband signal to generate an angle-modulated reference signal.

13. The method of claim 12, wherein the mixed signal phase/frequency detector comprises a fractional-N, delta-sigma phase/frequency detector (ΔΣ-PFD) configured to frequency-divide the local RF signal, wherein the difference signal is derived from comparing zero crossings of the angle-modulated reference signal with zero crossings of the frequency-divided local RF signal.

14. The method of claim 13, wherein the modulation component comprises a digitized baseband signal and the error component comprises a fractional control sequence.

15. The method of claim 14, wherein the local RF signal is generated by a digitally-controlled oscillator (DCO), the method further comprising: generating a digital frequency error from a difference between the fractional control sequence and a fractional control number; accumulating the digital frequency error to generate a digital phase error; and selecting the digital phase error with a digital loop filter (DLF), wherein phase-locking the local RF signal to the reference signal comprises tuning the DCO with the digital phase error.

16. The method of claim 15, further comprising demodulating the digital baseband signal to recover a stream of received data bits.

17. The method of claim 11, further comprising angle-modulating a local RF signal source with a digitized baseband signal to generate the local RF signal.

18. The method of claim 17, wherein the mixed-signal phase/frequency detector comprises a fractional-N, delta-sigma phase/frequency detector (ΔΣ-PFD) configured to frequency-divide the local RF signal, wherein the difference signal is derived from comparing zero crossings of the reference signal with zero crossings of the frequency-divided, local RF signal, and wherein the modulation component comprises the digitized baseband signal and the error component comprises a fractional control sequence.

19. The method of claim 18, wherein the local RF signal source comprises a digitally-controlled oscillator (DCO), the method further comprising: generating a digital frequency error from a difference between the fractional control sequence and a fractional control number; accumulating the digital frequency error to generate a digital phase error; and selecting the digital phase error with a digital loop filter (DLF), wherein phase-locking the local RF signal to the reference signal comprises tuning the DCO with the digital phase error.

20. The method of claim 19, wherein angle-modulating the local RF signal source comprises: encoding a stream of data bits in a digital modulator to generate the digitized baseband signal; combining the digitized baseband signal with the digital phase error at a digital control input of the DCO; and tuning the DCO with the digitized baseband signal.

21. The method of claim 20, further comprising: amplifying the angle-modulated local RF signal; and transmitting the amplified angle-modulated local RF signal.

22. A system, comprising: a radio frequency (RF) transceiver, comprising: a reference signal source configured to generate a reference signal; a local RF source configured to generate a local RF signal; and a mixed-signal phase/frequency detector configured to compare the reference signal to the local RF signal, and to generate a difference signal from the comparison, wherein the difference signal comprises a modulation component and an error component; and an antenna coupled with the RF transceiver to transmit and receive angle-modulated RF signals.

23. The system of claim 22, further comprising: a receiver front end configured to receive and downconvert an angle-modulated RF signal to a baseband signal; and a quadrature modulator coupled with the receiver front end and the reference signal source, wherein the quadrature modulator is configured to angle-modulate the reference signal source with the baseband signal.

24. The system of claim 23, wherein the mixed-signal phase/frequency detector comprises a fractional-N, delta-sigma phase/frequency detector (ΔΣ-PFD), configured to frequency divide the modulated local RF signal, wherein the difference signal is derived from comparing zero crossings of the reference signal and zero crossings of the frequency divided local RF signal, and wherein the modulation component comprises a digitized baseband signal and the error component comprises a fractional control sequence.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) For a more complete understanding of various examples, reference is now made to the following detailed description taken in connection with the accompanying drawings in which like identifiers correspond to like elements:

(2) FIG. 1 is a block diagram illustrating an example transceiver according to the present disclosure;

(3) FIG. 2 is a block diagram illustrating the example transceiver of FIG. 1 in receive mode;

(4) FIG. 3A is a block diagram illustrating the example transceiver of FIG. 1 in a first transmit mode;

(5) FIG. 3B is a block diagram illustrating the example transceiver of FIG. 1 in a second transmit mode;

(6) FIG. 4 is a block diagram illustrating an example transceiver according to the present disclosure;

(7) FIG. 5 is a flowchart illustrating an example method for implementing a receiver in a phase/frequency tracking transceiver according to the present disclosure; and

(8) FIG. 6 is a flowchart illustrating an example method for implementing a transmitter in a phase/frequency tracking transceiver according to the present disclosure.

DETAILED DESCRIPTION

(9) The present disclosure describes examples of systems and method for coherently modulating and demodulating angle-modulated (i.e., constant envelope) radio frequency signals using phase/frequency tracking transceivers.

(10) FIG. 1 is a block diagram illustrating an example phase/frequency tracking transceiver 100 according to the present disclosure. Transceiver 100 is coupled to an antenna 101 to transmit and receive angle-modulated RF carrier signals (signals 102A and 102B, respectively). Antenna 101 is connected to a first transmit/receive switch (TR1), 102 which selects between transmit and receive modes. The receive chain (receiver front end) includes a low noise amplifier (LNA) 103, a digitally controlled local oscillator (DCO) 104, a mixer 105 and a channel selection filter (CSF) 106. The frequency of the DCO 104 is selected and controlled to generate a zero (or low frequency) intermediate frequency (IF) baseband signal 105A at the output of mixer 105. The CSF 106 is configured to filter out unwanted noise and interference from the baseband signal.

(11) The output of CSF 106 is coupled to a quadrature phase modulator that includes a 90-degree phase shifter 107, mixers 108 and 109, a 0/90-degree phase shifter 110 and an adder 111.

(12) In receive mode, a stable (e.g., crystal controlled) reference oscillator 112 is used to provide a reference signal (f.sub.ref), via the 0/90-degree phase shifter 110, that is modulated by the quadrature modulator with the baseband signal. As a result of the quadrature mixing, the output S.sub.ref(t) at the output of adder 111 carries the angle modulation of the original RF input signal at the frequency (f.sub.ref) of the reference oscillator 112.

(13) The output of adder 111, S.sub.ref(t), is limited by limiter 113 to generate a constant amplitude sequence of pulses corresponding to zero crossings that track the phase shifts of the angle modulated reference oscillator 112. In receive mode, a second transmit/receive switch (TR2) 114 connects the output of limiter 113 to one input of a mixed signal (e.g., hybrid analog/digital) phase/frequency detector, which may be a fractional-N delta-sigma phase/frequency detector (ΔΣ-PFD) 115. The ΔΣ-PFD 115 includes a phase-frequency detector (PFD) 116, a charge pump (CP) 117, a delta-sigma analog to digital converter (ΔΣ-ADC) 118, an adder 119 and a multi-modulus divider (MMD) 120. A second input of the ΔΣ-PFD 115 receives the local oscillator signal S.sub.LO(t) from the DCO 104.

(14) The ΔΣ-PFD 115 compares the phase of the baseband modulated (i.e., angle-modulated) reference oscillator signal with the phase of a divided down version of the DCO signal S.sub.LO(t) from MMD 120, and locks the frequency of the DCO 104 to (N.sub.int+N.sub.frac).Math.f.sub.ref, where N.sub.int (an integer value) and N.sub.frac (a fractional value) are determined by the carrier frequency of a selected RF channel. The signal S.sub.LO(t) can be mathematically described as:
S.sub.LO(t)=A.sub.LO cos(2πƒ.sub.LOt+∫2πΔƒ.sub.m(τ)dτ)
Where ƒ.sub.LO is the RF carrier frequency, Δƒ.sub.m−N.sub.mod f.sub.ref, where N.sub.mod is a digitized baseband signal, and A.sub.LO is the amplitude of the signal envelope.

(15) The MMD 120 performs fractional-N division of the DCO 104 local oscillator input by N.sub.int+{ . . . , −1, 0, 1, . . . }, where { . . . , −1, 0, 1, . . . } reflects the long-term fractional division control of the MMD 120 averaging over time to a value N.sub.frac, and the PFD/CP combination produces the phase error between the divided DCO 104 input and the reference oscillator signal f.sub.ref in the form of an f.sub.ref-rate pulse-width modulated (PWM) current signal (I.sub.cp). The ΔΣ-ADC 118 digitizes the I.sub.cp signal. An L.sup.th-order ΔΣ-ADC implements an (L+1).sup.th order ΔΣ-PFD by virtue of closing the loop within the ΔΣ-PFD.

(16) The output of the ΔΣ-PFD 115 includes the digitized baseband modulation component, N.sub.mod (121), and a digitized error component comprising a fractional control sequence 122 that averages to the required value of N.sub.frac over time. The fractional control sequence 122 is combined with N.sub.int in adder 119 and fed back to MMD 120 to set the instantaneous divider value of MMD 120 at each f.sub.ref clock cycle. The fractional control sequence 122 is also provided to adder 123, where it is subtracted from N.sub.frac at each clock cycle to generate a frequency error Δf.sub.e. The sequential values of Δf.sub.e are accumulated in an accumulator 124, which integrates the frequency error into phase error. The phase error signal is passed by digital loop filter (DLF) 125, which has a bandwidth greater than the frequency of the phase error signal. However, the bandwidth of the DLF 125 is below the bandwidth of the modulation N.sub.mod, so that the DCO is not affected by N.sub.mod. Rather N.sub.mod is directed to a digital demodulator 126, which extracts the RX bits.

(17) For clarity, FIG. 1 is reproduced in part as system 200 in FIG. 2, illustrating only the components used when system 100 is configured as a receiver. As noted above, the ΔΣ-PFD 115 includes a PFD 116 and a CP 117, which are analog components. The PFD 116 generates voltage pulses with widths corresponding to the phase difference between the baseband modulated reference oscillator signal from limiter 113 and the divided down version of the local oscillator signal from DCO 104, provided by MMD 120. The charge pump 117 converts the voltage pulses into pulse width modulated (PWM) current pulses I.sub.cp to drive the ΔΣ-ADC 118. The ΔΣ-ADC 118 digitizes the current pulses into the digitized baseband signal 121 (modulation component) and the fractional control sequence 122 (error component) that controls the MMD 120 in conjunction with N.sub.int. Thus, the ΔΣ-PFD 115 is implemented as a hybrid analog-digital frequency/phase detector.

(18) FIG. 1 is reproduced in part as system 300 in FIG. 3A, illustrating only the components used when system 100 is configured as a transmitter when transmit/receive phase coherence is required. In particular, the LNA 103, mixer 105 and CDF 106 are not used in transmit mode and can be disabled to reduce power consumption. In FIG. 3A, data to be transmitted (TX bits) are converted to the digitized baseband signal N.sub.mod by digital modulator 127. N.sub.mod from digital modulator 127 is coupled to DCO 104 through a transmit gain controller 128 and adder 129, where it modulates DCO 104. The modulated signal S.sub.LO(t) from DCO 104 is provided as one input to ΔΣ-PFD 115. N.sub.mod from digital modulator 127 is also coupled to adder 123 where it is cancelled by the digitized baseband signal N.sub.mod 121 from the ΔΣ-PFD 115.

(19) In TX mode with phase coherence, as illustrated in FIG. 3A, the reference oscillator 112 is still connected to the quadrature modulator (as in the RX mode). However, since there is no baseband signal from the receiver front end, the output of the quadrature modulator is simply f.sub.ref, the signal from reference oscillator 112. This signal is limited by limiter 113 and directly to the PFD 114 of ΔΣ-PFD 115 via transmit/receive switch TR2 (not shown). This mode of operation allows the transceiver to switch from receive mode to transmit mode without switching the connection of the reference oscillator, which provides phase coherence.

(20) As noted above, signal S.sub.LO(t) from DCO 104 is provided to MMD 120. As in the case of the receive mode operation, the PFD 116 compares the reference oscillator signal f.sub.ref, provided by reference oscillator 112, with the modulated signal from DCO 104 divided down in frequency by MMD 120. The PFD 116 and the CP 117 produce a sequence of pulse width modulated (PWM) current pulses I.sub.cp based on the phase differences between the reference oscillator signal (fref) and the divided down DCO signal, which is modulated by N.sub.mod as described above. Accordingly, the digitized output of the ΔΣ-ADC 118 includes both the fractional control sequence 122 that represents the difference between N.sub.int and N.sub.frac, and the digital modulation N.sub.mod 121. The fractional control sequence 122 is combined with N.sub.int in adder 119 to adjust the instantaneous divider ratio of MMD 120 with each clock cycle of reference oscillator 112.

(21) The digitized baseband modulation data N.sub.mod 121 and the fractional control sequence 122 from ΔΣ-ADC 118 are coupled to adder 123. As noted above, the digital baseband signals (N.sub.mod) from the ΔΣ-PFD 115 and the digital modulator 127 cancel out, but the fractional control sequence 122 is differenced with N.sub.frac on a clock cycle by clock cycle basis, and the difference between the fractional control sequence 122 and the fractional control number N.sub.frac appears as the digital frequency error signal Δf.sub.e. As described above with respect to the receive mode of operation, the digital frequency error signal Δf.sub.e is integrated by accumulator 124 into an accumulated digital phase error Δϕ.sub.e. The digital phase error Δϕ.sub.e corresponding to the error between N.sub.frac and the fractional control sequence 122 is passed by the narrowband digital loop filter 125, where it is combined in adder 129 with the gain adjusted digital N.sub.mod signal from a wideband TX gain controller 128, to drive the DCO 104 into phase-lock with the reference oscillator 112, and to modulate the DCO 104 with the digitized transmission data N.sub.mod. This approach, using a narrowband loop to control the center RF frequency of the signal source (DCO 104), and a wideband path outside of the loop to modulate the signal source is known as two-point modulation. The modulated DCO signal is then coupled to the power amplifier (PA) 130 through TR switch 102 and the amplified signal is transmitted by antenna 101.

(22) FIG. 1 is reproduced in part as system 350 in FIG. 3B, illustrating only the components used when system 100 is configured as a transmitter when transmit/receive phase coherence is not required. As illustrated in FIG. 3B, the connection of the reference oscillator 112 is switched from the quadrature modulator to a direct connection with the ΔΣ-PFD 115. This allows the components of the quadrature modulator to be powered down to reduce overall power consumption.

(23) As in the case of system 300 of FIG. 3A, data to be transmitted (TX bits) are converted to the digitized baseband signal N.sub.mod by digital modulator 127. N.sub.mod from digital modulator 127 is coupled to DCO 104 through a transmit gain controller 128 and adder 129, where it modulates DCO 104. The modulated signal SLO(t) from DCO 104 is provided as one input to ΔΣ-PFD 115. N.sub.mod from digital modulator 127 is also coupled to adder 123 where it is cancelled by the digitized baseband signal N.sub.mod 121 from the ΔΣ-PFD 115.

(24) As noted above, signal S.sub.LO(t) from DCO 104 is provided to MMD 120. The PFD 116 compares the reference oscillator signal f.sub.ref, provided by reference oscillator 112, with the modulated signal from DCO 104 divided down in frequency by MMD 120. The PFD 116 and the CP 117 produce a sequence of pulse width modulated (PWM) current pulses I.sub.cp based on the phase differences between the reference oscillator signal (fref) and the divided down DCO signal, which is modulated by N.sub.mod as described above. Accordingly, the digitized output of the ΔΣ-ADC 118 includes both the fractional control sequence 122 that represents the difference between N.sub.int and N.sub.frac, and the digital modulation N.sub.mod 121. The fractional control sequence 122 is combined with N.sub.int in adder 119 to adjust the instantaneous divider ratio of MMD 120 with each clock cycle of reference oscillator 112.

(25) The digitized baseband modulation data N.sub.mod 121 and the fractional control sequence 122 are coupled to adder 123. As noted above, the digital baseband signals (N.sub.mod) from the ΔΣ-PFD 115 and the digital modulator 127 cancel out, but the fractional control sequence 122 is differenced with N.sub.frac on a clock cycle by clock cycle basis (at the rate f.sub.ref of reference oscillator 112), and the difference between the fractional control sequence 122 and the fractional control number N.sub.frac appears as the digital frequency error signal Δf.sub.e. As described above, the digital frequency error signal Δf.sub.e is integrated by accumulator 124 into an accumulated digital phase error Δϕ.sub.e. The digital phase error Δϕ.sub.e corresponding to the error between N.sub.frac and the fractional control sequence 122 is passed by the narrowband digital loop filter 125, where it is combined in adder 129 with the gain adjusted digital N.sub.mod signal from a wideband TX gain controller 128, to drive the DCO 104 into phase-lock with the reference oscillator 112, and to modulate the DCO 104 with the digitized transmission data N.sub.mod. The modulated DCO signal is then coupled to the power amplifier (PA) 130 through TR switch 102 (not shown) and the amplified signal is transmitted by antenna 101.

(26) While the closed loop operation described herein operates to drive the digital frequency error Δf.sub.e toward zero, there are variations in the DCO's digital gain (K.sub.dco in Hertz per least significant bit) due to process, voltage and temperature (PVT) variations that result in residual Δf.sub.e. The latter serves as an error signal to adaptively track the DCO gain, effectively eliminating its process-voltage-temperature (PVT) variations and maximizing the transmit path bandwidth that cannot be directly corrected by the normal operation of the loop. Accordingly, any residual digital frequency error Δfe is processed by the calibration module (CAL) 131 to correct the transmission gain with TX gain module 128 for such variations.

(27) FIG. 4 is a block diagram illustrating another example phase/frequency tracking transceiver 400 according to the present disclosure. System 400 is similar in most respects to system 100, as indicated by the like reference designators in system 100 and system 400. The transceiver illustrated in FIG. 4 replaces the single-channel mixer 105 and CSF 106 of system 100 with a quadrature mixer 132 and complex CSF 133, respectively, eliminating the need for 90-degree phase shifter 107 for the secondary mixing operation.

(28) FIG. 5 is a flowchart illustrating an example method 500 for receiving an angle-modulated radio frequency signal in a phase/frequency tracking transceiver according to the present disclosure. With reference to FIG. 2, method 500 begins at operation 502, receiving & downconverting an angle-modulated radio frequency (RF) signal (e.g., 102B) to a baseband signal (e.g., 105A) in a receiver front end (e.g., antenna 101, LNA 103, and mixer 105). Method 500 continues at operation 504, angle-modulating a reference source (e.g., reference source 112) with the baseband signal to generate an angle-modulated reference signal. (e.g., Sref(t)). Next, method 500 continues at operation 506, comparing zero crossings of the angle-modulated reference signal to zero crossings of a frequency divided local RF signal (e.g., S.sub.LO(t)) in a fractional-N, delta-sigma phase/frequency detector, to generate a difference signal comprising a modulation component (e.g., digitized baseband signal N.sub.mod 121) and an error component (e.g., fractional control sequence 122). In one example, method 500 continues at operation 508: generating a digital frequency error (e.g., Δf.sub.e) from a difference between the fractional control sequence (e.g., 122) and a fractional control number (e.g., N.sub.frac); at operation 510: accumulating the digital frequency error (e.g., in accumulator 124) to generate the digital phase error signal Δϕ.sub.e; at operation 512: selecting the digital phase error (e.g., Δϕ.sub.e) with a digital loop filter (e.g., DLF 125); at operation 514: phase-locking local RF signal to the reference signal (e.g., f.sub.ref) by tuning a digitally-controlled oscillator (e.g., DCO 104) with the digital phase error; and at operation 516: demodulating the digital baseband signal in digital demodulator (e.g., demodulator 126) to recover a stream of received (RX) data bits.

(29) FIG. 6 is a flowchart illustrating an example method 600 for transmitting angle-modulated RF signals in a phase/frequency tracking transceiver according to the present disclosure. With reference to FIG. 3, method 600 begins at operation 602, angle-modulating a digitally-controlled oscillator (e.g., DCO 104) with a digitized baseband signal (e.g., N.sub.mod). Method 600 continues at operation 604, comparing zero crossings of the reference signal to zero crossings of a frequency-divided, angle-modulated local RF signal in a fractional-N, delta-sigma phase/frequency detector, to generate a difference signal comprising a modulation component (e.g., the digitized baseband signal, N.sub.mod 121) and an error component (e.g., the fractional control sequence 122). Next, method 600 continues at operation 606, generating a digital frequency error (e.g., Δf.sub.e) from a difference (e.g., in adder 123) between the fractional control sequence and a fractional control number (e.g., N.sub.frac). Method 600 continues at operation 608: accumulating the digital frequency error (e.g., in accumulator 124) to generate a digital phase error Δϕ.sub.e; at operation 610: selecting the digital phase error with a digital loop filter (e.g., DLF 125); at operation 612: where the local RF source is a digitally-controlled oscillator (DCO), phase-locking the local RF signal to the reference signal by tuning the DCO with the digital phase error; and at operation 614: encoding a stream of transmit (TX) data bits in a digital modulator (e.g., 127) to generate the digital baseband signal (e.g., N.sub.mod).

(30) The preceding description sets forth numerous specific details such as examples of specific systems, components, methods, and so forth, in order to provide a thorough understanding of several examples in the present disclosure. It will be apparent to one skilled in the art, however, that at least some examples of the present disclosure may be practiced without these specific details. In other instances, well-known components or methods are not described in detail or are presented in simple block diagram form in order to avoid unnecessarily obscuring the present disclosure. Thus, the specific details set forth are merely exemplary. Particular examples may vary from these exemplary details and still be contemplated to be within the scope of the present disclosure.

(31) Any reference throughout this specification to “one example” or “an example” means that a particular feature, structure, or characteristic described in connection with the examples are included in at least one example. Therefore, the appearances of the phrase “in one example” or “in an example” in various places throughout this specification are not necessarily all referring to the same example.

(32) Although the operations of the methods herein are shown and described in a particular order, the order of the operations of each method may be altered so that certain operations may be performed in an inverse order or so that certain operation may be performed, at least in part, concurrently with other operations. Instructions or sub-operations of distinct operations may be performed in an intermittent or alternating manner.

(33) The above description of illustrated examples of the invention, including what is described in the Abstract, is not intended to be exhaustive or to limit the invention to the precise forms disclosed. While specific implementations of, and examples for, the invention are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the invention, as those skilled in the relevant art will recognize. The words “example” or “exemplary” are used herein to mean serving as an example, instance, or illustration. Any aspect or design described herein as “example” or “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects or designs. Rather, use of the words “example” or “exemplary” is intended to present concepts in a concrete fashion. As used in this application, the term “or” is intended to mean an inclusive “or” rather than an exclusive “or”. That is, unless specified otherwise, or clear from context, “X includes A or B” is intended to mean any of the natural inclusive permutations. That is, if X includes A; X includes B; or X includes both A and B, then “X includes A or B” is satisfied under any of the foregoing instances. In addition, the articles “a” and “an” as used in this application and the appended claims should generally be construed to mean “one or more” unless specified otherwise or clear from context to be directed to a singular form. As used in this application, the terms “coupled to” or “coupled with” in the context of connected components or systems, includes both directly coupled components or systems, and components or systems that are indirectly coupled through other components, systems of interfaces.