Preparation Method of GaN Field Effect Transistor Based on Diamond Substrate

Abstract

The disclosure provides a preparation method of GaN field effect transistor based on diamond substrate, and relates to the technical field of semiconductor manufacturing. The method includes the following steps: preparing a GaN heterojunction layer on the front-side of a SiC substrate; thinning the SiC substrate; etching the SiC substrate; growing a diamond layer; removing a sacrificial layer and the diamond layer on the sacrificial layer; preparing a source electrode, a drain electrode and a gate electrode on the front surface of the GaN heterojunction layer; etching the SiC substrate and the GaN heterojunction layer to form a source through hole communicated with the source electrode; and removing the through hole mask layer, and preparing back grounding metal to complete the preparation of the diamond substrate GaN transistor device.

Claims

1. A preparation method of a gallium nitride (GaN) field effect transistor, comprising following steps: step 1, preparing a GaN heterojunction layer on a front-side of a silicon carbide (SiC) substrate; step 2, thinning a backside of the SiC substrate to obtain a thinned SiC substrate; step 3, growing a sacrificial layer on a backside of the thinned SiC substrate; step 4, coating a photoresist on the sacrificial layer; step 5, exposing and developing the photoresist to form a metal mask area graphics on the sacrificial layer; step 6, evaporating and stripping a metal on the metal mask area graphics to form a metal mask layer on the metal mask area graphics; step 7, removing a part of the sacrificial layer that is outside an area covered by the metal mask layer to form a groove area on the sacrificial layer and to obtain a remaining sacrificial layer; step 8, removing the metal mask layer using a wet process; step 9, using the remaining sacrificial layer as a mask, and etching the thinned SiC substrate such that the groove area extends to a backside of the GaN heterojunction layer and to obtain a remaining SiC substrate; step 10, growing a diamond layer on the remaining sacrificial layer and the backside of the GaN heterojunction layer; step 11, removing a part of the diamond layer that covers the remaining sacrificial layer using the wet process to obtain a remaining diamond layer, and removing the remaining sacrificial layer using the wet process; step 12, preparing a source electrode, a drain electrode and a gate electrode on a front-side of the GaN heterojunction layer; step 13, preparing a through hole mask layer on the remaining diamond layer and the remaining SiC substrate; step 14, using the through hole mask layer as a mask, and etching the remaining SiC substrate and the GaN heterojunction layer to form a source through hole that is in communication with the source electrode; and step 15, removing the through hole mask layer, and preparing a back grounding metal on the remaining diamond layer and the remaining SiC substrate, to complete preparation of the GaN field effect transistor, the back grounding metal being in communication with the source through hole.

2. The method according to claim 1, wherein in the step 1, the GaN heterojunction layer comprises a buffer layer, a channel layer and a barrier layer.

3. The method according to claim 2, wherein in the step 1, the barrier layer is an AlGaN layer, 0<x≤1; or the barrier layer is an In.sub.xAlN layer, 0<x≤1; or the barrier layer is an In.sub.xAl.sub.yGaN layer, 0≤x<1, 0<y≤1, 0≤x+y≤1.

4. The method according to claim 2, wherein in the step 1, the buffer layer is an AlN layer, and the channel layer is a GaN layer.

5. The method according to claim 1, wherein in the step 1, the GaN heterojunction layer comprises a buffer layer, a channel layer, an insertion layer, a barrier layer and a cap layer, wherein the insertion layer is an AlN layer with a thickness of 1 nm˜2 nm, and the cap layer is a GaN layer with a thickness of 2 nm˜4 nm.

6. The method according to claim 5, wherein in the step 1, the barrier layer is an Al.sub.xGaN layer, 0<x≤1; or the barrier layer is an In.sub.xAlN layer, 0<x<1; or the barrier layer is an In.sub.xAl.sub.yGaN layer, 0≤x<1, 0<y≤1, 0≤x+y≤1.

7. The method according to claim 5, wherein in the step 1, the buffer layer is an AlN layer, and the channel layer is a GaN layer.

8. The method according to claim 1, wherein in the step 2, a thickness of the SiC substrate is greater than 300 μm, and a thickness of the thinned SiC substrate is 1 μm˜100 μm.

9. The method according to claim 1, wherein in the step 3, the sacrificial layer is a SiO.sub.2 layer.

10. The method according to claim 1, wherein in the step 10, a thickness of the diamond layer is smaller than a sum of a thicknesses of the remaining sacrificial layer and a thicknesses of the thinned SiC substrate by at least 1 μm.

11. The method according to claim 1, wherein in the step 13, the through hole mask layer is a SiO.sub.2 mask layer or a metal Ni mask layer.

12. The method according to claim 1, wherein in the step 15, a metalized through hole and the back grounding metal are formed using magnetron sputtering or electroplating.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the embodiments or the drawings used in the prior art description will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings can be obtained from these drawings without involving any inventive effort for a person skilled in the art.

[0034] FIG. 1 is a schematic structural diagram of a preparation method of GaN field effect transistor based on diamond substrate according to an embodiment of the disclosure.

[0035] In the FIG. 1: 1. SiC substrate; 2. buffer layer; 3. channel layer; 4. insertion layer; 5. barrier layer; 6. cap layer; 7. sacrificial layer; 8. photoresist; 9. metal mask layer; 10. diamond layer; 11. source electrode; 12. drain electrode; 13. gate electrode; 14. through hole mask layer; 15. source through hole; 16. back grounding metal; 17. metalized through hole.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

[0036] In order to make the technical problems to be solved, technical solutions and beneficial effects by the present application more clear, the present application will be further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application, but not to limit the present application.

[0037] Referring to FIG. 1, an embodiment preparation method of GaN field effect transistor based on diamond substrate provided by the application is described. The preparation method of GaN field effect transistor based on diamond substrate includes the following steps 1-15.

[0038] Step 1, with reference to FIG. 1(a), preparing a GaN heterojunction layer on a front-side of a SiC substrate 1.

[0039] Step 2, with reference to FIG. 1(b), thinning the SiC substrate 1; this step may thin a backside of the SiC substrate 1 to obtain a thinned SiC substrate 1.

[0040] Step 3, with reference to FIG. 1(c), growing a sacrificial layer 7 on a backside of the thinned SiC substrate 1.

[0041] Step 4, with reference to FIG. 1(d), coating a photoresist 8 on the sacrificial layer 7.

[0042] Step 5, with reference to FIG. 1(e), exposing and developing the photoresist 8 to form a metal mask area graphics on the sacrificial layer 7. It is apparent to those of ordinary skill in the art, that the metal mask area graphics is a pattern obtained by removing a part of the photoresist 8 after exposing and developing of the photoresist 8. This step may result in a remaining photoresist 8.

[0043] Step 6, with reference to FIG. 1(f), evaporating and stripping a metal on the metal mask area graphics to form a metal mask layer 9 on the metal mask area graphics. It is apparent to those of ordinary skill in the art, that by using the metal mask area graphics as a mask, and evaporating the required metal, while removing the remaining photoresist 8, the metal on the remaining photoresist 8 is also stripped off, leaving only the metal that is in direct contact with the sacrificial layer 7.

[0044] Step 7, with reference to FIG. 1(g), removing a part of the sacrificial layer 7 that is outside an area covered by the metal mask layer 9 to form a groove area on the sacrificial layer 7 and to obtain a remaining sacrificial layer 7.

[0045] Step 8, with reference to FIG. 1(h), removing the metal mask layer 9 using a wet process. It is apparent to those of ordinary skill in the art that the wet process refers to removal by wet etching. The wet etching is an etching method, which is a technique of immersing the structure to be etched in an etching solution for etching.

[0046] Step 9, with reference to FIG. 1(i), using the remaining sacrificial layer 7 as a mask, and etching the thinned SiC substrate 1 such that the groove area extends to a backside of the GaN heterojunction layer and to obtain a remaining SiC substrate 1. The remaining sacrificial layer 7 is obtained after removing the sacrificial layer 7 outside the area covered by the metal mask layer 9 on the original sacrificial layer 7 in the step 7.

[0047] Step 10, with reference to FIG. 1(j), growing a diamond layer 10 on the remaining sacrificial layer 7 and the backside of the GaN heterojunction layer.

[0048] Step 11, with reference to FIG. 1(k), removing a part of the diamond layer 10 that covers the remaining sacrificial layer 7 using the wet process to obtain a remaining diamond layer 10, and removing the remaining sacrificial layer 7 using the wet process. It is apparent to those of ordinary skill in the art that the wet process refers to removal by wet etching as described above.

[0049] Step 12, with reference to FIG. 1(l), preparing (or making, or creating) a source electrode 11, a drain electrode 13 and a gate electrode 12 on a front-side of the GaN heterojunction layer.

[0050] Step 13, with reference to FIG. 1(m), preparing (or making, or creating) a through hole mask layer 14 on the remaining diamond layer 10 and the remaining SiC substrate 1. The remaining SiC substrate 1 is obtained after etching on the thinned SiC substrate 1 in the step 9.

[0051] Step 14, with reference to FIG. 1(n), using the through hole mask layer 14 as a mask, and etching the remaining SiC substrate 1 and the GaN heterojunction layer to form a source through hole 15 that is in communication with the source electrode 11.

[0052] Step 15, with reference to FIG. 1(o), removing the through hole mask layer 14, and preparing a back grounding metal 16 on the remaining diamond layer 10 and on the remaining SiC substrate 1, to complete preparation of the GaN field effect transistor based on the diamond substrate, the back grounding metal being in communication with the source through hole 15. The back grounding metal 16 is formed on the backside of the substrate and is used for connecting with the source electrode to realize the grounding effect of the source electrode 11. The diamond substrate is formed by the SiC substrate 1 and diamond layer 10.

[0053] It can be understood that in the above steps, the operation object of the latter step is the operation object obtained by executing the previous corresponding step.

[0054] It is apparent to those of ordinary skill in the art that the front-side and the backside are two opposite sides. As an example, if one side of a layer or substrate is used as the front-side, and then the other side (opposite to the front-side) of the layer or substrate is used as the backside. The direction represented by the front-side of a layer is generally used to prepare the source electrode, the gate electrode and the drain electrode.

[0055] Compared with the prior art, the preparation method of GaN field effect transistor based on diamond substrate provided by the present application, by retaining the SiC substrate in the through hole area and replacing the difficult diamond laser through hole process, the back through hole grounding on GaN heterojunction device based on diamond substrate is realized, which is convenient for the preparation of GaN HEMT device based on diamond substrate; and meanwhile, on the GaN HEMT wafer based on SiC substrate, SiC is only removed in a small area on the backside, which avoids large deformation of the material and provides convenience for the subsequent front-side process preparation.

[0056] In some possible embodiments, with reference to FIG. 1(a), in the step 1, the GaN heterojunction layer includes a buffer layer 2, a channel layer 3 and a barrier layer 5.

[0057] In other possible embodiments, with reference to FIG. 1(a), in the step 1, the GaN heterojunction layer includes a buffer layer 2, a channel layer 3, an insertion layer 4, a barrier layer 5 and a cap layer 6, wherein the insertion layer 4 is an AlN (aluminum nitride) layer with a thickness of 1 nm˜2 nm, and the cap layer 6 is a GaN layer with a thickness of 2 nm˜4 nm. Understandably, the numerical range of the insertion layer 4 and the cap layer 6 refers to the thickness and may be any value within the above numerical range. Of course, the GaN heterojunction layer may also include other layer structures, and the layer structure thickness may also be in other ranges, not limited to this.

[0058] In one embodiment, with reference to FIG. 1(a), in the step 1, the barrier layer 5 is an Al.sub.xGaN (aluminum gallium nitride) layer, 0<x≤1, and the preferred range is 0.15≤x≤0.4; or the barrier layer 5 is an In.sub.xAlN (indium aluminum nitride) layer, 0<x≤1, and the preferred range is 0.13≤x≤0.25; or the barrier layer 5 is an In.sub.xAl.sub.yGaN (indium aluminum gallium nitride) layer, 0≤x<1, 0<y≤1, 0≤x+y≤1. Understandably, the value of the barrier layer 5 may be any value within the above numerical range. Of course, the barrier layer 5 may also be other materials and other values.

[0059] In one embodiment, with reference to FIG. 1(a), in the step 1, the buffer layer 2 is an AlN layer, and the channel layer 3 is a GaN layer.

[0060] In some possible embodiments, in the step 2, with reference to FIG. 1(b), a thickness of the SiC substrate 1 is greater than 300 μm, and a thickness of the thinned SiC substrate 1 is 1 μm˜100 μm. Understandably, the thickness of the SiC substrate 1 greater than 300 μm refers to the initial thickness of the original, unthinned SiC substrate 1. The above thickness may be any value within the above numerical range. Of course, it may also be other values.

[0061] In some possible embodiments, in the step 3, with reference to FIG. 1(c), the sacrificial layer 7 is a SiO.sub.2 layer. The sacrificial layer 7 is the final structure to be removed. When depositing the diamond layer 10, the diamond will evenly cover the surface of the SiC substrate 1. If the diamond is directly deposited on the SiC substrate 1, it will be difficult to remove the diamond at the hole forming position. The purpose of setting the sacrificial layer 7 is to remove the diamond layer 10 deposited on the sacrificial layer 7 at the hole forming position. Thus, the diamond layer 10 deposited on the corresponding hole position of the SiC substrate 1 may be removed, so that the SiC substrate 1 may be removed using dry etching or wet etching to form a hole.

[0062] In some possible embodiments, in the step 7, with reference to FIG. 1(g), the sacrificial layer 7 outside the area covered by the metal mask layer 9 is removed using dry etching, or dry etching combined with wet etching.

[0063] In some possible embodiments, in the step 9, with reference to FIG. 1(i), this technology uses ICP (Inductively Coupled Plasma Etching) to etch part of SiC substrate 1. The control accuracy of ICP is higher than that of mechanical grinding process that completely removes the backside SiC substrate 1. It is easy to form fragments when removing SiC substrate 1 using mechanical grinding process, and the time to completely remove the SiC substrate 1 is not easy to control.

[0064] In some possible embodiments, in the step 10, with reference to FIG. 1(j), a thickness of the diamond layer 10 is smaller than a sum of a thicknesses of the remaining sacrificial layer 7 and a thicknesses of the thinned SiC substrate 1 by at least 1 μm. For example, the thickness of the diamond layer 10 may be lower than the thickness of the thinned SiC substrate 1 or higher than the thickness of the thinned SiC substrate 1, but less than the sum of the thickness of the remaining sacrificial layer 7 and the thinned SiC substrate 1, so as to remove the diamond layer 10 located on the sacrificial layer 7 and to remove the sacrificial layer 7. Of course, the thickness of the diamond layer 10 may also be other values.

[0065] In some possible embodiments, in the step 12, with reference to FIG. 1(l), the prepared source electrode 11, drain electrode 13 and gate electrode 12 are the most basic structures of the transistor device, and may also be optimized based on the passivation layer and the field plate structure based on the structure. The passivation layer and field plate structure may also be optimized based on the basic structures.

[0066] In some possible embodiments, in the step 13, with reference to FIG. 1(m), the through hole mask layer 14 is a SiO.sub.2 mask layer or a metal Ni mask layer. Wherein, the preparation process of the through hole mask layer 14 is similar to that of the metal mask layer 9, and will not be repeated here. The growth method of the SiO.sub.2 mask layer may be PECVD (Plasma Enhanced Chemical Vapor Deposition) or LPCVD (Low Pressure Chemical Vapor Deposition), and the thickness of the SiO.sub.2 mask layer ranges from 10 um to 1000 um. The preparation method of the metal Ni mask layer may be electron beam evaporation, magnetron sputtering evaporation or electroplating. The area of the source through hole 15 is exposed by photolithography, and then the SiO.sub.2 mask layer and the metal Ni mask layer are etched away using ICP to prepare for etching the SiC substrate 1 to form the source through hole 15.

[0067] In some possible embodiments, in the step 14, the SiC substrate 1 and the GaN heterojunction layer are etched by ICP to form a source through hole 15.

[0068] In some possible embodiments, in the step 15, with reference to FIG. 1(o), a metalized through hole 17 and the back grounding metal 16 are formed using magnetron sputtering or electroplating.

[0069] The above mentioned embodiments are only preferred embodiments of this application, but not to limit this disclosure. Any modification, equivalent replacement and improvement made within the spirit and principles of this application should be included in the scope of protection of this application.