METHOD OF MAKING A SILICON ON INSULATOR WAFER

Abstract

A process for making silicon on insulator wafer by bond and etch back—BESOI. A boron etch stop is formed by BF2+ ion implantation followed by solid phase epitaxy—SPE. Fluorine getters metals for OISF immunity of the final wafer. SPE activates boron above solubility limit thus facilitates high etch selectivity. Future cap silicon film is epitaxially grown over the boron etch stop at temperature that limits boron diffusion and boron deactivation. High temperature hydrogen bake step in epitaxy is replaced with Siconi of similar low temperature process. Buried oxide is thermally grown from portion of cap silicon layer at temperature limiting Boron diffusion and deactivation. Thus, SOI wafer design is the same as in layer transfer process—bonding interface is at the bottom interface of BOX; properties of final SOI wafer are equal to SOI made by layer transfer process—including cap silicon layer thickness variation, and OISF defect count. Advantage over the layer transfer—this process does not require non-standard equipment. Standard processing tool set readily available at semiconductor foundries is sufficient to run this process. Foundries can use this process for in house SOI wafer manufacturing.

Claims

1. A method for making silicon on insulator wafers comprising; preparation of device and handle wafers where said device wafer comprises a sacrificial starting wafer covered with a stack of layers, said stack comprises etch stop layers, future cap silicon layer, and future BOX layer, said etch stop layers comprises 1.sup.st and 2.sup.nd etch stop layers where said 1.sup.st etch stop layer comprises low doped silicon epi layer over heavily doped said sacrificial bulk wafer, said 2.sup.nd etch stop layer comprises heavily boron doped layer, bonding of said device wafer stack to said handle wafer, preparing bonded wafer assembly for thinning by anneal step, thinning of said device wafer stack by complete removal of said starting wafer by sequence of grinding and HNA etching, and removal of etch stop layers until said cap silicon film exposed characterized in that said 2.sup.nd etch stop layer is formed by a sequence of ion implantation and solid phase epitaxy, and said ion implantation uses Boron and Fluorine containing species, and said Boron concentration in said 2.sup.nd etch stop layer is equal or exceeds 1E20 cm-3, and said concentration of Boron is achieved by solid phase epitaxy of layer amorphized by said ion implantation said cap silicon layer is grown over said 2.sup.nd etch stop layer by epitaxy after surface preparation at low temperature.

2. The method of claim 1, where said ion implantation comprises implanting FB.sub.2+ ion species.

3. The method of claim 2, where said implantation dose is chosen to cause amorphization of silicon from surface to a depth defined by implant energy.

4. The method of claim 3, where energy of said ions is in a range from 20 to 100 keV.

5. The method of claim 3, where dose of said ions is in a range from 5E.sup.14 to 5E.sup.15 cm.sup.−2.

6. The method of claim 2, where said boron etch stop layer is formed by electrical activation of implanted boron with solid phase epitaxy.

7. The method of claim 6, where where said solid phase epitaxy is performed by <1° C./minute ramp up anneal starting from 450° C. till 600° C.

8. The method of claim 1, where said cap silicon layer is grown over said 2.sup.nd etch stop layer by epitaxy after surface preparation for epi at temperature below 600° C.

9. The method of claim 8, where said epitaxy of the cap silicon layer is performed at temperature equal or below 800° C.

10. The method of claim 9, where said buried oxide layer is grown from portion of said cap silicon by thermal oxidation at temperature equal or below 800° C.

11. The method of claim 1, where gettering anneal at 350-750° C. is performed after grinding and HNA etching steps of said bonded device stack and handle wafers.

Description

BRIEF DESCRIPTION OF THE DRAWING

[0054] FIG. 1 illustrates a schematic process flow of BESOI process due to the invention.

[0055] FIG. 2 compares art process with SiGe etch stop (left) to inventive process (right).

[0056] FIG. 3 further compares art process with SiGe etch stop to inventive process

[0057] FIG. 4 compares art process with Si:B etch stop to inventive process

[0058] FIG. 5 further compares art process with Si:B etch stop to inventive process

[0059] FIG. 6 shows as-implanted boron profile after exemplary implant recipe BF2+ at 55 keV, 9E14 cm-2.

[0060] FIG. 7 illustrates concept of SPE process.

[0061] FIG. 8 schematically show device and handle wafer stacks before wafer bonding step for RF SOI.

[0062] FIG. 9 schematically show a device wafer stack obtained by inventive process.

[0063] FIG. 10 illustrates boron profile widening for exemplary 750 C oxidation used to manufacture device wafer stack

[0064] FIG. 11 illustrates boron profile widening for exemplary 800 C oxidation used to manufacture device wafer stack.

DETAILED DESCRIPTION OF THE INVENTION

1.SUP.st .Preferred Embodiment

[0065] First, a seed wafer is prepared. It can be called also donor wafer, or device wafer. Starting wafer is, for example an epi wafer 300 mm size having p++ bulk and 1 to 5-micron thick p− epi. Wafers with 5-micron epi are readily available from all major wafer manufacturers as they are used in mainstream CMOS chip manufacturing. The 5-micron thickness is acceptable, but not optimal for the inventive process. An optimal 1-2-micron epi can be made either on special order or grown in-house. Referring to FIG. 1, step 1, BF2+ ion implantation is performed into the p− epi. An exemplary recipe—implant at 55 keV, 9E14 cm-2—satisfies all the conditions needed: (1) it amorphizes Si from surface to about 100 nm, (2) deliver proper amount of Boron to form high selectivity etch stop, (3) deliver Fluorine—to exclude OISF formation during chip fabrication. For the BESOI process, an obvious method to prevent OISF—by lowering of metal contamination—is not applicable—as there are BEOL steps in the process—grinding of sacrificial wafer, HNA etching till 1.sup.st etch stop, etc. In this invention the metal contamination problem is solved by an metal gettering by layer that is heavy doped Boron and Fluorine. This provides OISF immunity.

[0066] An exemplary recipe 55 keV, 9E14 cm-2 can be done at medium or high current implanters available at fabs, for example AMAT (Varian) HC implanter. In this recipe Boron has energy 12.35 keV. FIG. 6 shows an as-implanted boron distribution: —concentration for etch stop->2E19 cm-3 is from 12 till 78 nm, peak concentration 9.6E19 provides high enough selectivity >100. Optionally the wafer can be oxidized—10 nm SiO2—before implant—to avoid channeling, and for easy post implant clean by oxide strip.

[0067] Energy range for BF2+ implant—10-100 keV. At lower energy much higher dose is needed to exceed amorphization threshold. At higher energy boron peak is too wide and deep thus thin SOI is more difficult to form.

[0068] Dose range for BF2+ implant—5E14-5E15 cm-2. At lower doses amorphization does not happen—thus no SPE, no B activation, no etch stop. At higher doses F and B clusters are formed, further causing defects in cap silicon.

[0069] Referring to FIG. 1, step 2, solid phase epitaxy (SPE) is performed. SPE is a special mode of recrystallization of amorphous layer if it is in contact with a crystalline lattice, see FIG. 7 for illustration. Amorphous Si itself is stable till 600 C. Above 600, crystals nucleate in bulk of a-Si and grow until all becomes crystal grains (poly crystal). At temperatures 450-580 C there is no nucleation in bulk of a-Si. Amorphous Si only crystallize at a/c interface inheriting proper lattice orientation and lattice constant. The a/c interface moves till all a-Si becomes single crystal.

[0070] Surprisingly, despite almost any ion implanter has BF2+ capability, BF2+ followed by SPE is still not well studied, see Mirabella, S., G. Impellizzeri, E. Bruno, L. Romano, M. G. Grimaldi, F. Priolo, E. Napolitani, and A. Camera. “Fluorine segregation and incorporation during solid-phase epitaxy of Si.” Applied Physics Letters 86, no. 12 (2005): 121905. Even though, fluorine redistribution upon SPE has bright anomalous feature—heavy segregation toward surface, still no much studies beyond University of Padova, Italy team. In this application, the fluorine segregation toward surface is very advantageous—we get (1) high F concentrations near bottom of cap Si in final SOI wafer—this gives OISF suppression as F prevents metal precipitates to evolve into OISF, (2) high F content in BOX—as BOX is grown here. —all excess of fluorine “self-removes”—leave wafer after SPE. Thus, only less than few % of as-implanted fluorine is left in silicon. Upon next anneal steps in BESOI processing, this fluorine redistributes by diffusion and eventually binds to existing defects in cap Si and Si-BOX interface thus passivating them.

[0071] So far, only one commercially viable application of BF2/SPE is known—making shallow source/drain contacts in MOSFETs—Kanemoto, Kei, Akira Nakada, and Tadahiro Ohmi. “Minimization of BF2+-Implantation Dose to Reduce the Annealing Time for Ultra-Shallow Source/Drain Junction Formation below 600° C.” Japanese journal of applied physics 37, no. 3S (1998): 1166. To the best of our knowledge, it was no attempts to use BF2-then-SPE to make BESOI in the art.

[0072] The higher temperature, the higher SPE rate. We need to SPE 50-100 nm of layer amorphized by implantation in reasonable time range—10-100 minutes. 100 nm of pure Si will SPE in ˜10s at 580 C and in ˜10 min at 450 C. B-doped Si SPE rate is roughly 10× faster than pure. F-doped Si SPE roughly 100× slower than pure. Finally, B+F doped Si SPE roughly 10× slower than pure. Therefore, the temperature range for SPE is 450-580 C. At lower temperatures SPE is too slow. Above 580 C SPE regrown layer contains defects. Optimal temperature/time is around 550/30 min. This BF2/SPE process is somehow like making shallow source/drain extensions which also calls for amorphization/SPE to get electrically active Boron well above solubility limit.

[0073] An important feature of SPE—activation well above solubility limit—is used here. SPE is performed at low temperature<600 C, thus it is an ideal to prevent undesirable Boron diffusion. Notice, Si:B:F layer behavior was neither well studied/understood, nor used to improve BESOI process.

[0074] There were attempts in the art as to make BESOI wafer using BF2 ion implantation—see: Desmond, Cynthia A., Charles E. Hunt, and Shari N. Farrens. “The Effects of Process-Induced Defects on the Chemical Selectivity of Highly Doped Boron Etch Stops in Silicon.” Journal of The Electrochemical Society 141, no. 1 (1994): 178-184. However, they used RTA (rapid thermal anneal), not SPE. Thus, no high boron activation, then no good etch selectivity, heavy boron out diffusion, and eventually low quality BESOI wafer.

[0075] Referring to FIG. 1 step 3, the wafer is loaded into epitaxy tool—to grow cap silicon film over the boron etch stop layer. Regular epi cannot be used—it starts from hydrogen bake step at >1100 C. At this temperature boron diffuses and B concentration in ion implant peak drops. If it drops below 2E19 cm-3, the layer will not serve as an etch stop anymore. Also, above 800 C “over-solubility-limit” boron de-activates, thus does not contribute to the etch selectivity. Therefore, traditional hydrogen bake cannot be used here. Instead, low temperature process is used to prepare surface for epitaxy—i.e., remove native oxide from surface. If AMAT tool is used, the surface preparation is done in Siconi chamber—before wafer moves into epi chamber. If ASM Epsilon or Intrepid tool is used, the surface preparation is in Previum chamber. Even though Siconi and Previum are different processes, for our purposes important is only that they both capable to remove native oxide from surface at low temperature, thus enabling epitaxy.

[0076] Referring to FIG. 1, step 4, regular silicon epitaxy is performed at temperature 800 C or below. 800 C limit is for the same reasons—limit boron diffusion and prevent boron deactivation. As cap silicon is typically thinner than 100 nm, this limitation does not lower the throughput. Regular deposition from trichlororosilane takes about 100 s.

[0077] All other steps of BESOI wafer manufacturing—bonding and thinning—are the same as in a regular process known in the art, therefore these steps are not described here.

2nd Preferred Embodiment

[0078] This embodiment describes how to enable proximity metal gettering at final stages of SOI wafer fabrication. Thus, metal contamination from all process steps that are before the final thinning does not cause OISF and next GOI failure in the chips. For BESOI manufacturing it means that BEOL lines can be used, except 3 final process steps—boron etch-stop removal, bond finalizing, and cap silicon layer thickness adjustment.

[0079] An issue inherent to all SOI wafers regardless of manufacturing method (SIMOX, BESOI or layer transfer) is that BOX precludes metal gettering by handle wafer from cap Si. Therefore, BESOI wafers made with the processes known in the art are extremely sensitive to metal contamination. This disclosure enables gettering in BESOI thus suppressing OISFs, improve GOI and yield of final chips.

[0080] Here, the Si:B:F layer serves as the getter instead of the substrate. In Si, almost any heavy doped region has gettering activity, B+F doped is not an exception. Thus, Si:B:F serves 3 functions—template for cap Si epi, etch stop, and getter. The metal gettering is performed by annealing of SOI wafer after selective etch away of p− layer and before selective etch of Si:B:F layer. Anneal is in temperature range—350-750 C. At temperatures below 350 C gettering loses efficiency (due to lowering diffusivity of metals in Si with temperature). At temperatures above 750 C boron start diffusing into cap Si layer. One skilled in the art can choose the proper annealing temperature to achieve efficient gettering using, for example, using a textbook by Geng, Hwaiyu. Semiconductor manufacturing handbook. 2.sup.nd edition, 2017, chapter 3.4.2.

[0081] F in Si is also known as an efficient metal getter, thus BF2 implant maximizes gettering efficiency. The etch stop Si:B:F layer is sacrificial, thus all gettered metals are removed together with the sacrificial layer.

3.SUP.rd .Preferred Embodiment

[0082] In this embodiment an oxidation step added at the end of making the device wafer stack.

[0083] This way the design of the final wafer changes—bonding interface is at BOX bottom, not on top. And, BESOI turns the same design as layer transfer wafer. Accordingly, all advantages of this design (1) BOX—cap Si interface has automatically zero particles (2) less flakes and other bonding-related defects, (3) lower interface state density at BOX—cap Si interface=better electrical performance of final chips.

[0084] During oxidation some boron diffusion from p+ layer into cap Si will happen. Still, there is a process window where the B diffusion is acceptably low—at 750-800 C. Boron diffuses by vacancy jump mechanism. Therefore, the diffusion coefficient drops exponentially with temperature: 3E-13 at 1100 C and 5E-17 at 800 C; Lowering temperature by 300 C—from 1100 down to 800 C—results in 4 orders of magnitude drop of diffusion coefficient—see FIG. 10a—from Jones, Scotten W. “Diffusion in silicon.” IC Knowledge LLC (2008): p. 25. Therefore, lowering temperature is extremely efficient way to control and minimize B diffusion.

[0085] Typical BOX thickness is 200 nm. At 750 C it needs 13 hours to grow, at 800 C—it needs 6 hours (reasonable), see FIG. 10, FIG. 11. Another reason to limit temperature—risk of B deactivation (remember, we have B well over solid solubility limit). The deactivation means dropping etch selectivity, which is undesirable. At 800 C and below there is no any significant deactivation. Also, the universal trend (i.e., Moore's law) in semiconductor industry is size shrinking. Thus, for next generations of SOI wafers—having thinner BOX around 20 nm, 750 C oxidation will take much shorter time.

[0086] Referring to FIG. 10—an example of calculations: Oxidation temperature 750 C. To get final 80 nm cap Si SOI—add 88 nm—to be consumed by oxidation and add 28 nm to compensate B diffusion into cap Si during oxidation, add 4 nm to compensate B diffusion while epi of cap Si. Total epi needed: 80+88+28+4=200 nm.

[0087] Referring to FIG. 11—if oxidation temperature is 800 C. To get final 80 nm cap Si SOI—add 88 nm—to be consumed by oxidation, add 60 nm to compensate B diffusion into cap Si during oxidation, add 4 nm to compensate B diffusion while epi of cap Si. Total epi 80+88+60+4=232 nm.

4.SUP.th .Preferred Embodiment

[0088] This embodiment is for making RF SOI. RF SOI wafer has an additional layer—polysilicon. BESOI process known in the art grow BOX from top of handle wafer stack. For RF SOI case, there is poly layer on the top of the handle stack. Thus, in known processes, BOX is made by oxidizing polysilicon. This inevitably forms very rough interface between poly and BOX.

[0089] In the inventive process, BOX is grown on device wafer stack, not on handle stack. Therefore, no rough BOX/poly interface in final SOI wafer. FIG. 8 illustrates device wafer stack and handle wafer stack before bonding and thinning.

5.SUP.th .Preferred Embodiment

[0090] In this embodiment, 2 separate ion implants done instead of single BF2+ or single BF3+ implant. One is boron implant; another is fluorine implant.

[0091] Boron implant is at 5 to 20 keV—to get proper dopant location. However, boron is a light ion, thus it does not cause amorphization if implantation done at room temperature. B+ must be implanted into wafer cooled below about −50 C to achieve amorphization. End stations with cooling are available on many implanters, thus no technical challenge here. Alternatively, F+ implant can be used for amorphization. Though F+ ion beam current is typically significantly lower than for BF2+ specie, so throughput will suffer. Advantages of separate B and F implants is that energy and dose of each specie can be independently optimized achieving high etch selectivity by Boron implant/SPE optimization, and efficient OISF suppression as well as lowering of wafer bonding temperature by F implant optimization. With separate F implant, fluorine can be implanted later, after BOX grown on device stack wafer, right before bonding. This allow F placement at future BOX/cap Si interface, thus maximizing F efficiency for suppression of OISF. This option is described in co-pending application by author.

[0092] In Silicon lattice, Boron has vacancy diffusion mechanism, while Fluorine has interstitial diffusion. Therefore, Fluorine diffusion is faster and proceeds at lower temperatures compared to Boron. To keep Fluorine from out diffusion and get maximum of its positive effects on OISF reduction, and on wafer bonding, all the following is useful (1) implant it later in the process flow, (2) use low 550 C or lower processing temperatures, (3) have oxide on surface before implant to capture F.