Superconducting nanowire single photon detector and method of fabrication thereof

Abstract

A superconductor device is manufactured by depositing a barrier layer over a substrate including silicon, the barrier layer including silicon and nitrogen; depositing a seed layer for a superconductor layer over the barrier layer, the seed layer including aluminum and nitrogen; depositing the superconductor layer over the seed layer, the superconductor layer including a layer of a superconductor material, the barrier layer serving as an oxidation barrier between the layer superconductor material and the substrate; and depositing a silicon cap layer over the superconductor layer. In some embodiments, the superconductor device includes a waveguide and a metal contact at a sufficient distance from the waveguide to prevent optical coupling between the metal contact and the waveguide.

Claims

1. A method of manufacturing a superconductor device, comprising: depositing a barrier layer over a substrate including silicon, the barrier layer including silicon and nitrogen; depositing a seed layer for a superconductor layer over the barrier layer, the seed layer including aluminum and nitrogen; depositing the superconductor layer over the seed layer, the superconductor layer including a layer of a superconductor material, the barrier layer serving as an oxidation barrier between the layer of the superconductor material and the substrate; depositing a silicon cap layer over the superconductor layer; patterning the silicon cap layer, the superconductor layer, the seed layer and the barrier layer to form a multilayer stack; after forming the multilayer stack: depositing a layer of protective material over the multilayer stack; anisotropically etching the layer of protective material to form a plurality of sidewalls on sides of the multilayer stack; and removing oxygen from the superconductor layer in an annealing process.

2. The method of claim 1, further comprising obtaining the substrate, wherein obtaining the substrate comprises: patterning a semiconductor layer of a semiconductor-on-insulator wafer to form a waveguide; depositing a dielectric layer over the waveguide; and planarizing the dielectric layer.

3. A method of manufacturing a superconductor device, comprising: depositing a barrier layer over a substrate including silicon, the barrier layer including silicon and nitrogen; depositing a seed layer for a superconductor layer over the barrier layer, the seed layer including aluminum and nitrogen; depositing the superconductor layer over the seed layer, the superconductor layer including a layer of a superconductor material, the barrier layer serving as an oxidation barrier between the layer of the superconductor material and the substrate; depositing a silicon cap layer over the superconductor layer; patterning the silicon cap layer, the superconductor layer, the seed layer and the barrier layer to form a multilayer stack; after forming the multilayer stack: depositing a dielectric layer; and forming an electrical contact through the dielectric layer to a portion of the superconductor layer, wherein forming the electrical contact comprises: etching a cavity in the dielectric layer to expose a portion of the silicon cap layer in the dielectric layer; depositing a first metal to coat the portion of the silicon cap layer and exposed surfaces of the dielectric layer; converting the portion of the silicon cap layer into a conductive compound; and depositing a second metal to fill the cavity.

4. The method of claim 3, wherein the first metal is selected from the group consisting of titanium, nickel, and cobalt, and wherein the second metal is selected from the group consisting of tungsten, aluminum, and copper.

5. The method of claim 3, wherein the substrate includes a waveguide, and the portion of the silicon cap layer is located at a sufficient lateral distance from the waveguide to prevent optical coupling between the waveguide and the electrical contact.

6. The method of claim 1, wherein the superconductor material includes niobium and one or more of nitrogen, titanium, aluminum, germanium, and tin.

7. The method of claim 6, wherein the silicon cap layer includes one or more of amorphous silicon, polysilicon, and single-crystal silicon.

8. The method of claim 1, wherein the superconductor material includes niobium nitride, and wherein the silicon cap layer includes amorphous silicon.

9. The method of claim 8, further comprising depositing a protective layer after depositing the superconductor layer and before depositing the silicon cap layer, the protective layer including aluminum and nitrogen.

10. The method of claim 1, further comprising, after forming the multilayer stack: depositing a dielectric layer; and forming an electrical contact through the dielectric layer to a portion of the superconductor layer, wherein forming the electrical contact comprises: etching a cavity in the dielectric layer to expose a portion of the silicon cap layer in the dielectric layer; depositing a first metal to coat the portion of the silicon cap layer and exposed surfaces of the dielectric layer; converting the portion of the silicon cap layer into a conductive compound; and depositing a second metal to fill the cavity.

11. The method of claim 10, wherein the first metal is selected from the group consisting of titanium, nickel, and cobalt, and wherein the second metal is selected from the group consisting of tungsten, aluminum, and copper.

12. The method of claim 10, wherein the substrate includes a waveguide, and the portion of the silicon cap layer is located at a sufficient lateral distance from the waveguide to prevent optical coupling between the waveguide and the electrical contact.

13. The method of claim 3, further comprising obtaining the substrate, wherein obtaining the substrate comprises: patterning a semiconductor layer of a semiconductor-on-insulator wafer to form a waveguide; depositing a dielectric layer over the waveguide; and planarizing the dielectric layer.

14. The method of claim 3, wherein the superconductor material includes niobium and one or more of nitrogen, titanium, aluminum, germanium, and tin.

15. The method of claim 14, wherein the silicon cap layer includes one or more of amorphous silicon, polysilicon, and single-crystal silicon.

16. The method of claim 3, wherein the superconductor material includes niobium nitride, and wherein the silicon cap layer includes amorphous silicon.

17. The method of claim 16, further comprising depositing a protective layer after depositing the superconductor layer and before depositing the silicon cap layer, the protective layer including aluminum and nitrogen.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) For a better understanding of the various described embodiments, reference should be made to the Detailed Description below, in conjunction with the following drawings in which like reference numerals refer to corresponding parts throughout the figures.

(2) FIG. 1A illustrates a plan view of a superconducting nanowire single photon detector in accordance with some embodiments.

(3) FIG. 1B is a cross-sectional view along line A-A′ across a nanowire portion of the superconducting nanowire single photon detector shown in FIG. 1A in accordance with some embodiments.

(4) FIG. 1C illustrates a cross-sectional view of a superconducting nanowire single photon detector that includes a protective layer in accordance with some embodiments.

(5) FIG. 1D is a cross-sectional view along line B-B′ across a contact portion of the superconducting nanowire single photon detector shown in FIG. 1A in accordance with some embodiments.

(6) FIG. 1E illustrates a cross-sectional view of a superconducting nanowire single photon detector that includes a protective layer in accordance with some embodiments.

(7) FIG. 1F illustrates another plan view of a superconducting nanowire single photon detector in accordance with some embodiments.

(8) FIGS. 2A-2Q illustrate cross-sectional views of a superconducting nanowire single photon detector at various stages of a fabricating process in accordance with some embodiments.

(9) FIG. 3 illustrates a method of fabricating a superconducting nanowire single photon detector in accordance with some embodiments.

(10) Like reference numerals refer to corresponding parts throughout the several views of the drawings. For ease of illustration, the drawings may not be drawn to scale unless stated otherwise.

DETAILED DESCRIPTION

(11) Reference will now be made in detail to embodiments, examples of which are illustrated in the accompanying drawings. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the various described embodiments. However, it will be apparent to one of ordinary skill in the art that the various described embodiments may be practiced without these specific details. In other instances, well-known methods, procedures, components, circuits, and networks have not been described in detail so as not to unnecessarily obscure aspects of the embodiments.

(12) It will also be understood that, although the terms first, second, etc. are, in some instances, used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, a first dielectric layer could be termed a second dielectric layer, and, similarly, a second dielectric layer could be termed a first dielectric layer, without departing from the scope of the various described embodiments. The first dielectric layer and the second dielectric layer are both dielectric layers, but they are not the same dielectric layer.

(13) A1. In some embodiments, a superconductor device comprises: a barrier layer including silicon and nitrogen; a seed layer over the barrier layer, the seed layer including aluminum and nitrogen; a superconductor layer over the seed layer, the superconductor layer including a layer of a superconductor material; and a cap layer including silicon over the superconductor layer.

(14) A2. In some embodiments, the superconductor device of A1 further comprises a metal contact. The cap layer has a converted portion including a conductive compound to provide electrical coupling between the superconductor layer and a metal contact, and the metal contact is over the conductive compound and electrically-coupled to the superconductor layer via the conductive compound.

(15) A3. In some embodiments, in the superconductor device of A2, the metal contact comprises a core including a first metal; and an outer layer around the core and including a second metal; the conductive compound includes a silicide of the second metal.

(16) A4. In some embodiments, the superconductor device of any of A2-A3 further comprises a waveguide; and the metal contact is at a sufficient lateral distance from the waveguide to prevent optical coupling between the metal contact and the waveguide.

(17) A5. In some embodiments, in the superconductor device of A4, the lateral distance is at least 800 nm.

(18) A6. In some embodiments, the superconductor device of any of A1-A5 further comprises: a dielectric layer over the cap layer; and a metal routing layer over the dielectric layer, the dielectric layer has a thickness sufficient to prevent optical coupling between the waveguide and the metal routing layer.

(19) A7. In some embodiments, in the superconductor device of A6, the thickness is at least 800 nm.

(20) A8. In some embodiments, the superconductor device of any of A1-A7 further comprises: a substrate; a waveguide over the substrate; and a dielectric layer over the waveguide, the barrier layer is over the dielectric layer.

(21) A9. In some embodiments, in the superconductor device of A8, the substrate is part of a semiconductor-on-insulator substrate having a semiconductor layer on an insulator layer, and the waveguide includes a portion of the semiconductor layer.

(22) A10. In some embodiments, the superconductor device of any of A1-A9 further comprises: sidewalls adjacent to the barrier layer, the seed layer, the superconductor layer, and the cap layer, the sidewalls include silicon and nitrogen.

(23) A11. In some embodiments, in the superconductor device of any of A1-A10, the superconductor material includes niobium and one or more of nitrogen, titanium, aluminum, germanium, and tin.

(24) A12. In some embodiments, in the superconductor device of any of A1-A10, the superconductor material includes niobium nitride.

(25) A13. In some embodiments, in the superconductor device of any of A1-A12, the cap layer includes one or more of amorphous silicon, polysilicon, and single-crystal silicon.

(26) A14. In some embodiments, in the superconductor device of any of A1-A12, the cap layer includes amorphous silicon.

(27) A15. In some embodiments, the superconductor device of any of A1-A14 further comprises a protective layer between the superconductor layer and the cap layer, the protective layer including aluminum and nitrogen.

(28) A16. In some embodiments, in the superconductor device of A15, the protective layer is 5-10 nm thick.

(29) A17. A method of manufacturing a superconductor device comprises depositing a barrier layer over a substrate including silicon, the barrier layer including silicon and nitrogen; depositing a seed layer over the barrier layer, the seed layer including aluminum and nitrogen; depositing a superconductor layer over the seed layer, the superconductor layer including a layer of a superconductor material; and depositing a silicon cap layer over the superconductor layer.

(30) A18. In some embodiments, the method of A17 further comprises patterning the silicon cap layer, the superconductor layer, the seed layer and the barrier layer to form a multilayer stack.

(31) A19. In some embodiments, the method of A18 further comprises, after forming the multilayer stack: depositing a layer of protective material over the multilayer stack; and anisotropically etching the layer of protective material to form a plurality of sidewalls on sides of the multilayer stack.

(32) A20. In some embodiments, the method of A19 further comprises, after forming the sidewalls, applying a hydrogen anneal to remove oxygen from the superconductor layer.

(33) A21. In some embodiments, the method of any of A18-A20 further comprises, after forming the multilayer stack: depositing a dielectric layer; and forming an electrical contact through the dielectric layer to a portion of the superconductor layer. In some embodiments, forming the electric contact comprises: etching a cavity in the dielectric layer to expose a portion of the silicon cap layer in the dielectric layer; depositing a first metal to coat the portion of the silicon cap layer and exposed surfaces of the dielectric layer; converting the portion of the silicon cap layer into a conductive compound; and depositing a second metal to fill the cavity.

(34) A22. In some embodiments, in the method of A21, forming the electrical contact further comprises forming a metal pad or a metal line over the cavity, the metal pad or metal line being connected to the second metal.

(35) A23. In some embodiments, in the method of any of A21-A22, the first metal is selected from the group consisting of titanium, nickel, and cobalt.

(36) A24. In some embodiments, in the method of A23, the second metal is selected from the group consisting of tungsten, aluminum, and copper.

(37) A25. In some embodiments, in the method of any of A21-A24, the substrate includes a waveguide, and the portion of the silicon cap layer is located at a sufficient lateral distance from the waveguide to prevent optical coupling between the waveguide and the electrical contact.

(38) A26. In some embodiments, in the method of A25, the lateral distance is at least 800 nm.

(39) A27. In some embodiments, the method of any of A17-A26 further comprises obtaining the substrate. In some embodiments, obtaining the substrate comprises: patterning a semiconductor layer of a semiconductor-on-insulator wafer to form a waveguide; depositing a dielectric layer over the waveguide; and planarizing the dielectric layer.

(40) A28. The method of any of A17-A27, the superconductor material includes niobium and one or more of nitrogen, titanium, aluminum, germanium, and tin.

(41) A29. The method of any of A17-A27, the superconductor material includes niobium nitride.

(42) A30. The method of any of A17-A29, the silicon cap layer includes one or more of amorphous silicon, polysilicon, and single-crystal silicon.

(43) A31. The method of any of A17-A29, the silicon cap layer includes amorphous silicon.

(44) A32. In some embodiments, the method of any of A17-A31 further comprises depositing a first protective layer after depositing the superconductor layer and before depositing the silicon cap layer, the protective layer including aluminum and nitrogen.

(45) A33. In some embodiments, in the method of A32, the protective layer is 5-10 nm thick.

(46) FIG. 1A is a plan view of an SNSPD 100 in an x-y plane according to some embodiments. As shown, SNSPD 100 includes a superconductor stack 102 including a nanowire portion 110, connector portions 121, 122, and contact portions 123, 124. Nanowire portion 110 includes parallel line segments 111 and joining segments 112 together forming a meandering superconducting nanowire. In some embodiments, as shown in the inset in FIG. 1A, which provides a zoomed-in view of a joining segment 112, the joining segment 112 can have a curved inner perimeter 113 between two neighboring line segments 111 joined by the joining segment 112. In some embodiments, the curved inner perimeter provides a smooth transition between the two neighboring line segments to minimize current crowding effects. In some embodiments, nanowire portion 110 is fabricated over an optical waveguide structure (or waveguide) 105 to improve optical coupling efficiency. In some embodiments, as shown in FIG. 1A, nanowire portion 110 is wider than waveguide 105 to further improve the optical coupling efficiency.

(47) As an example, FIG. 1A shows an area occupied by nanowire portion 110 being somewhat rectangular in shape. In practice, the nanowire portion can have any of a variety of geometrical configurations. For example, the nanowire can form one or more U-shapes, as shown in FIG. 1F. In some embodiments, the nanowire portion 110 can have a geometry that is independent of that of waveguide 105, as discussed below with respect to FIG. 2D. Most generally, one or more embodiment disclosed herein can have any geometry without departing from the scope of the present disclosure.

(48) As shown in FIG. 1A, contact portion 123 is connected to a first end 115 of nanowire portion 110 via connector portion 121, and contact portion 124 is connected to a second end 116 of nanowire portion 110 via connector portion 122. In some embodiments, SNSPD 100 further includes metal contacts (not shown in FIG. 1A) over contact portions 123, 124. To prevent or reduce optical coupling (e.g., evanescent coupling) between the metal contacts and waveguide 105, contact portions 123, 124 are disposed (e.g., spaced apart) at a distance D (e.g., a lateral distance measured in the x-y plane) from waveguide 105. Distance D is dependent on a wavelength of photons to be transferred via the waveguide 105. In some embodiments, distance D can be at least 500 nm, e.g., 800 nm. Superconductor stack 102 and waveguide 105 are disposed on a substrate 101.

(49) FIG. 1B is a cross-sectional view of SNSPD 100 in an y-z plane cut across line segments 111 of nanowire portion 110 (along line A-A′ in FIG. 1A), according to some embodiments. As shown, SNSPD 100 has a layered structure, including a first dielectric layer 104 over substrate 101, waveguide 105 over first dielectric layer 104, a second dielectric layer 106 over and around waveguide 105 and serving as cladding for waveguide 105, superconductor stack 102 over second dielectric layer 106, a third dielectric layer 108 encapsulating superconductor stack 102, and additional layers and structures not shown in FIG. 1B. In other words, first dielectric layer 104 is located between substrate 101 and waveguide 105, waveguide 105 is located between first dielectric layer 104 and a first portion of second dielectric layer 106, a second portion of second dielectric layer 106 is located around waveguide 105 and over first dielectric layer 104, and superconductor stack 102 is located between second dielectric layer 106 and a portion of third dielectric layer 108. In some embodiments, first dielectric layer 104 functions as a buffer layer between substrate 101 and waveguide 105 and has a thickness of at least 20 nm.

(50) FIG. 1B also includes an inset showing a zoomed-in view of the cross-section of one of the line segments 111 and a corresponding portion of waveguide 105, according to some embodiments. As shown, multi-layer stack 102 includes a barrier layer 130, a seed layer 132 over the barrier layer 130, a superconductor layer 134 over the seed layer 132, and a silicon cap layer (or cap layer) 136 over the superconductor layer 134. In other words, seed layer 132 is located between barrier layer 130 and superconductor layer 134, and superconductor layer 134 is located between seed layer 132 and cap layer 136). SNSPD 100 may further include sidewalls 138-A and 138-B flanking opposing sides of superconductor stack 102. In some embodiments, barrier layer 130 includes silicon and nitrogen (e.g., silicon nitride), seed layer 132 includes aluminum and nitrogen (e.g., aluminum nitride), superconductor layer 134 includes niobium and one or more of nitrogen, titanium, aluminum, germanium, and tin (e.g., NbN, NbTi, NbAl, NbGe, NbSn, etc.), cap layer 136 includes silicon (e.g., amorphous silicon or a-Si, polysilicon or poly-Si, or single-crystal silicon or mono c-Si), and sidewalls 138-A and 138-B include silicon and nitrogen (e.g., silicon nitride).

(51) As shown in FIG. 1B, a portion 106A of second dielectric layer 106 is located between waveguide 105 and barrier layer 130. Also, a portion of third dielectric layer 108 is located over the cap layer 136, and a portion of first dielectric layer 104 is located between waveguide 105 and substrate 101. FIGS. 1A and 1B illustrate some vertical and horizontal dimensions of SNSPD 100, as listed below: L1: width of superconducting layer 134 in each line segment 111 of nanowire portion 110; L2: width of space between two neighboring line segments 111 of nanowire portion 110; L3: thickness of the portion 106A of second dielectric layer 106; L4: thickness of barrier layer 130; L5: thickness of seed layer 132; L6: thickness of superconductor layer 134; L7: thickness of cap layer 136; L8: thickness of sidewalls 138-A and 138-B; L9: thickness of waveguide 105; L10: thickness of third dielectric layer 108;
In some embodiments: L1 is greater than 20 nanometers (nm) and less than 200 nm (i.e., 20 nm<L1<200 nm); L2 is greater than 20 nm and less than 300 nm (i.e., 30 nm<L2<300 nm); L3 is greater than 10 nm and less than 100 nm (i.e., 10 nm<L3<100 nm); L4, L5, L6 and L7 are each greater than 2 nm and less than 40 nm (i.e., 2 nm<L4, L5, L6, L7<40 nm); L8 is greater than 1 nm and less than 20 nm (i.e., 1<L8<20 nm); L9 is greater than 100 nm and less than 1 micrometer (μm) (i.e., 100 nm<L9<1 μm); L10 is greater than 800 nm and less than 100 μm (e.g., 800 nm<L10<20 μm); and
In some embodiments: L1 is greater than 45 nm and less than 100 nm (i.e., 45 nm<L1<100 nm); L2 is greater than 45 nm and less than 200 nm (i.e., 45 nm<L2<200 nm); L3 is greater than 20 nm and less than 50 nm (i.e., 20 nm<L3<50 nm); L4 is greater than 5 nm and less than 20 nm (i.e., 5 nm<L4<20 nm); L5 and L6 are each greater than 5 nm and less than 20 nm (i.e., 5 nm<L5, L6<20 nm); L7 is greater than 3 nm and less than 20 nm (i.e., 3 nm<L7<20 nm); L8 is greater than 2 nm and less than 10 nm (i.e., 2<L8<10 nm); L9 is greater than 150 nm and less than 500 nm (i.e., 150 nm<L9<500 nm); L10 is greater than 1 μm and less than 10 μm (i.e., 1 μm<L10<10 μm).

(52) In some embodiments, the width L1 and thickness L6 of superconductor layer 134 are selected based on the wavelength of the photons to be detected. In some embodiments, L10 is designed to be sufficiently large to prevent any optic coupling (e.g., evanescent coupling) between metal lines (not shown) formed over dielectric layer 108 and waveguide 105 or superconductor stack 102. In some embodiments, the sum of L3, L4, and L5 is small enough to enable optical coupling (e.g., evanescent coupling) between superconductor layer 134 and the waveguide 105 (e.g., L3+L4+L5<200 nm).

(53) FIG. 1C is nearly identical to FIG. 1B except that the inset in FIG. 1C shows superconductor stack 102 further including an optional protective layer 131 between superconductor layer 134 and cap layer 136, according to some embodiments. In some embodiments, protective layer 131 includes aluminum and nitrogen (e.g., aluminum nitride). In some embodiments, the protective layer has a thickness L11 greater than 5 nm and less than 10 nm (e.g., 5 nm<L11<10 nm). In some embodiments, L11 greater than 1 nm and less than 5 nm (e.g., 1 nm<L11<5 nm) In some embodiments, protective layer 131 can be included to prevent oxidation of superconductor layer 134 during fabrication of SNSPD 100, if fabrication facilities used to fabricate SNSPD do not provide in-situ deposition of superconductor layer 134 and cap layer 136.

(54) FIG. 1D is a cross-sectional view of SNSPD 100 cut across contact portions 123 (along line B-B′ in FIG. 1A), according to some embodiments. As shown, SNSPD 100 further includes a contact 140 above contact portion 123 of superconductor stack 102. According to some embodiments, contact 140 includes a contact core 141 in a contact hole 142 formed in dielectric layer 108. SNSPD 100 further includes a contact liner or outer layer 143 between contact core 141 and dielectric layer 108. Contact 140 further includes a contact pad (or metal line) 145 above and electrically coupled with contact core 141 and contact liner 143. Contact core 141 includes a metallic material, such as tungsten, aluminum, copper, etc. Contact liner 143 may include a same or different metallic material, such as titanium (Ti), nickel (Ni), cobalt (Co), etc. In some embodiments, as shown in FIG. 1D, contact hole 142 has a diameter (or horizontal dimension) d1 of about 100 nm or more near bottom 146 and a diameter (or horizontal dimension) d2 of about 100 nm or more near contact pad 145, and contact liner 143 has a thickness t1 of about 5 nm-100 nm.

(55) FIG. 1D also includes an inset showing a zoomed in view of an area 147 near a bottom 146 of contact 140. As shown, a region 137 of cap layer 136 under and adjacent bottom 146 of contact 140 is converted to a conductive compound 138, which provides low-resistance electrical coupling between contact 140 and superconducting layer 134. In some embodiments, contact hole lining 143 includes Ti, Ni or Co and conductive compound 138 includes titanium silicide, nickel silicide, or cobalt silicide respectively.

(56) FIG. 1E illustrates a cross-sectional view of SNSPD 100 cut across contact portions 123 (along line B-B′ in FIG. 1A), with an inset showing superconductor stack 102 further including a protective layer 131 between superconductor layer 134 and cap layer 136, according to some embodiments, as discussed above with reference to FIG. 1C. In some embodiments, as shown in the inset in FIG. 1E, when protective layer 131 is provided, contact hole 142 extends through protective layer 131.

(57) FIGS. 2A through 2Q, together with FIG. 3, illustrate a method 300 of manufacturing SNSPD 100, according to some embodiments. As shown in FIGS. 2A-2D and 3, method 300 includes obtaining a substrate (310). In some embodiment, as shown in FIG. 2A, obtaining a substrate (310) may start with a semiconductor-on-insulator (SOI) substrate 201 that includes a semiconductor (e.g., silicon, gallium arsenide, etc.) substrate 101, an insulator layer (e.g., dielectric layer 104) over the semiconductor substrate 101, and a semiconductor (e.g., silicon, gallium arsenide, etc.) film 205 over the insulator layer 104. As shown in FIG. 2B, obtaining a substrate (310) may further include patterning the semiconductor layer 205 (312) using, for example, photolithography and anisotropic etching (e.g., plasma or reactive ion etching), to form waveguide 105 on dielectric layer 104. As shown in FIGS. 2C and 2D, obtaining a substrate (310) may further include forming a dielectric layer (314) over waveguide 105 and dielectric layer 104, which may include, for example, depositing a dielectric (e.g., silicon dioxide) layer 206 over substrate 201 using, for example, chemical vapor deposition. Dielectric layer 206 is then planarized to form dielectric layer 106 using, for example, chemical mechanical polishing, resulting in a flat surface 106a, on which a superconductor nanowire of any of various shapes and dimensions can be fabricated. For example, the superconductor nanowire to be formed over the cladding (e.g., dielectric layer 106) of waveguide 105 can be wider than waveguide 105. In some embodiments, the obtained substrate (e.g., substrate 200) includes substrate 101, dielectric layer 104, waveguide 105, and dielectric layer 106, as shown in FIG. 2D.

(58) As shown in FIG. 3, method 300 further includes fabricating a superconductor stack (320) over the obtained substrate (e.g., substrate 200). In some embodiments, as shown in FIGS. 3 and 2E, fabricating the superconductor stack (320) includes forming 322 on substrate 200 a multilayer thin film 210. In some embodiments, multilayer thin film 210 includes a layer of a first material 230, a layer of a second material 232 formed over (e.g., on top of, on a surface of) the layer of the first material 230, a layer of a third material 234 formed over (e.g., on top of, on a surface of) the layer of the second material 232, and a layer of a fourth material 236 formed over (e.g., on top of, on a surface of) the layer of the third material 234. In some embodiments, the layer of the first material 230 includes silicon and nitrogen (e.g., silicon nitride), the layer of the second material 232 includes aluminum and nitrogen (e.g., aluminum nitride), the layer of the third material 234 includes niobium and one or more of nitrogen, titanium, aluminum, germanium, and tin (e.g., NbN, NbTi, NbAl, NbGe, NbSn, etc.), and the layer of the fourth material 236 includes silicon (e.g., a-Si, poly-Si, or mono c-Si). In some embodiments, each layer in the multilayer thin film 210 has a thickness that is greater than 2 nm and less than 40 nm. In some embodiments, the layer of the first material 230 is greater than 10 nm and less than 20 nm, the layer of the second material 232 and the layer of the third material 234 are each greater than 5 nm and less than 10 nm, the layer of the fourth material 236 is greater than 3 nm and less than 10 nm.

(59) In some embodiments, the layer of the first material 230 is deposited onto substrate 200 using a process suitable for depositing an ultrathin film (e.g., 10 nm-20 nm) including silicon and nitrogen (e.g., silicon nitride), such as, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-enhanced chemical vapor deposition (PECVD), catalytic chemical vapor deposition (Cat-CVD), hot wire chemical vapor deposition (HWCVD), etc. In some embodiments, the layer of the second material 232 is deposited onto the first layer of material 230 using a process suitable for depositing an ultrathin film (e.g., 5 nm-10 nm) including aluminum and nitrogen (e.g., aluminum nitride), such as, for example, CVD, PECVD, PVD, magnetron sputtering (MS), molecular beam epitaxy (MBE), atomic layer deposition (ALD), Plasma-Enhanced Atomic Layer Deposition (or PEALD), etc. In some embodiments, the layer of the third material 234 is deposited onto the layer of the second material 232 using a process suitable for depositing an ultrathin (e.g., 2 nm-40 nm) film including a superconductor compound (e.g., NbN, NbTi, NbAl, NbGe, or NbSn), such as, for example, CVD, PVD, PECVD, MS, MBE, ALD, PEALD, etc. In some embodiments, the layer of the fourth material 236 is deposited onto the layer of the third material 234 using a process suitable for depositing an ultrathin (e.g., 2 nm-40 nm) film including silicon (e.g., a-Si, poly-Si, or mono c-Si), such as, for example, CVD, PECVD, MS, MBE, ALD, PEALD, etc. In some embodiment, the layer of the fourth material 236 includes a-Si because a-Si can be deposited at relative low temperature (e.g., ˜75 degrees Celsius) using a CVD process that causes little or no damage the underlying superconductor layer 234.

(60) In some embodiments, as shown in FIGS. 3 and 2F, fabricating the superconductor stack (320) further includes patterning 324 multilayer thin film 210 to form a patterned multilayer stack 212 using a plurality of fabrication processes including, for example, a high-resolution lithography process to form a mask on multilayer thin film 210, and one or more anisotropic etching processes to successively etch away exposed portions of the layer of the fourth material 236, the layer of the third material 234, the layer of the second material 232, and the layer of the first material 230. At least the layer of the first material 230 is etched using an anisotropic process that is selective to dielectric layer 106. FIG. 2F shows a cross-sectional view of the resulting multilayer stack 212, according to some embodiments.

(61) After multilayer stack 212 is formed by patterning 324 multilayer thin film 210, the remaining portion of the layer of the first material 230 becomes barrier layer 130, the remaining portion of the layer of the second material 232 becomes seed layer 132, the remaining portion of the layer of the third material 234 becomes superconducting layer 134, and the remaining portion of the layer of the fourth material 236 becomes cap layer 136. In some embodiments, the layer of the second material 232 acts as a seed layer for improved surface morphology during subsequent deposition of the layer of the third material 234, resulting in enhanced qualities of superconducting layer 134. Barrier layer 130 acts as a barrier between superconducting layer 134 and dielectric layer 106, preventing or reducing oxidation of superconducting layer 134 from oxygen released from dielectric layer 106 during and/or after fabrication of SNSPD 100.

(62) In certain embodiments, as shown in FIG. 2G, multilayer thin film 210 further includes an optional layer of a fifth material 231 formed over the layer of the third material 234 and before forming the layer of the fourth material 236. In some embodiments, the layer of the fifth material 231 includes aluminum and nitrogen (e.g., aluminum nitride), and has a thickness that is greater than 1 nm and less than 10 nm, or greater than 1 nm and less than 5 nm. When multilayer thin film 210 further includes the layer of a fifth material 231, patterning 324 multilayer thin film 210 further includes etching the layer of the fifth material 231 after etching the layer of the fourth material 236 and before etching the other layers in the multilayer thin film 210, to form protective layer 131, as shown in FIG. 2H. In some embodiments, protective layer 131 can be used to protect superconductor layer 134 from exposure to atmosphere during fabrication of SNSPD 100. For example, if the fabrication facility/process chamber used to form the layer of the fourth material 236 (e.g., a-silicon) must be isolated from one or more materials that are used to form the layer of the third material 234 (e.g., NbN), substrate 101 or 200 may first need to be brought up to atmosphere and transferred from one process chamber that is used to deposit the NbN to another process chamber that is used to deposit a-silicon.

(63) In some embodiments, as shown in FIG. 3, fabricating the superconductor stack 320 further includes forming 326 sidewalls on two opposing sides 241 and 242 of multilayer stack 212 by depositing a layer of sidewall materials 238 that conforms to contours of multilayer stack 212, as shown in FIG. 2I. In some embodiments, the layer of sidewall materials 238 can be deposited using, for example, chemical vapor deposition, to cover a top 243 and the two opposing sides 241 and 242 of multilayer stack 212, as well as portions of dielectric layer 106 not under (or covered) multilayer stack 212. Portions of the layer of sidewall material on top of multilayer stack 212 and on dielectric layer 106 are then removed in an anisotropic etching process, leaving sidewalls 138-A and 138-B on sides 241 and 242 of multilayer stack 212, respectively. The sidewall material 238 can be including, for example, silicon and nitrogen (e.g., silicon nitride), and the remaining sidewalls 138-A and 138-B each has a thickness greater than 500 Angstrom and less than 2 nm.

(64) In some embodiments, as shown in FIGS. 3 and 2K, fabricating the superconductor stack (320) further includes subjecting substrate 200, along with the structures formed thereon, to an anneal process 328 to allow oxygen atoms or molecules 250 trapped in or near superconducting layer 134 to escape the multilayer stack 212. After the annealing process 328, the patterned multilayer stack 212, together with sidewalls 138-A and 138-B, become the fabricated superconductor stack, such as either of the superconductor stacks 102 shown in FIGS. 1A through 1C, according to some embodiments.

(65) In some embodiments, as shown in FIGS. 3 and 2L, method 300 of manufacturing SNSPD 100 further includes encapsulating the superconductor stack (330) with a dielectric layer by depositing a thick layer of dielectric material (e.g., silicon dioxide) over substrate 200 and superconductor stack 102 formed thereon, using, for example, a CVD process, and by planarizing the thick layer of dielectric material using, for example, chemical mechanical polishing, to form the encapsulating dielectric layer (e.g., dielectric layer 108). In some embodiments, the encapsulating dielectric layer (e.g., dielectric layer 108) has a thickness L10 that is sufficiently large to prevent optical coupling (e.g., evanescent coupling) between metal lines (not shown) that are formed over dielectric layer 108 and waveguide 105 or superconductor stack 102. In some embodiments, thickness L10 is greater than 800 nm and less than 20 μm. In some embodiments, thickness L10 is greater than 1 μm and less than 10 μm.

(66) In some embodiments, as shown in FIGS. 3 and 2M-2Q, method 300 of manufacturing SNSPD 100 further includes metallization processes 340 to form contacts over contact portions 123, 124 of superconductor stack 102. FIG. 2M is a cross-sectional view of contact portion 123 of superconductor stack 102 before the contacts are formed, showing contact portion 123 disposed over dielectric layer 106 and away from waveguide 105, as illustrated in FIG. 1A, according to some embodiments. As shown in FIGS. 3 and 2N, metallization processes 340 include forming 342 contact holes (e.g., contact hole 142 over contact portion 123) by etching dielectric layer 108 using one or more anisotropic etching process (e.g., plasma etching, or reactive ion etching or RIE) to allow bottoms of the contact holes to reach cap layer 136, as shown in FIG. 2N. In some embodiments, the one or more etching processes includes a first etching process for removing portions of dielectric layer 108 occupying upper portions of the contact holes (e.g., portion 142A of contact hole 142) and a second etching process for removing portions of dielectric layer 108 occupying lower portions of the contact holes (e.g., portion 142B of contact hole 142). The first etching process is an anisotropic etching process for etching the dielectric material in dielectric layer 108 with a relatively high etch rate. The second etching process is an anisotropic etching process for etching the dielectric material in dielectric layer 108 with a relatively low etch rate but with a high selectivity over the layer under dielectric layer 108 (e.g., cap layer 136). The etching process(es) with high selectivity is used to clear (e.g., remove) portions of dielectric layer 108 or portions of the optional protective layer 131 near the bottoms of the contact holes without punching through any part of cap layer 136. In some embodiments, the one or more etching processes for forming 342 contact holes can be any reactive ion etching processes for etch silicon dioxide that is selective to amorphous silicon. Thus, the cap layer can function as an etch-stop layer for forming the contact holes for SNSPD 100.

(67) As shown in FIGS. 3 and 2O, metallization processes 340 further includes depositing 344 a film 243 including a metal, such as Ti, Ni, Co, etc., or one or more compound thereof, over substrate 200 and the structures formed thereon using, for example, a PVD process. In some embodiments, the metal in film 243 is selected such that film 243 can be deposited at temperatures below 600 degrees Celsius. Film 243 is deposited to coat exposed surfaces of dielectric layer 108 (including walls of the contact holes), and exposed portions of cap layer 136 at the bottoms of the contact holes (e.g., contact hole 142). As shown in FIGS. 3 and 2P, metallization processes 340 further include silicide formation 346, during which the metal in film 243 diffuses into portions of cap layer 136 in contact with the metal film 243 at the bottoms of the contact holes (e.g., portion 137 under contact hole 142) resulting in such portions to be converted to silicide 138. Silicide formation 246 may include subjecting substrate 200, along with the structures formed thereon, to an annealing process, such as rapid thermal annealing (RTA). In some embodiments, the material in cap layer 136 and the metal(s) in film 243 are selected to enable formation of silicide 138 at temperatures below 600 degrees Celsius.

(68) In some embodiments, when protective layer 131 is sufficiently thin (e.g., 5-10 nm in thickness), portions (e.g., portion 131a) of protective layer 131 under the silicide 138 can become conductive, resulting in the formation of ohmic contact through the protective layer 131 and a resulting contact resistance less than 10 ohms, which is the same or nearly the same as the contact resistance without protective layer 131.

(69) Subsequent to silicide formation process 346, substrate 200 with the structures formed thereon is then etched to remove portions of film 243 covering a top surface 248 of dielectric layer 108. Portions of film 243 remaining on sidewalls of the contact holes become contact liners or outer layers for the metal contacts to be formed (e.g., contact liner or outer layer 143 in contact hole 142), as shown in FIG. 2P. As shown in FIGS. 3 and 2Q, metallization processes 240 further includes contact core formation 348, during which the contact holes (e.g., contact hole 142) are filled with contact cores (e.g., contact core 141). Contact pads (or metal line) (e.g., contact pad or metal line 145) can then be formed over contact core 141, using, for example, conventional processes for forming contact pads or metal line.

(70) The terminology used in the description of the various described embodiments herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used in the description of the various described embodiments and the appended claims, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term “and/or” as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items. It will be further understood that the terms “includes,” “including,” “comprises,” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

(71) As used herein, the term “if” is, optionally, construed to mean “when” or “upon” or “in response to determining” or “in response to detecting” or “in accordance with a determination that,” depending on the context.

(72) The foregoing description, for purpose of explanation, has been described with reference to specific embodiments. However, the illustrative discussions above are not intended to be exhaustive or to limit the scope of the claims to the precise forms disclosed. Many modifications and variations are possible in view of the above teachings. The embodiments were chosen in order to best explain the principles underlying the claims and their practical applications, to thereby enable others skilled in the art to best use the embodiments with various modifications as are suited to the particular uses contemplated.