Semiconductor Device with Oxide-Nitride Stack

Abstract

A semiconductor device includes a semiconductor layer with opposing first and second main surfaces and a first column extending from the first main surface and having a first concentration of a dopant of the first conductivity type. A trench with a sidewall and bottom extends at least partially through the semiconductor layer from the first main surface. A second column between the trench sidewall and the first column has a second concentration of a dopant of a second conductivity type and is formed in the semiconductor layer and extends from the first main surface. A trench oxide layer is in contact with at least the trench sidewall and the trench bottom. A trench nitride layer covers the trench oxide layer at least on the trench sidewall. A dielectric seal material seals the trench proximate the first main surface of the semiconductor layer such that the trench is air-tight.

Claims

1. A method of making a semiconductor device, comprising: providing a semiconductor layer; forming a first trench at least partially through the semiconductor layer; forming a first oxide layer over a surface of the semiconductor layer and over a sidewall of the first trench; and forming a first nitride layer over the first oxide layer.

2. The method of claim 1, further comprising: forming a second trench at least partially through the semiconductor layer; forming a first column of semiconductor material in the semiconductor layer between the first trench and second trench; and forming a second column of semiconductor material in the semiconductor layer between the first trench and second trench.

3. The method of claim 1, further comprising: removing a portion of the first oxide layer and first nitride layer to expose the surface of the semiconductor layer; and forming a source/drain region proximate to the surface of the semiconductor layer.

4. The method of claim 3, further comprising: forming a second oxide layer over the surface of the semiconductor layer; forming a second nitride layer over a portion of the second oxide layer; and forming a gate electrode over a portion of the second nitride layer.

5. The method of claim 1, further comprising forming a source/drain region proximate to the surface of the semiconductor layer prior to forming the first oxide layer and first nitride layer.

6. The method of claim 1, further comprising: forming a body contact region proximate to the surface of the semiconductor layer and adjacent to the sidewall of the first trench; and forming a body region proximate to the surface of the semiconductor layer and adjacent to the sidewall of the first trench and surrounding the source/drain region and the body contact region.

7. A method of making a semiconductor device, comprising: providing a semiconductor layer; forming a first trench into the semiconductor layer; forming an oxide layer over a surface of the semiconductor layer and over a sidewall of the first trench; and forming a nitride layer over the oxide layer.

8. The method of claim 7, further comprising: forming a second trench into the semiconductor layer; forming a first column of semiconductor material in the semiconductor layer between the first trench and second trench; and forming a second column of semiconductor material in the semiconductor layer between the first trench and second trench.

9. The method of claim 7, further comprising: removing a portion of the nitride layer and oxide layer to expose the surface of the semiconductor layer; and forming a source/drain region proximate to the surface of the semiconductor layer.

10. The method of claim 9, further comprising: forming a gate oxide layer over the surface of the semiconductor layer; forming a gate nitride layer over a portion of the gate oxide layer; and forming a gate electrode over a portion of the gate nitride layer.

11. The method of claim 7, further comprising forming a source/drain region proximate to the surface of the semiconductor layer prior to forming the oxide layer and nitride layer.

12. The method of claim 7, further comprising: forming a body contact region proximate to the surface of the semiconductor layer and adjacent to the sidewall of the first trench; and forming a body region proximate to the surface of the semiconductor layer and adjacent to the sidewall of the first trench and surrounding the source/drain region and the body contact region.

13. The method of claim 7, further including forming the oxide layer over a bottom surface of the first trench.

14. A semiconductor device, comprising: a semiconductor layer; a first trench formed into the semiconductor layer; a first oxide layer formed over a surface of the semiconductor layer and over a sidewall of the first trench; and a first nitride layer formed over the first oxide layer.

15. The semiconductor device of claim 14, further comprising: a second trench formed into the semiconductor layer; a first column of semiconductor material formed in the semiconductor layer between the first trench and second trench; and a second column of semiconductor material formed in the semiconductor layer between the first trench and second trench.

16. The semiconductor device of claim 14, further including a source/drain region formed proximate to the surface of the semiconductor layer.

17. The semiconductor device of claim 14, further comprising: a second oxide layer formed over the surface of the semiconductor layer; a second nitride layer formed over a portion of the second oxide layer; and a gate electrode formed over a portion of the second nitride layer.

18. The semiconductor device of claim 17, further including an insulating layer formed over the gate electrode.

19. The semiconductor device of claim 14, further comprising: a body contact region formed proximate to the surface of the semiconductor layer and adjacent to the sidewall of the first trench; and a body region formed proximate to the surface of the semiconductor layer and adjacent to the sidewall of the first trench and surrounding the source/drain region and the body contact region.

20. The semiconductor device of claim 14, wherein the first oxide layer covers a bottom surface of the first trench.

Description

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

[0023] The following detailed description of preferred embodiments of the invention will be better understood when read in conjunction with the appended drawings. For the purpose of illustration, there are shown in the drawings embodiments which are presently preferred. It should be understood, however, that the invention is not limited to the precise arrangements and instrumentalities shown.

[0024] In the drawings:

[0025] FIG. 1 is a plot of threshold voltage and threshold leakage current in power MOSFET structures for various levels of radiation exposure;

[0026] FIG. 2 is an enlarged partial cross-sectional elevational view of a semiconductor device in accordance with a first embodiment of the present invention;

[0027] FIG. 3 is an enlarged partial cross-sectional elevational view of a semiconductor substrate and a semiconductor layer in accordance with the first embodiment;

[0028] FIG. 4 is an enlarged partial cross-sectional elevational view of the device of FIG. 3 with a trench oxide layer formed thereon;

[0029] FIG. 5 is an enlarged partial cross-sectional elevational view of the device of FIG. 4 with a trench nitride layer formed thereon;

[0030] FIG. 6 is an enlarged partial cross-sectional elevational view of the device of FIG. 5 with an oxide wafer bonded thereto;

[0031] FIG. 7 is an enlarged partial cross-sectional elevational view of the device of FIG. 6 with portions of the dielectric materials on the first main surface removed;

[0032] FIG. 8 is an enlarged partial cross-sectional elevational view of the device of FIG. 7 following formation of various MOSFET components thereon;

[0033] FIG. 9 is an enlarged partial cross-sectional elevational view of the device of FIG. 8 following formation of an inter-dielectric oxide layer;

[0034] FIG. 10 is an enlarged partial cross-sectional elevational view of a semiconductor substrate and a semiconductor layer following formation of various MOSFET components in accordance with a second embodiment of the present invention;

[0035] FIG. 11 is an enlarged partial cross-sectional elevational view of the device of FIG. 10 following formation of trenches and columns;

[0036] FIG. 12 is an enlarged partial cross-sectional elevational view of the device of FIG. 11 with trench oxide and nitride layers formed thereon;

[0037] FIG. 13 is an enlarged partial cross-sectional elevational view of the device of FIG. 12 with an oxide wafer bonded thereto;

[0038] FIG. 14 is an enlarged partial cross-sectional elevational view of the device of FIG. 13 following source/drain electrode formation;

[0039] FIG. 15 is an enlarged partial cross-sectional elevational view of a semiconductor device in accordance with a third embodiment of the present invention;

[0040] FIG. 16 is an enlarged partial cross-sectional elevational view of the device of FIG. 5 in an alternative embodiment where portions of the trench nitride layer are removed; and

[0041] FIG. 17 is an enlarged partial cross-sectional elevational view of the device of FIG. 12 in an alternative embodiment where portions of the trench nitride layer are removed.

DETAILED DESCRIPTION OF THE INVENTION

[0042] Certain terminology is used in the following description for convenience only and is not limiting. The words “right”, “left”, “lower”, and “upper” designate directions in the drawings to which reference is made. The words “inwardly” and “outwardly” refer to directions toward and away from, respectively, the geometric center of the device and designated parts thereof. The terminology includes the above-listed words, derivatives thereof, and words of similar import. Additionally, the words “a” and “an”, as used in the claims and in the corresponding portions of the specification, mean “at least one.” Unless stated otherwise, terms such as “first” and “second” are used to arbitrarily distinguish between the elements such terms describe. Thus, these terms are not necessarily intended to indicate temporal or other prioritization of such elements.

[0043] It should also be understood that the terms “about,” “approximately,” “generally,” “substantially” and like terms, used herein when referring to a dimension or characteristic of a component of the invention, indicate that the described dimension/characteristic is not a strict boundary or parameter and does not exclude minor variations therefrom that are functionally similar. At a minimum, such references that include a numerical parameter would include variations that, using mathematical and industrial principles accepted in the art (e.g., rounding, measurement or other systematic errors, manufacturing tolerances, etc.), would not vary the least significant digit.

[0044] As used herein, reference to conductivity will be limited to the embodiment described. However, those skilled in the art know that p-type conductivity can be switched with n-type conductivity and the device would still be functionally correct (i.e., a first or a second conductivity type). Therefore, where used herein, reference to n or p can also mean either n or p or p and n can be substituted therefor.

[0045] Furthermore, n.sup.+ and p.sup.+ refer to heavily doped n and p regions, respectively; n.sup.++ and p.sup.++ refer to very heavily doped n and p regions, respectively; n.sup.− and p.sup.− refer to lightly doped n and p regions, respectively; and n.sup.−− and p.sup.−− refer to very lightly doped n and p regions, respectively. However, such relative doping concentration terms should not be construed as limiting.

[0046] Referring to FIG. 2, there is shown an enlarged, partial cross-sectional, elevational view of a semiconductor device 10 in accordance with a first exemplary embodiment of the present invention. The device 10 preferably includes a semiconductor substrate 12 and a semiconductor layer 14 having opposed first and second main surfaces 14a, 14b, with the second main surface 14b of the semiconductor layer 14 being coupled to a surface of the semiconductor substrate 12. The semiconductor layer 14 may include a plurality of alternating n and p columns 16, 18 that extend at least partially from the first main surface 14a toward the semiconductor substrate 12.

[0047] At least one, and preferably more, trenches 20 are formed to extend at least partially through the semiconductor layer 14 from the first main surface 14a thereof. Each trench 20 includes a sidewall 20a and a bottom 20b. In the embodiment shown in FIG. 2, the trench 20 extends entirely through the semiconductor layer 14 such that the bottom 20b is formed by a surface of the semiconductor substrate 12. However, the invention is not so limited. The trench 20 may only extend partially through the semiconductor layer 14, in which case a portion of the semiconductor layer 14 would form the bottom 20b of the trench 20. In still other embodiments, the trench 20 may extend through the semiconductor layer 14 and partially into the semiconductor substrate 12, for example. In the example shown in FIG. 2, one of the p columns 18 is disposed between the trench 20 and a nearby n column 16, although other arrangements of device components in the semiconductor layer 14 may be utilized as well. For example, the p column 18 may extend to a shorter depth than the trench 20 such that the trench sidewall 20a may also be in contact with an n-doped portion of the semiconductor layer 14.

[0048] A trench oxide layer 22 is preferably in contact with at least the sidewall 20a and the bottom 20b of the trench 20. In the embodiment of FIG. 2, the trench oxide layer 22 is also shown contacting a portion of the first main surface 14a of the semiconductor layer 14 surrounding the trench 20A trench nitride layer 24 further preferably covers the trench oxide layer 22 at least on the sidewall 20a of the trench 20, although in FIG. 2 the trench nitride layer 24 is also shown covering the trench oxide layer 22 at the bottom 20b of the trench 20 and extending over a portion of the first main surface 14a of the semiconductor layer 14 surrounding the trench 20. Although not required, the trench nitride layer 24 preferably overlies the entire trench oxide layer 22, thereby protecting any interface between the trench oxide layer 22 and semiconductor material in the device 10. Although not required, a thin oxide layer (not shown) may be formed over the trench nitride layer 24 in some embodiments.

[0049] A dielectric seal material 26 preferably seals the trench 20 proximate to the first main surface 14a of the semiconductor layer 14 such that the trench 20 is air-tight. The dielectric seal material 26 is shown in the embodiment of FIG. 2 as being formed outside of the trench 20 and in contact with the trench nitride layer 24 (or any layers formed thereover, such as a thin oxide layer). However, in some embodiments, the dielectric seal material 26 may partially extend into the trench 20 to provide the seal. It is preferred that except for the trench lining, the trench 20 remain largely unfilled. Preferably, processing takes place in air, or one or more other gases (such as inert gases or the like), or can be performed in a vacuum. Thus, the trench 20 may contain one or more gases, such as inert gases or air. Preferred inert gases include nitrogen and argon. In a preferred embodiment, a sealed trench 20 includes ambient air. It is preferred that moisture content be kept low in such embodiments. The trench 20 may be sealed at atmospheric pressure or below. In some other embodiments, the trench 20 may be sealed under vacuum.

[0050] Highly doped (e.g., n.sup.+) regions serving as source/drain regions 28 may be formed at the first main surface 14a of the semiconductor layer 14. Similarly, highly doped (e.g., p.sup.+) regions serving as body contact regions 30 may be formed at the first main surface 14a of the semiconductor layer 14 adjacent the sidewall 20a of the trench 20 (preferably between the source/drain region 28 and the trench 20). A body region 32 (such as a p doped region) may be formed at the first main surface 14a of the semiconductor layer 14 and adjacent the sidewall 20a of the trench 20, preferably surrounding the source/drain region 28 and the body contact region 30. As shown in the embodiment of FIG. 2, the trench oxide and trench nitride layers 22, 24 preferably overlap a portion of the body contact region 30 at the first main surface 14a of the semiconductor layer 14.

[0051] A gate electrode 34 may be provided spaced apart from the first main surface 14a of the semiconductor layer 14. For example, a gate oxide layer 36 may be formed over at least a portion of the first main surface 14a of the semiconductor layer 14 between adjacent trenches 20. Preferably, a gate nitride layer 38 is formed over at least a portion of the gate oxide layer 36. The gate electrode 34 is then formed on at least a portion of the gate nitride layer 38 (although a thin oxide layer (not shown) may be deposited on the gate nitride layer 38 before formation of the gate electrode 34). An inter-dielectric oxide layer 40 may be formed over the gate electrode 34. A metal source/drain electrode 42 preferably connects with the source/drain region 28.

[0052] FIGS. 3-9 generally show various steps of manufacturing the semiconductor device 10 shown in FIG. 2.

[0053] Referring to FIG. 3, the semiconductor substrate 12 is preferably formed of silicon (Si). But, the semiconductor substrate 12 may be formed of other materials such as gallium arsenide (GaAs), germanium (Ge), or the like. The semiconductor substrate 12 preferably is of the heavily doped n.sup.+ type.

[0054] The semiconductor layer 14 is formed such that the second main surface 14b is disposed on the semiconductor substrate 12. In some embodiments, the semiconductor layer 14 may be epitaxially grown on a surface of the semiconductor substrate 12 and may be a lightly doped n.sup.− or intrinsically n doped silicon layer. The epitaxial growth or deposition may occur in a suitable reaction chamber at a temperature of up to about 1200° C. to a desired thickness. Other methods for forming the semiconductor layer 14 on the semiconductor substrate 12, such as by bonding, annealing, and the like, may be used.

[0055] The trenches 20 are formed in the first main surface 14a of the semiconductor layer 14. The trenches 20 are preferably etched using deep reactive ion etching (DRIE). DRIE utilizes an ionized gas, or plasma, such as, for example, sulfur hexafluoride (SF.sub.6), to remove material from the semiconductor layer 14. DRIE technology permits deeper trenches 20 with straighter sidewalls. Other techniques for forming the trenches 18 can be used, however, such as plasma etching, reactive ion etching (RIE), sputter etching, vapor phase etching, chemical etching, or the like.

[0056] A mask (not shown) is selectively applied over the main surface 14a of the semiconductor layer 14. The mask may be created by deposition of a layer of photoresist or in some other manner well known to those skilled in the art. The developed photoresist is removed, and undeveloped photoresist remains in place as is known in the art. For simplification, the mask refers to the material used to prevent certain areas of a semiconductor from being etched, doped, coated or the like. In certain embodiments, a thin layer of oxide or other dielectric material (not shown) may be applied to the first main surface 14a prior to formation of the mask. The trenches 20 are formed in the areas not covered by the mask. After the trenching process, the mask is removed using techniques known in the art.

[0057] The sidewalls 20a of each trench 20 can be smoothed, if needed, using, for example, one or more of the following process steps: (i) an isotropic plasma etch may be used to remove a thin layer of silicon (typically 100-1000 Angstroms) from the trench 20 surfaces or (ii) a sacrificial silicon dioxide layer may be grown on the surfaces of the trench 20 and then removed using an etch such as a buffered oxide etch or a diluted hydrofluoric (HF) acid etch. The use of the smoothing techniques can produce smooth trench surfaces with rounded corners while removing residual stress and unwanted contaminates. However, in embodiments where it is desirable to have vertical sidewalls and square corners, an anisotropic etch process will be used instead of the isotropic etch process discussed above. Anisotropic etching, in contrast to isotropic etching, generally means different etch rates in different directions in the material being etched.

[0058] If necessary, the sidewalls 20a of the trenches 20 are implanted or doped with an n-type dopant, which may occur at predetermined angles, to form the n columns 16. The implantation angles are determined by the width of the trenches 20 and the desired doping depth, and are typically from about 2° to 12° (−2° to −12°) from vertical. The implant is done at angles so that the bottom 20b of each trench 20 is not implanted. Preferably, the implantation occurs at least partially, and preferably entirely, between the first main surface 14a and the semiconductor substrate 12. The implant is performed at an energy level of about 30-200 kilo-electron-Volts (KeV) with dose ranges from about 1E13 to 1E14 cm.sup.−2 (i.e., about 1×10.sup.13 to 1×10.sup.14 cm.sup.−2). Consequently, a dopant of the first conductivity type (e.g., n-type) is implanted into the semiconductor layer 14 to form doped regions of the first conductivity type having a doping concentration lower than that of the heavily doped semiconductor substrate 12. The doping may occur with the aid of a mask (not shown) placed over the first main surface 14a of the semiconductor layer 14.

[0059] The doping may be performed by one of ion implantation, solid diffusion, liquid diffusion, spin-on deposits, plasma doping, vapor phase doping, laser doping, or the like. Doping with boron B results in a more p-type region, doping with phosphorus P results in a more n-type region and doping with arsenic Ar results in a more n-type region. Other dopants may be utilized, such as antimony Sb, bismuth Bi, aluminum Al, indium In, gallium Ga or the like depending on the material and the desired strength of the doping. Preferably, the doping is performed by ion implantation.

[0060] Following implanting, a drive-in step at a temperature of up to 1200° C. may be performed for up to 12 hours. It should be recognized that the temperature and time are selected to sufficiently drive in the implanted dopant. But, the energy level used to perform ion implantation, as described above, may be high enough to sufficiently drive in the dopants without departing from the present invention. If the semiconductor layer 14 is already adequately doped for purposes of the resulting n column 16, then these steps may be omitted.

[0061] A similar doping step preferably occurs with respect to the sidewalls 20a of the trenches 20, but with a dopant of the opposite conductivity type (e.g., p-type), to form the p columns 18 that separate the n column 16 from the trench 20.

[0062] Referring to FIG. 4, the trench oxide layer 22 is preferably formed over the first main surface 14a of the semiconductor layer 14, as well as on the sidewalls 20a and bottoms 20b of the trenches 20. The trench oxide layer 22 may be formed using thermal growth, low pressure (LP) chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), atmospheric pressure chemical vapor deposition (APCVD), deposition, or the like. Preferably, the trench oxide layer 22 has a thickness in the range of about 200 to about 5000 Angstroms.

[0063] Referring to FIG. 5, the trench nitride layer 24 is preferably formed over at least a portion of the trench oxide layer 22. For example, the trench nitride layer 24 may be formed over the trench oxide layer 22 on the first main surface 14a of the semiconductor layer 14, and the sidewalls 20a and bottoms 20b of the trenches 20. The trench nitride layer 24 may be formed using thermal growth, LPCVD, PECVD, APCVD, deposition, or the like. Preferably, the trench nitride layer 24 has a thickness in the range of about 300 to about 2500 Angstroms.

[0064] In an alternative embodiment, shown in FIG. 16, the trench nitride layer 24′ may be removed via RIE or the like from the trench oxide layer 22′ on the bottom 20b′ of the trench 20′ and over the first main surface 14a′ of the semiconductor layer 14′. In this manner, the trench nitride layer 24′ resides only on the trench oxide layer 22′ lining the sidewall 20a′ of the trench 20′. In another alternative, the relevant surfaces may be masked to such that the trench nitride layer is only grown in desired locations, such as the trench sidewall. Thus, the coverage of the trench oxide layer by the trench nitride layer is not limited to the embodiments shown.

[0065] Referring to FIG. 6, the trenches 20 are sealed by the dielectric sealing material 26, which in this embodiment is shown as an oxide wafer that is bonded to the trench nitride layer 24 (which may be facilitated by attachment of the oxide wafer 26 to a thin oxide layer (not shown) formed over the trench nitride layer 24) proximate the first main surface 14a of the semiconductor layer 14. In embodiments where the trench oxide layer 22 is exposed through the trench nitride layer 24 near the first main surface 14a of the semiconductor layer 14 (see e.g., FIG. 16), the oxide wafer 26 may be bonded to the trench oxide layer 22 or both the trench oxide and nitride layers 22, 24, depending on the configuration. The oxide wafer 26 may be provided on a handle wafer (not shown). The bonding process may include heating the layers in an annealing furnace for a number of minutes or hours. For example, the partially fabricated device of FIG. 5 and the oxide wafer 26 may be placed in an annealing furnace at 800-1200° C. for few a minutes to several hours to cause the materials to sufficiently bond. The annealing process may be performed in an inert ambient atmosphere, e.g., nitrogen gas, or in an oxidizing ambient atmosphere, e.g., pure oxygen, oxygen/nitrogen mixture, steam or the like. During a “wet” anneal, i.e., when steam is the ambient, the steam is generated using a mixture of oxygen and hydrogen typically above 800° C. The handle wafer is subsequently removed, preferably through planarization using known techniques, such as chemical-mechanical polishing (CMP) or the like. The planarization can also be used to level and smooth the remaining oxide wafer 26, if necessary.

[0066] Referring to FIG. 7, portions of the first main surface 14a of the semiconductor layer 14—regions which may be referred to as “active areas” in this embodiment—may be exposed by, for example, removing portions of the oxide wafer 26, as well as underlying portions of the trench nitride layer 24 and the trench oxide layer 22, where applicable. The layers 26, 24, 22 may be removed via chemical and/or mechanical etching techniques, polishing, grinding, or the like. Preferably, portions of the oxide wafer 26 covering and sealing the trenches 20 remain following the exposure of the active areas on the first main surface 14a of the semiconductor layer 14.

[0067] Referring to FIG. 8, device components may be formed in the active areas. For example, one or more body regions 32 proximate the first main surface 14a of the semiconductor layer 14 and adjacent the sidewalls 20a of the trenches 20 may be formed. The body regions 32 are preferably of p-type conductivity, having a dopant concentration suitable for forming inversion layers that operate as conduction channels of the device 10. In preferred embodiments, the body regions 32 are formed by depositing an oxide layer (not shown) over the first main surface 14a of the semiconductor layer 14, followed by the ion implantation of a p-type dopant (or n-type dopant) into the n and p columns 16, 18 through the oxide layer at an energy level of about 30-1000 KeV with a dose range from about 1×10.sup.10 to 1×10.sup.16 atoms cm.sup.−2, preferably from about 1×10.sup.14 to 1×10.sup.16 atoms cm.sup.−2, followed by a high temperature drive-in step (i.e., a diffusion). Other methods may be utilized as are known in the art. In addition, the body regions 32 can be formed at least partially by performing ion implantation of the sidewalls of the trenches 18. However, such a step would have to be performed prior to covering the trenches 20 with the dielectric sealing material 26, and preferably prior to formation of the trench oxide layer 22 and/or the trench nitride layer 24.

[0068] The source/drain regions 28 may also be formed proximate the first main surface 14a of the semiconductor layer 14 and within the body regions 32. The source/drain regions 28 are preferably a heavily doped n.sup.+ type region, which may be formed using techniques similar to those described above for formation of the body regions 32. The orientation of the source/drain region 28 with respect to the body region 32 is not limited and can be varied depending upon the desired configuration of the device 10. Further, there is no limit to the order in which the two regions 28, 32 may be formed. Moreover, additional regions, such as a body-contact region 30 (preferably a heavily doped p.sup.+ type region) adjacent the source/drain region 28 and within the body region 30, preferably also adjacent the sidewall 20a of the trench 20, may be formed according to the methods described above.

[0069] The gate oxide layer 36 may be formed over the active areas on the first main surface 14a of the semiconductor layer 14, and the gate nitride layer 38 may be formed over at least a portion of the gate oxide layer 36. The gate oxide and nitride layers 36, 38 may be formed according to the same techniques described above with respect to the trench oxide and nitride layers 22, 24. The gate electrode 34 is then formed over at least a portion of the gate nitride layer 38 and may be composed of, for example, a metal, a doped polysilicon, an amorphous silicon, or a combination thereof, and formed by conventional techniques.

[0070] It should be noted that while the drawings and description show the gate oxide layer 36, gate nitride layer 38, and gate electrode 34 being formed after the source/drain region 28, body-contact region 30, and body region 32, it is also possible to form the source/drain region 28 (or others) after the gate oxide layer 36, gate nitride layer 38, and gate electrode 34. Such an order can allow the source/drain region 28, for example, to self-align with the gate electrode 34. Accordingly, one skilled in the art will recognize that various steps described herein may be performed in different orders while achieving the same end result.

[0071] Referring to FIG. 9, the inter-dielectric oxide layer 40 may be formed over the gate electrode 34, and preferably between the dielectric sealing materials 26 disposed over the trenches 20. The inter-dielectric oxide layer 40 may be formed according to dielectric layer formation techniques described above (e.g., thermal growth, LPCVD or the like). The inter-dielectric oxide layer 40 (and, if necessary, the intervening dielectric sealing materials 26) may further be planarized, using CMP or the like. Contact holes (FIG. 2) may be formed in the inter-dielectric oxide layer 40 using conventional oxide etching techniques. Using methods known in the field, metallization is performed to deposit a layer of metal 42, which serves as the source/drain electrode, over the contact hole openings, and the remaining inter-dielectric oxide layer 40 and dielectric sealing material 26, thereby coupling the source/drain electrode 42 to the source/drain region 28. Passivation is performed using methods known in the field with an appropriate passivation material such as nitride, oxide or phosphosilicate glass (PSG) to arrive at the device 10 shown in FIG. 2.

[0072] FIGS. 10-14 generally show various steps of manufacturing a semiconductor device 110 (FIG. 14) according to another embodiment. Like numerals have been used for like elements, except the 100 series numerals have been used for the embodiment shown in FIGS. 10-14. Accordingly, a complete description of the embodiment has been omitted, with only the differences being described.

[0073] Referring to FIG. 10, the semiconductor layer 114 is shown as an epitaxially grown n-type layer having its second main surface 114b disposed on the semiconductor substrate 112. The source/drain regions 128, body contact regions 130, and body regions 132 are all preferably formed at the first main surface 114a of the semiconductor layer 114, in a similar configuration to those shown in the embodiment of FIG. 2, although in this embodiment, doping would occur exclusively from the first main surface 114a since the trenches 120 have yet to be formed.

[0074] The gate oxide layer 136 is formed over the first main surface 114a of the semiconductor layer 114, and the gate nitride layer 138 is formed over at least a portion of the gate oxide layer 136, at least in the regions where the gate electrode(s) 134 are to be disposed. The gate electrode 134 is thereafter formed over at least a portion of the gate nitride layer 138. The inter-dielectric oxide 140 (not shown in FIG. 10) may then be formed over the gate oxide layer 136, gate nitride layer 138, and the gate electrode 134, and planarized as necessary.

[0075] Referring to FIG. 11, the trenches 120 may be formed through the inter-dielectric oxide layer 140, the gate oxide layer 136, the gate nitride layer 138 if necessary, and at least partially through the semiconductor layer 114 from the first main surface 114a. The trenches 120 each have a sidewall 120a and a bottom 120b. The n and p columns 116, 118 are preferably thereafter formed through the techniques described above.

[0076] Referring to FIG. 12, the trench oxide layer 122 may be formed over the sidewalls 120a and bottoms 120b of the trenches 120, as well as over the inter-dielectric oxide 140 overlying the first main surface 114a of the semiconductor layer 114. The trench nitride layer 124 is then preferably formed over at least a portion of the trench oxide layer 122. In the embodiment shown in FIG. 12, the trench nitride layer 124 covers the entire trench oxide layer 122, including portions overlying the sidewalls 120a and bottoms 120b of the trenches 120, as well as over the inter-dielectric oxide 140 overlying the first main surface 114a of the semiconductor layer 114. If necessary, a thin oxide deposition (not shown) may be applied to the trench nitride layer 124.

[0077] In an alternative embodiment, shown in FIG. 17, the trench nitride layer 124′ may be removed via RIE or the like from the trench oxide layer 122′ on the bottom 120b′ of the trench 120′ and over the inter-dielectric oxide layer 140′ overlying the first main surface 114a′ of the semiconductor layer 114′. In this manner, the trench nitride layer 124′ resides only on the trench oxide layer 122′ lining the sidewall 120a′ of the trench 120′. In another alternative, the relevant surfaces may be masked to such that the trench nitride layer is only grown in desired locations, such as the trench sidewall. Thus, the coverage of the trench oxide layer by the trench nitride layer is not limited to the embodiments shown.

[0078] Referring to FIG. 13, the oxide wafer 126 may be bonded to the trench nitride layer 124 and/or trench oxide layer 122, as appropriate, proximate the inter-dielectric oxide layer 140, thereby sealing the trenches 120.

[0079] Referring to FIG. 14, the source/drain region 128 at the first main surface 114a of the semiconductor layer 114 may be exposed by forming contact holes that are preferably etched through the oxide wafer 126, the trench nitride layer 138, the trench oxide layer 136, and/or inter-dielectric oxide layer 140 (as well as any other intervening layers). The source/drain electrode 142 can then be coupled to the source/drain region 128 through the contact holes. Thus, one of the main differences of the device 110 from the second embodiment as compared to the device 10 from the first embodiment is that the trench oxide and nitride layers 122, 124 may extend over the gate electrode 134 in the second embodiment.

[0080] Embodiments described herein can be applied to all types of semiconductor devices utilizing deep trenches, and are therefore not limited just to the types of power MOSFETs described above. For example, FIG. 15 shows an integrated circuit 200 having a plurality of sealed trenches 220 separating first and second semiconductor mesas 270, 272. The first semiconductor mesa 270 includes an n column 216 preferably separated from the adjacent trenches 220 by a heavily doped n.sup.+ column 280 and a heavily doped p.sup.+ column 282. The second semiconductor mesa 272 includes a p column 218 preferably separated from the adjacent trenches 220 by a heavily doped n.sup.+ column 280 and a heavily doped p.sup.+ column 282. The semiconductor mesas 270, 272 may be disposed on a buried oxide layer 288 formed on a support wafer 290. Sidewalls 220a and bottoms 220b of the trenches 220, as well as surfaces of the mesas 270, 272 opposite to the buried oxide layer 288 may be covered with a trench oxide layer 222. The trench oxide layer 222 on the sidewalls 220a and bottoms 220b of the trenches 220 is further preferably covered by a trench nitride layer 224, which may also extend partially over the surfaces of the mesas 270, 272 covered by the trench oxide layer 222, although it is preferred that active areas be left exposed between the trenches 220. The trenches 220 are preferably sealed by dielectric sealing material 226, as described above with respect to other embodiments. The integrated circuit 200 in FIG. 15 represents an exemplary additional use for the inventive concepts described herein.

[0081] Those skilled in the art will recognize that boundaries between the above-described operations are merely illustrative. The multiple operations may be combined into a single operation, a single operation may be distributed in additional operations and operations may be executed at least partially overlapping in time. Further, alternative embodiments may include multiple instances of a particular operation, and the order of operations may be altered in various other embodiments.

[0082] While specific and distinct embodiments have been shown in the drawings, various individual elements or combinations of elements from the different embodiments may be combined with one another while in keeping with the spirit and scope of the invention. Thus, an individual feature described herein only with respect to one embodiment should not be construed as being incompatible with other embodiments described herein or otherwise encompassed by the invention.

[0083] It will be appreciated by those skilled in the art that changes could be made to the embodiments described above without departing from the broad inventive concept thereof. It is understood, therefore, that this invention is not limited to the particular embodiments disclosed, but it is intended to cover modifications within the spirit and scope of the present invention as defined by the appended claims.