DEEP REACTIVE ION ETCHING PROCESS FOR FLUID EJECTION HEADS

Abstract

An ejection head chip and method for a fluid ejection device and a method for reducing a silicon shelf width between a fluid supply via and a fluid ejector stack. The ejection head chip includes a silicon substrate and a fluid ejector stack deposited on the silicon substrate, wherein at least one metal layer of the fluid ejector stack is isolated from a fluid supply via etched in the ejection head chip by an encapsulating material.

Claims

1. An ejection head chip for a fluid ejection device comprising, a silicon substrate and a fluid ejector stack deposited on the silicon substrate, wherein at least one metal layer of the fluid ejector stack is isolated from a fluid supply via etched in the ejection head chip by an encapsulating material.

2. The ejection head chip of claim 1, wherein a silicon shelf width between the fluid supply via and the fluid ejector stack ranges from about 0 to about 20 microns.

3. The ejection head chip of claim 1, wherein the at least one metal layer comprises tantalum.

4. The ejection head chip of claim 1, wherein the fluid supply via is etched in the silicon substrate from a fluid ejector stack side of the substrate using a deep reactive ion etch (DRIE) process.

5. The ejection head chip of claim 1, wherein the fluid supply via has a minimum width ranging from about 60 to about 520 microns.

6. The ejection head chip of claim 1, wherein the encapsulating material comprises silicon oxide or silicon dioxide derived from a chemical vapor deposition of an organic silicon compound as a protective overcoat layer.

7. The ejection head chip of claim 6, wherein the encapsulating material further comprises an inter-metal dielectric layer.

8. The ejection head chip of claim 7, wherein the inter-metal dielectric layer comprises a doped or undoped diamond-like-carbon material.

9. The ejection head chip of claim 6, wherein the encapsulating material further comprises a silicon nitride layer.

10. The ejection head chip of claim 1, wherein the at least one metal layer is isolated from an edge of the fluid supply via by from about 1.5 to about 2.5 microns of encapsulating material.

11. A method for reducing a silicon shelf width between a fluid supply via and a fluid ejector stack comprising, depositing at least one insulating layer on a silicon substrate, depositing a silicon nitride layer on the at least one insulating layer, depositing a metal layer on the silicon nitride layer, encapsulating the metal layer in an encapsulating material, wherein the encapsulating material boarders two sides of the fluid supply via, applying an etch mask to the fluid ejector stack to define a location for the fluid supply via, and etching the fluid supply via in the silicon substrate with a minimum width ranging from about 60 to about 520 microns, to provide a silicon shelf having a width ranging from about 0 to about 20 microns.

12. The method of claim 11, wherein the metal layer comprises tantalum.

13. The method of claim 11, wherein the fluid supply via is etched in the silicon substrate from a fluid ejector stack side of the substrate using a deep reactive ion etch (DRIE) process.

14. The method of claim 11, wherein the encapsulating material comprises silicon oxide or silicon dioxide derived from a chemical vapor deposition of an organic silicon compound as a protective overcoat layer.

15. The method of claim 14, wherein the encapsulating material further comprises an inter-metal dielectric layer.

16. The method of claim 15, wherein the inter-metal dielectric layer comprises a doped or undoped diamond-like-carbon material.

17. The method of claim 14, wherein the encapsulating material further comprises a silicon nitride layer.

18. The method of claim 11, wherein the at least one metal layer is isolated from an edge of the fluid supply via by from about 1.5 to about 2.5 microns of encapsulating material.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0013] FIG. 1 is plan view, not to scale, of a prior art silicon wafer containing a plurality of ejection head chips for use in making fluid jet ejection heads.

[0014] FIG. 2 is a plan view, not to scale, of a prior art ejection head chip made from the silicon wafer of FIG. 1.

[0015] FIG. 3 is an enlarged plan view, not to scale, of a portion of the ejection head chip of FIG. 2.

[0016] FIGS. 4-5 are cross-sectional views, not to scale, in a y direction through the ejection head chips of FIG. 2 made according to a prior art process.

[0017] FIGS. 6-7 are cross-sectional views, not to scale, in a y direction through an ejection head chips made according to an embodiment of the disclosure.

DETAILED DESCRIPTION

[0018] As shown in FIGS. 4-5, the maximum entrance width or the fluid supply via 14 for the prior art fluid ejector stack 36 ranges from about 60 (W1) to about 520 microns (W3). Such fluid supply width is maintained in order to prevent under-etching the fluid ejector stack 36 as shown in FIG. 5 and expose the metal layer 30 to corrosion from the fluid ejected by the ejection head.

[0019] In order to better protect the metal layer 30 so that the reliance on the silicon shelf is reduced, an improved fluid ejector stack 50 for an ejection head chip 52 is provided in FIGS. 6-7. The fluid ejector stack 50 is shown in cross-sectional view in they direction through the fluid supply via 14.

[0020] Like the prior art ejection head chip 10, the ejection head chip 52 includes a first layer field oxide layer 54 adjacent to the silicon substrate 24. Next, an insulating layer 56 that may be a doped glass layer such as a phosphorus-doped silicon glass layer is deposited or grown on the field oxide layer 54. The field oxide layer 54 and insulating layer 56 have a combined thickness ranging from about 8,000 to about 30,000 Angstroms. A silicon nitride layer 58 is deposited on the insulating layer 56 as a passivation layer and underlies a portion of the metal layer 60 so that the underlying portion is between the silicon substrate 24 and the metal layer 60. The passivation layer 58 has a thickness ranging from about 1,000 to about 15,000 Angstroms. Layer 60 has a thickness ranging from about 1,500 to about 10,000 Angstroms. Next a dielectric layer 62 such as a doped or undoped diamond-like-carbon (DLC) layer is deposited on the metal layer 60 so that the metal layer 60 is totally encapsulated between the silicon nitride layer 58 and the dielectric layer 62. The dielectric layer 62 has a thickness ranging from about 2,000 to about 10,000 Angstroms. Finally, an encapsulating layer 64 that is selected from silicon oxide or silicon dioxide that is deposited on the dielectric layer 62 by a chemical vapor deposition process from an organic silicon compound. The encapsulating layer 64 has a thickness ranging from about 2,000 to about 10,000 Angstroms. The encapsulating layer 64 is also resistant to etching and acts as an etch mask during the DRIE process for forming the fluid supply vias 14. The encapsulating layer 64 may also provide a planar surface for attaching a nozzle plate or a flow feature layer containing the fluid supply channels 38 and fluid chambers 18 thereto.

[0021] As shown in FIGS. 6-7, the metal layer 60 is totally isolated from the fluid supply via 14 by the passivation layer 58 and the combination of the dielectric layer 62 and encapsulating layer 64. The encapsulating layer 64 may be selected from other materials that are resistant to the DRIE process for forming the fluid vias 14 in the ejection head chips 52. For purposes of this disclosure, the passivation layer 58, dielectric layer 62, and encapsulating layer 64 are collectively referred to as the “encapsulating material.”

[0022] A positive photoresist mask may be deposited on the encapsulating layer 64 after the encapsulating layer 64 is imaged and developed to provide a location for the fluid supply via 14. Accordingly, the positive photoresist mask may be readily aligned with the opening in the encapsulating layer 64 without having to provide a silicon shelf adjacent to both edges of the fluid supply via 14. A shelf width W6 of a silicon shelf 70 may range from about 0 to about 20 microns.

[0023] As shown in FIG. 7, even if the encapsulating layer 64 and dielectric layer 62 are undercut during DRIE process for forming the fluid supply via 14 by misalignment of the etching mask, temperature variability in the etching, or other etching process variations, the metal layer 60 remains completely isolated from the fluid flowing through the fluid supply via 14 by the silicon nitride layer 58, dielectric layer 62 and encapsulating layer 64. All three layers 58, 62 and 64 are resistant to the DRIE process and thus remain intact surrounding the metal layer 60. Accordingly, the thickness 72 of the encapsulating layer 64 adjacent to the silicon substrate 24 may range from about 6,000 to about 12,000 Angstroms. The thickness 74 of the dielectric layer adjacent to the silicon substrate 24 may also range from about 6,000 to about 12,000 Angstroms. The thickness of the silicon nitride layer 58 adjacent to the silicon substrate 24 may range from about 10,000 to about 20,000 Angstroms.

[0024] As a benefit of the use of the revised fluid ejector stack 50, the reliance on the silicon shelf width W2 for corrosion protection has been eliminated. Accordingly, instead of a target shelf width of 10 to 20 microns, the shelf width target may be 8 microns or less. However, even with the reduced shelf width target, the amount of ejection head chips that are rejected is greatly reduced, even if there is silicon substrate undercutting in the x direction, because the metal layer is totally encapsulated in the encapsulating material. Accordingly, there is less need to include the shelf width in the calculations used to determine the width W4 of the entrance of the fluid supply via 14. Thus, DRIE mask placement may use the entire opening in the encapsulating layer to reduce process setup time. Wafer inspection after DRIE etching may be simplified thereby increasing product throughput.

[0025] As an added benefit, the encapsulating material may also reduce fluid supply via edge roughness due to mask failure during the DRIE process since the encapsulating material is etch resistant. Fluid supply via edge roughness, due to wafer temperature variability during the DRIE process has been known to reduce chip strength.

[0026] It will be appreciated that the use of a reduce shelf width W5 may also reduce ejection head chip costs by reducing the overall width of the ejection head chip. For the same overall width of the ejection head chip, a wider fluid supply via 14 may be used by reducing the shelf width W5 thereby increasing the fluid refill rate to the fluid chambers which will result in faster fluid ejection cycles for higher fluid dispensing speeds.

[0027] It is noted that, as used in this specification and the appended claims, the singular forms “a,” “an,” and “the,” include plural referents unless expressly and unequivocally limited to one referent. As used herein, the term “include” and its grammatical variants are intended to be non-limiting, such that recitation of items in a list is not to the exclusion of other like items that can be substituted or added to the listed items.

[0028] While particular embodiments have been described, alternatives, modifications, variations, improvements, and substantial equivalents that are or can be presently unforeseen can arise to applicants or others skilled in the art. Accordingly, the appended claims as filed and as they can be amended are intended to embrace all such alternatives, modifications variations, improvements, and substantial equivalents.