METHOD FOR THROUGH-HOLE PLATING

Abstract

A method for plating by means of a through-hole on a semiconductor wafer at least comprising the steps: providing a semiconductor wafer having a top side and a bottom side, wherein the semiconductor wafer has a plurality of solar cell stacks and comprises a substrate on the bottom side, and each solar cell stack has at least two III-V subcells, disposed on the substrate, and at least one through-hole, extending from the top side to the bottom side of the semiconductor wafer, with a continuous side wall, wherein the through-hole has a first edge region on the top side and a second edge region on the bottom side; applying an insulating layer to part of the first edge region, the side wall, and to the second edge region by means of a first printing process; and applying an electrically conductive layer.

Claims

1. A method for plating via a through-hole in a semiconductor wafer, the method comprising: providing a semiconductor wafer having a top side and a bottom side, the semiconductor wafer having a plurality of solar cell stacks and comprises a substrate on the bottom side; providing each solar cell stack with at least two III-V subcells disposed on the substrate; and providing at least one through-hole extending from the top side to the bottom side of the semiconductor wafer with a continuous side wall, wherein the through-hole has a first edge region on the top side and a second edge region on the bottom side; applying an insulating layer to part of the first edge region, the side wall, and to the second edge region via a first printing process; and applying an electrically conductive layer via a second printing process to the insulating layer on the top side and part of the first edge region, to the insulating layer on the side wall, and to part of the insulating layer on the bottom side.

2. The method according to claim 1, wherein a paste is used to form the insulating layer and the paste comprises organic components.

3. The method according to claim 1, wherein a paste containing metal particles is used to form the conductive layer.

4. The method according to claim 1, wherein the first printing process and/or the second printing process are carried out exclusively from the front side or exclusively from the back side.

5. The method according to claim 1, wherein after the insulating layer is formed, the through-hole still has a continuous hole.

6. The method according to claim 1, wherein after the conductive layer is formed, the through-hole is partially or completely closed or the through-hole still has a continuous hole.

7. The method according to claim 1, wherein the first edge region has a different, in particular smaller, diameter than the second edge region.

8. The method according to claim 1, wherein the first edge region and the second edge region are each formed as an edge region completely surrounding the through-hole, and wherein the respective edge region parallel to the semiconductor wafer has a diameter of at least 10 μm and at most 3.0 mm, or the respective edge region parallel to the semiconductor wafer has a diameter of at least 100 μm and at most 1.0 mm.

9. The method according to claim 1, wherein the printing process is carried out via an inkjet process or a screen printing process or a dispensing process or a stencil printing process.

10. The method according to claim 1, wherein the through-hole of the semiconductor wafer has a total height of at most 500 μm and of at least 30 μm or of at most 200 μm and of at least 50 μm.

11. The method according to claim 1, wherein the through-hole of the semiconductor wafer has a circumference which is oval in cross section, in particular a round circumference.

12. The method according to claim 1, wherein the through-hole has a diameter between 25 μm and 1 mm or typically 50 μm to 300 μm prior to the use of the first printing process.

13. The method according to claim 1, wherein the diameter of the through-hole in the substrate from the top side in the direction toward the bottom side is in a first approximation or exactly the same.

14. The method according to claim 1, wherein the substrate is formed as electrically conductive and the substrate comprises germanium or GaAs or silicon or consists of one of the aforementioned materials or the substrate comprises or consists of a metal film or an electrically conductive plastic.

15. The method according to claim 1, wherein the solar cell stack has a Ge subcell.

16. The method according to claim 1, wherein part of the insulating layer on the top side is formed on a metal surface.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0048] The present invention will become more fully understood from the detailed description given hereinbelow and the accompanying drawings which are given by way of illustration only, and thus, are not limitive of the present invention, and wherein:

[0049] FIG. 1 shows a cross-sectional view of a metallized through-hole in an exemplary embodiment;

[0050] FIG. 2 shows a cross-sectional view of a metallized through-hole in a further embodiment;

[0051] FIG. 3 shows a cross-sectional view of a metallized through-hole in another embodiment;

[0052] FIG. 4a shows a top view of the top side of the metallized through-hole according to the embodiment shown in connection with the diagram in FIG. 3;

[0053] FIG. 4b shows a top view of the bottom side of the metallized through-hole according to the embodiment shown in connection with the diagram in FIG. 3;

[0054] FIG. 5 shows a top view of a semiconductor wafer with two solar cell stacks.

DETAILED DESCRIPTION

[0055] The diagrams in FIG. 1 show a cross-sectional view of a metallized through-hole 22 of a semiconductor wafer 10.

[0056] A semiconductor wafer 10 is provided having a top side 10.1, a bottom side 10.2, and a through-hole 22, which extends from top side 10.1 to bottom side 10.2, with a continuous side wall 22.1.

[0057] Semiconductor wafer 10 comprises multiple not yet separated solar cell stacks 12; in the present case, only one solar cell stack 12 is shown, in each case with a layer sequence of a substrate 14 forming bottom side 10.2, a first III-V subcell 18, and a second III-V subcell 20 forming top side 10.1.

[0058] A metal structure MV is formed on top side 10.1. The metal structure MV is formed almost exclusively as a finger-shaped structure and, in particular, in first edge region 11.1 of through-hole 22, has a continuous metal surface formed completely around through-hole 22.

[0059] A full-area backside metallization MR is formed on bottom side 10.2 so as to connect conductive substrate 14. It is understood that the particular solar cell stack 12 is electrically connected to the two metallizations MV and MR.

[0060] Through-hole 22 has a first edge region 11.1 on top side 10.1 and a second edge region 11.2 on bottom side 10.2. First edge region 11.1 is formed directly on the metal structure MV and second edge region 11.2 is formed directly on the backside metallization MR.

[0061] A part of first edge region 11.1 that is formed directly around through-hole 22, and the entire second edge region 11.2 and side wall 22.1 of through-hole 22 are coated with an insulating layer 24, wherein insulating layer 24 is formed using a first printing process. It is understood that side wall 22.1 in through-hole 22 is completely covered by insulating layer 24.

[0062] By means of a second printing process, a conductive layer 32 is applied to the entire area of first edge region 11.1 and completely to the entire area of side wall 22.1 and to a part of second edge region 11.2 that is immediately adjacent to through-hole 22. In the present case, through-hole 22 is still open even after conductive layer 32 has been formed.

[0063] Because conductive layer 32 on top side 10.1 overlaps insulating layer 24 and forms a material connection with part of the metal structure MV and on bottom side 10.2, however, covers only the part of second edge region 11.2 that is immediately adjacent to through-hole 22, a contact region for a connection of the metal structure MV is thereby formed on bottom side 10.2.

[0064] A further embodiment is shown in the diagram in FIG. 2. Only the differences from the diagram in FIG. 1 will be explained below.

[0065] In the embodiment shown, conductive layer 32 joins in the center of substrate 14 and forms an hourglass-shaped profile.

[0066] Another embodiment is shown in the diagram in FIG. 3. Only the differences from the diagram in FIG. 1 will be explained below.

[0067] In the embodiment shown, through-hole 22 is completely filled by conductive layer 32 and forms an elevation protruding from top side 10.1 and an elevation protruding from bottom side 10.2.

[0068] The diagram in FIG. 4a shows a top view of the top side of the metallized through-hole 22 according to the embodiment shown in connection with the diagram in FIG. 3.

[0069] First edge region 11.1, as part of the metal structure MV, completely encloses through-hole 22. The part of first edge region 11.1 covered with insulating layer 24 is shown dashed. It can be seen that conductive layer 22 completely covers insulating layer 24 on top side 10.1.

[0070] The diagram in FIG. 4b shows a top view of the bottom side of the metallized through-hole 22 according to the embodiment shown in connection with the diagram in FIG. 3.

[0071] Second edge region 11.2, as part of the backside metallization MR, completely encloses through-hole 22. The part of second edge region 11.2 that is covered with insulating layer 24 is now larger than the part covered with conductive layer 22. Stated differently, conductive layer 22 only partially covers insulating layer 24 on bottom side 10.2.

[0072] A plan view of a semiconductor wafer 10 having two solar cell stacks is shown in the diagram in FIG. 5. In the present case, semiconductor wafer 10 has exactly two solar cell stacks 12. It is understood that in embodiments not shown, more than two solar cell stacks 12 are also formed on semiconductor wafer 10.

[0073] The invention being thus described, it will be obvious that the same may be varied in many ways. Such variations are not to be regarded as a departure from the spirit and scope of the invention, and all such modifications as would be obvious to one skilled in the art are to be included within the scope of the following claims.