SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREFOR

Abstract

The present invention relates to a semiconductor device (10), comprising a substrate (11), a semiconductor layer (12), a stressor layer (13), an insulator barrier (14) and a plurality of electrical connectors. The semiconductor layer (12) is sandwiched between the substrate (11) and the stressor layer (13). The stressor layer (13) is on top of the semiconductor layer (12) and is capable of inducing strain on the semiconductor layer (12). A method for fabricating a semiconductor device comprises the steps of forming a substrate (110), epitaxially growing a semiconductor layer on the substrate (120), depositing a stressor layer on the semiconductor layer (130) and forming a plurality of electrical connectors (140), wherein the electrical connectors are capable of electrically connecting the semiconductor device to an external circuit.

Claims

1. A semiconductor device (10), comprising: (a) a substrate (11); (b) at least one stressor layer (13); and (c) at least one semiconductor layer (12) sandwiched between said substrate (11) and said stressor layer (13), characterized in that an insulator barrier (14) provided on said substrate (11) defines a cavity (15), such that said semiconductor layer (12) and said stressor layer (13) are confined to said cavity.

2. The semiconductor device (10) of claim 1, wherein said barrier (14) forms a perimeter around said cavity (15) and said substrate (11) forms a bottom of said cavity (15).

3. The semiconductor device (10) of claim 1, wherein a plurality of electrical connectors electrically connects said semiconductor device (10) to an external circuit.

4. The semiconductor device (10) of claim 1, wherein said semiconductor layer (12) is capable of absorbing an electromagnetic radiation.

5. The semiconductor device (10) of claim 1, wherein said semiconductor layer (12) is capable of emitting an electromagnetic radiation.

6. The semiconductor device (10) of claim 1, wherein said stressor layer (13) is formed by chemical vapor deposition of a complementary metal oxide semiconductor process-compatible dielectric.

7. The semiconductor device (10) of claim 6, wherein said complementary metal oxide semiconductor process-compatible dielectric is silicon nitride.

8. The semiconductor device (10) of claim 1, wherein thickness of said stressor layer (13) is within a range of 10-1500 nanometers.

9. The semiconductor device (10) of claim 1, wherein said semiconductor device (10) is at least one of a light emitting diode, a laser diode and a photodiode.

10. A method (100) for fabricating a semiconductor device, comprising the steps of: (a) forming a substrate (110); (b) epitaxially growing at least one semiconductor layer on said substrate (120); (c) depositing at least one stressor layer on said semiconductor layer (130), characterized in that epitaxially growing said semiconductor layer includes forming an insulator barrier on said substrate to define a cavity, such that said semiconductor layer and said stressor layer are confined to said cavity.

11. The method (100) of claim 9, wherein said barrier forms a perimeter around said cavity while said substrate forms a bottom of said cavity.

12. The method (100) of claim 9, further comprising the step of forming a plurality of electrical connectors (140), wherein the connectors are capable of electrically connecting said semiconductor device to an external circuit.

13. The method (100) of claim 9, wherein said step of depositing includes depositing a complementary metal oxide semiconductor process-compatible dielectric on said semiconductor layer by means of chemical vapor deposition.

14. The method (100) of claim 9, further comprising the step of removing excess stressor layer, such that a combined thickness of said semiconductor layer and said stressor layer does not exceed a depth of said cavity.

15. The method (100) of claim 9, wherein said step of removing excess stressor layer includes chemical mechanical polishing process and/or chemical etching process.

16. The method (100) of claim 9, wherein thickness of said stressor layer is within a range of 10-1500 nanometers.

Description

BRIEF DESCRIPTION OF THE ACCOMPANYING DRAWINGS

[0015] The present invention will be fully understood from the detailed description given herein below and the accompanying drawings which are given by way of illustration only, and thus are not limitative of the present invention, wherein:

[0016] In the appended drawings:

[0017] FIG. 1 shows a cross sectional view of the semiconductor device, in accordance with an exemplary embodiment of the present invention;

[0018] FIGS. 2A-2E show cross sectional view of the semiconductor device during fabrication process, in accordance with an exemplary embodiment of the present invention; and

[0019] FIG. 3 shows a flow diagram of the method for fabricating a stressor layer for the semiconductor device, in accordance with an exemplary embodiment of the present invention; and

[0020] FIG. 4 shows a graphical representation of photocurrent responsivity of a germanium photodiode subjected to different strain levels.

DETAILED DESCRIPTION OF THE INVENTION

[0021] Detailed description of preferred embodiments of the present invention is disclosed herein. It should be understood, however, that the embodiments are merely exemplary of the present invention, which may be embodied in various forms. Therefore, the details disclosed herein are not to be interpreted as limiting, but merely as the basis for the claims and for teaching one skilled in the art of the invention. The numerical data or ranges used in the specification are not to be construed as limiting. The following detailed description of the preferred embodiments will now be described in accordance with the attached drawings, either individually or in combination.

[0022] The present invention relates to a semiconductor device and a method for fabricating the semiconductor device. The device comprises a semiconductor layer and a stressor layer stacked on a substrate and confined to a cavity defined by an insulator barrier formed on the substrate. Confinement of the stressor layer to the cavity prevents cracking of the stressor layer, and thus fabrication of the stressor layer of desired thickness, which induces a desired strain on the semiconductor layer. Thereby, the present invention allows achieving desired radiation absorption or emission characteristics without a need for changing conditions of fabricating the semiconductor device, and thus reducing a cost and complexity of the fabrication process, while minimizing damages during fabrication.

[0023] Referring to the accompanying drawings, FIG. 1 shows a cross sectional view of a semiconductor device (10), in accordance with an exemplary embodiment of the present invention. The device (10) comprises a substrate (11), a semiconductor layer (12), a stressor layer (13), an insulator barrier (14) and a plurality of electrical connectors (not shown). Preferably, the substrate (11) is a silicon-on-insulator (SOI) substrate formed as a flat support layer, as shown in FIG. 2A, for supporting components formed thereon. Alternatively, the substrate may also be a silicon substrate, wherein additional layers of semiconductor or insulator material may be formed on the silicon substrate before forming the semiconductor layer (12). The semiconductor layer (12) is epitaxially grown on top of the substrate (11) and is capable of absorbing or emitting an electromagnetic radiation such as near infrared radiation and visible light radiation. In a preferred embodiment, the device (10) is a germanium (Ge) photodiode and the semiconductor layer (12) is a Ge layer epitaxially grown on the substrate (11) by a chemical vapor deposition (CVD) process such as ultra-high vacuum CVD (UI-IVCVD), reduced pressure CVD (RPCVD) and atmospheric-pressure CVD (APCVD). Alternatively, the device (10) may be a light emitting diode (LED), laser diode, photovoltaic cell, sensor and neutron detector, and the semiconductor layer (12) may be a layer of silicon (Si), SiGe, silicon carbide (SiC), gallium arsenide (GaAs), aluminum GaAs (AlGaAs), gallium nitride (GaN), aluminum GaN (AlGaN), indium phosphide (InP), indium GaAs phosphide (InGaAsP) or a combination of two or more semiconductors. Similarly, the semiconductor layer (12) may be grown on the substrate (11) by means of a molecular beam epitaxy (MBE) process.

[0024] The stressor layer (13) is on top of the semiconductor layer (12) such that the semiconductor layer (12) is sandwiched between the stressor layer (13) and the substrate (11). The stressor layer (13) induces strain on the semiconductor layer (12), wherein the amount of induced strain is directly proportion to thickness of the stressor layer (13). Preferably, the thickness of the stressor layer (13) is within a range of 10-1500 nanometers (nm). In case of multiple stressor layers, the amount of induced strain is directly proportion to combined thickness of the stressor layers. Preferably, the stressor layer (13) is a single layer of complementary metal oxide semiconductor (CMOS) process-compatible dielectric, more preferably silicon nitride (SiN) layer. Alternatively, the stressor layer (13) is made of any other conventional CMOS process-compatible dielectric such as silicon dioxide, silicon oxynitride and boron. The stressor layer (13) is formed by chemical vapor deposition (CVD) such as plasma enhanced CVD (PECVD) and low pressure CVD (LPCVD), of the CMOS process-compatible dielectric. However, the stressor layer (13) may also be formed of by means of a sputtering process like reactive radio frequency (RF) magnetron sputtering process.

[0025] The insulator barrier (14) provided on the substrate (11) defines a cavity (15), as shown in FIG. 2B. The barrier (14) forms a perimeter around the cavity (15) while the substrate (11) forms a bottom of the cavity (15), such that the semiconductor layer (12) and the stressor layer (13) are confined to the cavity (15), as shown in FIG. 2D. Preferably, the barrier (14) is formed of silicon dioxide (SiO.sub.2). Alternatively, any other conventional insulator material can be used for forming the barrier (14). Preferably, the barrier (14) may be ring-shaped. Alternatively, the barrier (14) can also be of polygonal shape, oval shape or any other shape capable of defining the cavity (15). Similarly, a cross section of the cavity (15) may be polygonal shaped or curved. A maximum width of the stressor layer (13) and the semiconductor layer (12) do not exceed that of the cavity (15). Furthermore, the stressor layer (13) is configured in such a way that a combined thickness of the semiconductor layer (12) and the stressor layer (13) does not exceed depth of the cavity (15), as shown in FIG. 1.

[0026] Confinement of the stressor layer (13) to the cavity (15) prevents cracking which is often seen when the thickness of the stressor layer exceeds a few hundred nanometers (nm), in particular 200 nm. Thus, the present invention allows increasing the thickness of the stressor layer (13) beyond 200 nm without cracking by increasing the depth of the cavity (15), which in turn increases the strain induced on the semiconductor layer (12). Furthermore, the increased strain enhances absorption or emission capability of the semiconductor layer (12). By this way, the present invention allows achieving desired radiation absorption or emission characteristics without a need for changing conditions of fabricating the semiconductor device, and thus a semiconductor device with desired characteristics can be fabricated in a simple and inexpensive manner, while minimizing damages during fabrication.

[0027] FIG. 3 shows a flow diagram of a method for fabricating a stressor layer for a semiconductor device, in accordance with an exemplary embodiment of the present invention. The method (100) comprises the steps of: (a) forming a substrate (110), epitaxially growing a semiconductor layer on the substrate (120), depositing a stressor layer on the semiconductor layer (130) and forming a plurality of electrical connectors (140). Preferably, the semiconductor device is germanium (Ge) photodiode and the substrate is a silicon-on-insulator (SOI) substrate, wherein a portion of a top surface of the substrate is heavily doped with impurities while forming the substrate. Similarly, a portion of a top surface of the semiconductor layer is heavily doped with impurities of opposite type. Preferably, doping density in these heavily doped portions is about 10.sup.20 atoms per cubic centimeter. Alternatively, the doping density may be varied according to the materials used for forming the substrate and the semiconductor layer. However, if the substrate is doped with p-type impurities, the semiconductor layer is doped with n-type impurities and vice versa. Furthermore, the semiconductor device may also be a semiconductor diode, laser diode, light emitting diode, photovoltaic cell, sensor or neutron detector, and the substrate may be a silicon substrate formed with doped regions.

[0028] In a preferred embodiment, he semiconductor layer is a Ge layer capable of absorbing near infrared radiation. Alternatively, the semiconductor layer may be a layer of silicon (Si), SiGe, silicon carbide (SiC), gallium arsenide (GaAs), aluminum GaAs (AlGaAs), gallium nitride (GaN), aluminum GaN (AlGaN), indium phosphide (InP), indium GaAs phosphide (InGaAsP) or a combination of two or more semiconductors, capable of emitting or absorbing an electromagnetic radiation such as visible light radiation.

[0029] Preferably, the stressor layer is deposited by means of chemical vapor deposition (CVD) such as plasma enhanced CVD (PECVD) and low pressure CVD (LPCVD). Furthermore, the stressor layer is formed by depositing a complementary metal oxide semiconductor (CMOS) dielectric, preferably Si nitride (SiN), on the SOI substrate by CVD process. The stressor layer is capable of inducing strain on the semiconductor layer, wherein the strain influences a radiation absorption or emitting capability of the semiconductor layer. For example, if the semiconductor layer is a Ge layer, then the induced strain may reduce a direct bandgap of the germanium from the bulk value of 0.80 electronvolt (eV), which in turn enhances absorption at longer wavelengths into the L-band.

[0030] In a preferred embodiment, during epitaxially growing the semiconductor layer, an insulator barrier is formed on the substrate to define a cavity wherein the barrier forms a perimeter of the cavity and the substrate forms a bottom of the cavity, such that the semiconductor layer and the stressor layer are confined to the cavity. The barrier may be formed as a ring-, polygonal- or elliptical shaped and a cross section of the cavity may be formed as a box-shaped, curved or V-shaped.

[0031] Furthermore, excess stressor layer is removed, such that a combined thickness of the semiconductor layer and the stressor layer does not exceed a depth of the cavity, as shown in FIG. 1. Preferably, the excess stressor layer is removed by chemical mechanical polishing (CMP). More preferably, a CMP slurry with high Si.sub.3N.sub.4:SiO.sub.2 selectivity is used to remove the excess stressor layer, such that a top portion of the stressor layer and a top portion of the insulator barrier form a single flat surface. Additionally, the electrical connectors are formed for electrically connecting the semiconductor device to an external circuit, more particularly for connecting the semiconductor layer and the substrate to the external circuit. The external circuit may be any conventional power source, controlling devices, photonic devices and the like. The electrical connectors are connected to the semiconductor layer and the substrate by forming holes through the stressor layer or the insulator barrier and inserting a conductive material through the holes to make electrical contact with the semiconductor layer and the substrate. Furthermore, the connectors may include bond pads positioned on top or side surface of the semiconductor device.

[0032] The insulator barrier functions to confine the semiconductor layer within the cavity while growing the semiconductor layer on the substrate and to confine the stressor layer to the cavity while depositing the stressor layer on top of the semiconductor layer, such that a maximum width of the stressor layer and the semiconductor layer do not exceed a maximum width of the cavity. Furthermore, a combined thickness of the semiconductor layer and the stressor layer does not exceed a depth of the cavity.

[0033] Confinement of the stressor layer to the cavity prevents cracking which is often seen when thickness of the stressor layer exceeds a few hundred nanometers, especially when exceeds 200 nm. Thus, thickness of the stressor layer can be increased without cracking by increasing a depth of the cavity, which in turn increases the strain induced on the semiconductor layer without damaging the stressor layer. Furthermore, the increased strain enhances absorption or emission capability of the semiconductor layer. By this way, the present invention allows manufacture of semiconductor device with desired radiation absorption or emission characteristics in a simple and inexpensive manner without a need for changing conditions of fabricating the semiconductor device, while minimizing damages during fabrication.

[0034] Even though the above embodiments show the present invention being implemented for inducing strain on a semiconductor layer to modify its radiation absorption or emitting properties, it is to be understood that the present invention may also be applied for modifying any other semiconductor properties that can be modified when the bandgap of the semiconductor layer is reduced by externally inducing strain. It includes but not limited to electron mobility, laser states, transistor switching speeds and photon absorption.

[0035] The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting. As used herein, the singular forms “a”, “an” and “the” may be intended to include the plural forms as well, unless the context clearly indicates otherwise. The terms “comprises”, “comprising”, “including” and “having” are inclusive and therefore specify the presence of stated features, integers, steps, operations, elements and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and/or groups thereof.

[0036] The method steps, processes and operations described herein are not to be construed as necessarily requiring their performance in the particular order discussed or illustrated, unless specifically identified as an order of performance. It is also to be understood that additional or alternative steps may be employed. The use of the expression “at least” or at “least one” suggests the use of one or more elements, as the use may be in one of the embodiments to achieve one or more of the desired objects or results.