Single inductor dual input buck converter with reverse capability

Abstract

The present document relates to Single Inductor Dual Input (SIDI) buck power converters. More specifically, a dual input power converter may comprise an inductor, a first high-side switching element, a second high-side switching element, and a low-side switching element. The inductor may be coupled between an intermediate node and an output of the dual input power converter. The first high-side switching element may be coupled between a first input of the dual input power converter and the intermediate node. The second high-side switching element may be coupled between a second input of the dual input power converter and the intermediate node. The low-side switching element may be coupled between the intermediate node and a reference potential.

Claims

1. A dual input power converter comprising an inductor coupled between an intermediate node and an output of the dual input power converter; a first switching element coupled between a first input of the dual input power converter and the intermediate node; a second switching element coupled between a second input of the dual input power converter and the intermediate node; and a low-side switching element coupled between the intermediate node and a reference potential, wherein the dual input power converter is configured to: down-convert, during a first buck operation state, a first input voltage at the first input to an output voltage at the output, down-convert, during a second buck operation state, a second input voltage at the second input to the output voltage at the output; and up-convert, during a back-boost operation state, the output voltage to the second input voltage, wherein the back-boost operation state comprises a first sub-state and a second sub-state, and wherein the dual input power converter is configured to: during the first sub-state, open the first switching element, open the second switching element, and close the low-side switching element; and during the second sub-state, open the first switching element, and open the low- side switching element.

2. The dual input power converter of claim 1, further comprising a storage capacitor coupled to the second input, wherein the dual input power converter is configured to switch from the first buck operation state to the back-boost operation state when a voltage across said storage capacitor falls below a target voltage.

3. The dual input power converter of claim 1, wherein the dual input power converter is configured to generate, during the back-boost operation state, a negative inductor current flowing from the output, via the inductor, via the intermediate node, via the second switching element to the second input.

4. The dual input power converter of claim 1, wherein the dual input power converter is configured to switch from the first sub-state to the second sub-state when a current through the low-side switching element reaches a threshold current.

5. The dual input power converter of claim 1, wherein the dual input power converter is configured to, during the first buck operation state, alternately establish a magnetizing current path from the first input, via the first switching element, via the inductor to the output, and a demagnetizing current path from the reference potential, via the low-side switching element, via the inductor, to the output.

6. The dual input power converter of claim 1, further comprising a fourth switching element coupled between first switching element and said intermediate node, wherein the dual input power converter is configured to close the fourth switching element during the first buck operation state, and to open the fourth switching element during the back-boost operation state.

7. The dual input power converter of claim 1, wherein the dual input power converter is configured to switch from the first buck operation state to the second buck operation state if the input voltage falls below a threshold voltage.

8. A method of operating a dual input power converter comprising coupling an inductor between an intermediate node and an output of the dual input power converter; coupling a first switching element between a first input of the dual input power converter and the intermediate node; coupling a second switching element between a second input of the dual input power converter and the intermediate node; and coupling a low-side switching element between the intermediate node and a reference potential, wherein the method further comprises: down-converting, during a first buck operation state, a first input voltage at the first input to an output voltage at the output, down-converting, during a second buck operation state, a second input voltage at the second input to the output voltage at the output; and up-converting, during a back-boost operation state, the output voltage to the second input voltage, wherein the back-boost operation state comprises a first sub-state and a second sub-state, and wherein the method further comprises: during the first sub-state, opening the first switching element, opening the second switching element, and closing the low-side switching element; and during the second sub-state, opening the first switching element, and opening the low-side switching element.

9. The method of claim 8, wherein the dual input power converter further comprises a storage capacitor coupled to the second input, and wherein the method comprises switching from the first buck operation state to the back-boost operation state when a voltage across said storage capacitor falls below a target voltage.

10. The method of any one of claims 8, wherein the method comprises generating, during the back-boost operation state, a negative inductor current flowing from the output, via the inductor, via the intermediate node, via the second switching element to the second input.

11. The method of claim 8, wherein the method comprises switching from the first sub-state to the second sub-state when a current through the low-side switching element reaches a threshold current.

12. The method of any one of claims 8, wherein the method comprises, during the first buck operation state, alternately establishing a magnetizing current path from the first input, via the first switching element, via the inductor to the output, and a demagnetizing current path from the reference potential, via the low-side switching element, via the inductor, to the output.

13. The method of any one of claims 8, wherein the dual input power converter comprises a fourth switching element coupled between first switching element and said intermediate node, and wherein the method comprises closing the fourth switching element during the first buck operation state, and opening the fourth switching element during the back-boost operation state.

14. The method of any one of claims 8, wherein the method comprises switching from the first buck operation state to the second buck operation state if the input voltage falls below a threshold voltage.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The present invention is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings in which like reference numerals refer to similar or identical elements, and in which

(2) FIG. 1 shows a power tree of an SSD module with PLP capability;

(3) FIG. 2 shows transient voltages in case of a power loss event;

(4) FIG. 3 shows an exemplary SIDI buck power converter;

(5) FIG. 4 shows another block diagram of the exemplary SIDI buck power converter with hold-up voltage monitoring to enable/disable back-boost operation;

(6) FIG. 5 shows an exemplary timing diagram of the inductor current I.sub.L and the control signals during a buck operation state and a back-boost operation state;

(7) FIG. 6 shows a timing diagram of the hold-up voltage V.sub.H; and

(8) FIG. 7 shows a method of use for a single inductor dual input buck converter with reverse boost capability.

DETAILED DESCRIPTION

(9) FIG. 3 shows an exemplary SIDI buck power converter 3 able to operate as a pre-regulator as well as a PLP device. It comprises an inductor 30 coupled between an intermediate node 35 and an output of the power converter 3. A switch S1 (first high-side switching element 31) is coupled between a first input and the intermediate node 35. A switch S3 (second high-side switching element 33) is coupled between a second input of the power converter 3 and the intermediate node 35. A switch S2 (low-side switching element 32) is coupled between the intermediate node 35 and a reference potential. The power converter 3 may comprise a switch S4 (fourth high-side switching element 34) coupled between switch S1 and the intermediate node 35. Switches S1 and S4 connect to the input voltage V.sub.IN, and switch S3 connects to the hold-up voltage V.sub.H. At the first input, an input capacitor C.sub.IN 37 may stabilize the input voltage V.sub.IN. At the second input, a hold-up (or storage) capacitor C.sub.H 36 may store energy for powering the PMIC at the output of the power converter 3 in case of a power loss event. At the output of the power converter 3, an output capacitor C.sub.OUT 38 may stabilize the output voltage V.sub.OUT_PRE.

(10) When V.sub.IN is connected, switches S1 and S2 are switching, i.e. V.sub.IN is down-converted to V.sub.OUT_PRE by alternately switching S1 and S2 on and off with a PWM control. Meanwhile, switch S4 may be maintained closed. If V.sub.IN is disconnected, the switch S3 may start switching, and V.sub.H is down-converted to V.sub.OUT_PRE by switching switches S3 and S2 with a PWM control. In addition, switch S4 isolates V.sub.IN, thereby preventing reverse leakage current.

(11) FIG. 4 shows another block diagram of the exemplary SIDI buck power converter 3 with hold-up voltage monitoring to enable/disable back-boost operation. While V.sub.IN is present, if the voltage on C.sub.H drops below the target voltage V.sub.H_REF of the storage capacitor 36, the hold-up capacitor voltage C.sub.H is regulated/increased by periodically allowing the inductor current to become negative so that it flows into the hold-up capacitor C.sub.H involving switches S2 and S3. For this purpose, the exemplary SIDI buck power converter 3 may comprise a comparator 41 and a control unit 42 for generating corresponding control signals for controlling the switches S1 to S4. Control unit 42 may also receive a feedback signal indicative for the output voltage V.sub.OUT_PRE, and control unit 42 may be configured to regulate the output voltage V.sub.OUT_PRE.

(12) FIG. 5 shows an exemplary timing diagram of the inductor current I.sub.L and the control signals during a (first) buck operation state 51 and a back-boost operation state 52 of the exemplary power converter 3. During the buck operation state 51, switches S1 and S2 are switching to regulate the output voltage by magnetizing and demagnetizing the inductor 30. At time 511, the power converter switches from the (first) buck operation state 51 to the back-boost operation state 52 for charging the hold-up capacitor 36. Within this document, the back-boost operation state may also be denoted as top-up cycle, and such a top-up cycle may be triggered by a top-up event triggered by comparator 41 by generating a so-called TOPUP_gating signal. As shown in FIG. 5, the back-boost operation state 52 comprises a first sub-state 521 during which I.sub.L is decreasing until a (negative) threshold current −1.sub.PEAK_N is reached. In other words, the de-magnetization phase of the buck operation state is prolonged by keeping switch S2 closed and by allowing the inductor current to reach the negative limit value −1.sub.PEAK_N. In the subsequent, second sub-state 522 of the back-boost operation state 522, once switch S2 is open, the inductor current is going to flow into hold-up capacitor C.sub.H through the body diode of switch S3. Switch S3 may be then closed to reduce losses. Switch S3 is maintained close until the current reaches a value of e.g. zero. The normal buck operation state may then be resumed by magnetizing the inductor by closing switches S1 and S4.

(13) If the Top-Up Request Happens with a Period N.sub.TOPUPT.sub.SW (T.sub.SW is the Switching Period), the charge provided by a single top-up event Q.sub.TOPUP should be higher than the charge loss due to the capacitor leakage current I.sub.LEAK during the same period:
Q.sub.TOPUP<Q.sub.LEAK  (1)

(14) Here, the capacitor leakage current I.sub.LEAK denotes the self-discharge of the hold-up capacitor C.sub.H. In FIG. 5, the top-up charge provided to C.sub.H during top-up cycle is equal to:
Q.sub.TOPUP=I.sub.PEAK_N.Math.ΔT/2  (2)

(15) On the other hand, the charge loss due to leakage can be calculated as:
Q.sub.LEAK=I.sub.LEAK=.Math.N.sub.TOPUP.Math.T.sub.SW  (3)

(16) FIG. 6 shows a timing diagram of the hold-up voltage V.sub.H. Once the voltage V.sub.H drops with respect to the reference by an amount higher than the comparator hysteresis V.sub.HYST, the top-up action is enabled by asserting the signal TOPUP_gating. The top-up happens at an interval N.sub.TOPUPT.sub.SW as defined by the signal TOPUP_REQ (internal to the SIDI controller). The top-up request can have a lower priority by design with respect to the normal buck operation. Also, a signal from outside could be used to disable the top-up action of the SIDI.

(17) The voltage rating of the power FETs used in the SIDI power converter 3 is determined by the voltages used for V.sub.IN and V.sub.H: switches S2, S3 and S4 should be V.sub.H-rated, while switch S1 needs to be V.sub.IN-rated.

(18) FIG. 7 shows 700, a method for operating a dual input power converter is described. The method may comprise 710, coupling an inductor between an intermediate node and an output of the dual input power converter. The method may comprise 720, coupling a first switching element between a first input of the dual input power converter and the intermediate node. The method may comprise 730, coupling a second switching element between a second input of the dual input power converter and the intermediate node. The method may comprise 740, coupling a low-side switching element between the intermediate node and a reference potential.

(19) It should be noted that the description and drawings merely illustrate the principles of the proposed methods and systems. Those skilled in the art will be able to implement various arrangements that, although not explicitly described or shown herein, embody the principles of the invention and are included within its spirit and scope. Furthermore, all examples and embodiment outlined in the present document are principally intended expressly to be only for explanatory purposes to help the reader in understanding the principles of the proposed methods and systems. Furthermore, all statements herein providing principles, aspects, and embodiments of the invention, as well as specific examples thereof, are intended to encompass equivalents thereof.