RECTIFIER FOR MILLIMETER-WAVE AC VOLTAGE SIGNALS

Abstract

A rectifier cell for rectifying an electrical AC voltage, which rectifier cell comprises a transistor series circuit having a first field effect transistor and a second field effect transistor. A first frequency-independent voltage divider connected in parallel with the transistor series circuit has a first node which is connected to the gate electrode of the first field effect transistor. A second frequency-independent voltage divider connected in parallel with the transistor series circuit has a second node which is connected to the gate electrode of the second field effect transistor. In this case, the first and the second node of the frequency-independent voltage dividers are additionally each connected to earth via a bias capacitor.

Claims

1-10. (canceled)

11. A rectifier cell for rectifying an electrical AC voltage, comprising: a transistor series connection having a first field effect transistor and a second field effect transistor, a node arranged between the first and the second field effect transistor being connected via an input capacitor to an input node at which an electrical AC voltage can be applied, a first frequency-independent voltage divider connected in parallel to the transistor series connection and having a first node connected to the gate electrode of the first field effect transistor, a second frequency-independent voltage divider connected in parallel to the transistor series connection having a second node connected to the gate electrode of the second field effect transistor, the first and the second node of the frequency-independent voltage dividers each also being connected to ground via at least one bias capacitor.

12. The rectifier cell according to claim 11, wherein at least one frequency-independent voltage divider is formed with at least two series-connected bias resistors which are designed as components.

13. The rectifier cell according to claim 12, wherein at least one of said at least two series-connected bias resistors of a frequency-independent voltage divider has an ohmic resistance of at least 10 kOhm for limiting the current flowing through the frequency-independent voltage divider.

14. The rectifier cell according to claim 11, wherein said at least one bias capacitor has a capacitance of at least 1 pF for filtering high-frequency signal components.

15. The rectifier cell according to claim 11, wherein the rectifier cell is manufactured in integrated silicon-on-insulator (SOI) technology and the transistor series connection is formed with an NMOS transistor as a first field effect transistor and a PMOS transistor as a second field effect transistor, wherein the NMOS transistor and the PMOS transistor are arranged in a cascading manner with respect to their respective forward current direction and the drain electrode of the NMOS transistor is connected to the drain electrode of the PMOS transistor.

16. The rectifier cell according to claim 11, wherein the source electrode of the first field effect transistor is connected to ground via a first output node and/or the source electrode of the second field effect transistor is connected to a load and/or a storage capacitor.

17. The rectifier cell according to claim 11, wherein the input capacitor is formed with a metal-oxide-metal capacitor (MOM).

18. A rectifier formed with at least one rectifier cell according to claim 11, wherein bulk connections of the field effect transistors of the at least one rectifier cell are connected to output nodes of an auxiliary charge pump coupled to an oscillator.

19. A rectifier formed with at least two coupled rectifier cells according to claim 11, wherein a source electrode of the second field effect transistor of a first rectifier cell is connected to a source electrode of the first field effect transistor of a second rectifier cell.

20. A use of a rectifier formed with at least two series-connected rectifier cells according to claim 11, which rectifier is integrated in an RFID transponder for providing a DC voltage for supplying a load having a load resistance of at least 20 kOhm by rectifying an AC voltage signal present at the input node having a carrier frequency of at least 50 GHz and an average power between −5 dBm and −1 dBm available at the input node.

Description

[0031] Exemplary embodiments of the invention are shown in the drawings and are explained in more detail below with reference to FIGS. 1 and 2.

[0032] Shown are

[0033] FIG. 1 a schematic illustration of an electronic circuit showing a rectifier cell according to the invention, and

[0034] FIG. 2 a schematic illustration of an electronic circuit showing a rectifier according to the invention formed with a plurality of rectifier cells.

[0035] FIG. 1 shows a rectifier cell 1 having a transistor series connection, which shows a first field effect transistor 2 designed as an NMOS transistor, which has a bulk connection 9, and a second field effect transistor 3 designed as a PMOS transistor, which has a bulk connection 10. The drain electrode of the first field effect transistor 2 is connected to the drain electrode of the second field effect transistor 3 via a node, wherein the node is connected to the input node 5 via an input capacitor 4 designed as a MOM capacitor. The NMOS transistor 2 and the PMOS transistor 3 form a transistor series connection cascaded in the forward direction.

[0036] Particularly, an AC voltage signal having a carrier frequency in the millimeter waveband that is greater than 50 GHz can be present at the input node 5.

[0037] The source electrode of the NMOS transistor 2 is connected to the source electrode of the PMOS transistor 3 via a first frequency-independent voltage divider 6 formed with two series-connected bias resistors 6.1, 6.2, and via a second frequency-independent voltage divider 7 also formed with two series-connected bias resistors 7.1, 7.2. Both the first and the second frequency-independent voltage dividers 6, 7 are arranged in parallel with the transistor series connection. The bias resistors 6.1, 6.2, 7.1, 7.2 are each designed as a component having an ohmic resistance of more than 10 kOhm.

[0038] A first node arranged between the two bias resistors 6.1, 6.2 of the first frequency-independent voltage divider 6 is connected to the gate electrode of the NMOS transistor 2 and connected to ground via a bias capacitor 8.1 having a capacitance of 1 pF. A second node arranged between the two bias resistors 7.1, 7.2 of the second frequency-independent voltage divider 7 is connected to the gate electrode of the PMOS transistor 3 and connected to ground via a bias capacitor 8.2 having a capacitance of 1 pF. The DC voltage present at the output nodes 11, 12 can be used as a supply voltage by an application, for example, by a load having a power resistor.

[0039] FIG. 2 shows a rectifier formed with a plurality of coupled rectifier cells 1, an auxiliary charge pump 13 with the output nodes 13.1, 13.2, an oscillator 14 and a storage capacitor 16. Recurring features are provided in this figure with the same reference numerals as in FIG. 1. The storage capacitor 16 has a capacitance of 6.2 nF. A load 15 can be connected to the source electrode of a PMOS transistor and/or to the output node 12. The rectifier cells 1 are connected to the input node 5 so that the input power of each rectifier cell 1 corresponds to at least part of the input power of an AC voltage signal present at the input node 5.

[0040] The rectifier cells 1 are coupled to one another such that a source electrode of the NMOS transistor 2 of a first rectifier cell 1 is connected to ground and a source electrode of the PMOS transistor 3 of a second rectifier cell 1 is connected to the storage capacitor 16. Further rectifier cells 1 can be arranged between the first and the second rectifier cell 1.

[0041] The bulk connections 9, 10 of the rectifier cells 1 are connected to the output nodes 13.1, 13.2 of the auxiliary charge pump 13. The oscillator 14 regulates the charge transfer of the auxiliary charge pump 13 by periodically switching over at least one switch of the auxiliary charge pump 13. The use of an auxiliary charge pump 13 regulated by an oscillator 14 also makes it possible to effectively compensate for the threshold voltage.

[0042] The number of coupled rectifier cells 1 can be selected as a function of the load resistance of the load 15 and the input power of the AC voltage signal applied to the input node 5. For example, the rectifier shown in FIG. 2 for an AC voltage signal having a carrier frequency of 61 GHz and an input power between −5 dBm and −1 dBm and a load resistance of 10 kOhm can be formed with two coupled rectifier cells 1. The efficiency of the rectifier can be greater than 2% and the DC voltage achieved can be more than 300 mV. With a load resistance of 50 kOhm, however, it is recommended to form a rectifier with three coupled rectifier cells 1. The efficiency of the rectifier can be greater than 0.7% and the DC voltage achieved can be more than 400 mV. With a load resistance of 1 kOhm and an input power of 5.2 dBm, the rectifier according to the invention can even achieve efficiencies of more than 6%.