A Differential Combiner Circuit

Abstract

A differential combiner circuit (200) comprises three ports each has two terminals (1a, 1b, 2a, 2b, 3a, 3b). The differential combiner circuit (200) further comprises a first sub-circuit comprising a first inductor (L1) connected between the first terminals (1a, 2a) of the first and second ports, and a first capacitor (C1) connected between the first terminals (2a, 3a) of the second and third ports; a second sub-circuit comprising a second inductor (L2) connected between the second terminals (1b, 2b) of the first and second ports, and a second capacitor (C2) connected between the second terminals (2b, 3b) of the second and third ports. The differential combiner circuit (200) further comprises a third capacitor (C3) connected between the first and second terminals (1a, 1b) of the first port, a third inductor (L3) connected between the first and second terminals (3a, 3b) of the third port; a first resistor (R1) connected between the first terminal (1a) of the first port and the second terminal (3b) of the third port; and a second resistor (R2) connected between the second terminal (1b) of the first port and the first terminal (3a) of the third port.

Claims

1-8. (canceled)

9. A differential combiner circuit, comprising: a first port having a first terminal and a second terminal; a second port having a first terminal and a second terminal; a third port having a first terminal and a second terminal; a first sub-circuit comprising: a first inductor connected between the first terminals of the first and second ports; and a first capacitor connected between the first terminals of the second and third ports; a second sub-circuit comprising: a second inductor connected between the second terminals of the first and second ports; and a second capacitor connected between the second terminals of the second and third ports; a third capacitor connected between the first and second terminals of the first port; a third inductor connected between the first and second terminals of the third port; a first resistor connected between the first terminal of the first port and the second terminal of the third port; and a second resistor connected between the second terminal of the first port and the first terminal of the third port.

10. The differential combiner circuit of claim 9, wherein resistances of the first and second resistors are variable or programmable.

11. The differential combiner circuit of claim 9, wherein the capacitance of the first, second, and third capacitors are variable or programmable.

12. The differential combiner circuit of claim 9, wherein the inductance of the first, second, and third inductors are variable or programmable.

13. The differential combiner circuit of claim 9, further comprising a set of variable or programmable capacitors in parallel with the first and second resistors.

14. The differential combiner circuit of claim 9, further comprising a set of variable or programmable capacitors, one of the set of variable or programmable capacitors between the first terminal of the first port and the first terminal of the third port, and one of the set of variable or programmable capacitors between the second terminal of the first port and the second terminal of the third port.

15. A transceiver for full duplex or frequency division duplex communications, comprising: a differential combiner circuit, the differential combiner circuit comprising: a first port having a first terminal and a second terminal; a second port having a first terminal and a second terminal; a third port having a first terminal and a second terminal; a first sub-circuit comprising: a first inductor connected between the first terminals of the first and second ports; and a first capacitor connected between the first terminals of the second and third ports; a second sub-circuit comprising: a second inductor connected between the second terminals of the first and second ports; and a second capacitor connected between the second terminals of the second and third ports; a third capacitor connected between the first and second terminals of the first port; a third inductor connected between the first and second terminals of the third port; a first resistor connected between the first terminal of the first port and the second terminal of the third port; and a second resistor connected between the second terminal of the first port and the first terminal of the third port; wherein the second port of the differential combiner circuit serves as an antenna port coupled to an antenna; and wherein either: the first port of the differential combiner circuit serves as a receive port coupled to a receiver and the third port of the differential combiner circuit serves as a transmit port coupled to a transmitter; or the third port of the differential combiner circuit serves as the receive port coupled to the receiver and the first port of the differential combiner circuit serves as the transmit port coupled to the transmitter.

16. The transceiver of claim 15, wherein resistances of the first and second resistors are variable or programmable.

17. The transceiver of claim 15, wherein the capacitance of the first, second, and third capacitors are variable or programmable.

18. The transceiver of claim 15, wherein the inductance of the first, second, and third inductors are variable or programmable.

19. The transceiver of claim 15, wherein the differential combiner circuit further comprising a set of variable or programmable capacitors in parallel with the first and second resistors.

20. The transceiver of claim 15, wherein the differential combiner circuit comprises a set of variable or programmable capacitors, one of the set of variable or programmable capacitors between the first terminal of the first port and the first terminal of the third port, and one of the set of variable or programmable capacitors between the second terminal of the first port and the second terminal of the third port.

21. A communication device, comprising: a transceiver for full duplex or frequency division duplex communications and having a differential combiner circuit, the differential combiner circuit comprising: a first port having a first terminal and a second terminal; a second port having a first terminal and a second terminal; a third port having a first terminal and a second terminal; a first sub-circuit comprising: a first inductor connected between the first terminals of the first and second ports; and a first capacitor connected between the first terminals of the second and third ports; a second sub-circuit comprising: a second inductor connected between the second terminals of the first and second ports; and a second capacitor connected between the second terminals of the second and third ports; a third capacitor connected between the first and second terminals of the first port; a third inductor connected between the first and second terminals of the third port; a first resistor connected between the first terminal of the first port and the second terminal of the third port; and a second resistor connected between the second terminal of the first port and the first terminal of the third port; wherein the second port of the differential combiner circuit serves as an antenna port coupled to an antenna; and wherein either: the first port of the differential combiner circuit serves as a receive port coupled to a receiver and the third port of the differential combiner circuit serves as a transmit port coupled to a transmitter; or the third port of the differential combiner circuit serves as the receive port coupled to the receiver and the first port of the differential combiner circuit serves as the transmit port coupled to the transmitter.

22. The communication device of claim 21, wherein resistances of the first and second resistors are variable or programmable.

23. The communication device of claim 21, wherein the capacitance of the first, second, and third capacitors are variable or programmable.

24. The communication device of claim 21, wherein the inductance of the first, second, and third inductors are variable or programmable.

25. The communication device of claim 21, wherein the differential combiner circuit comprises a set of variable or programmable capacitors in parallel with the first and second resistors.

26. The communication device of claim 21, wherein the differential combiner circuit comprises a set of variable or programmable capacitors, one of the set of variable or programmable capacitors between the first terminal of the first port and the first terminal of the third port, and one of the set of variable or programmable capacitors between the second terminal of the first port and the second terminal of the third port.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Examples of embodiments herein are described in more detail with reference to attached drawings in which:

[0018] FIG. 1 is a schematic view of a differential combiner circuit according to a first embodiment herein;

[0019] FIG. 2 is a schematic view of a differential combiner circuit according to a second embodiment herein;

[0020] FIG. 3 shows simulation results for the differential combiner circuit according to embodiment herein;

[0021] FIG. 4 is a circuit schematic for analysing the differential combiner circuit according to embodiment herein;

[0022] FIG. 5 shows simulation results for the differential combiner circuit according to embodiment herein when antenna impedance varies but isolation resistors kept constant;

[0023] FIG. 6 shows simulation results for the differential combiner circuit according to embodiment herein when antenna impedance varies and isolation resistors also varies;

[0024] FIG. 7 is a schematic view of a differential combiner circuit according to a third embodiment herein;

[0025] FIG. 8 shows simulation results for the differential combiner circuit according to embodiment herein shown in FIG. 7;

[0026] FIG. 9 shows simulation results for the differential combiner shown in FIG. 7 with non-ideal inductors;

[0027] FIG. 10 shows simulation results for the differential combiner shown in FIG. 7 with more fine-tuned settings of circuit parameters; and

[0028] FIG. 11 is a block diagram illustrating an electronic device in which a transceiver according to embodiments herein may be implemented.

DETAILED DESCRIPTION

[0029] FIG. 1 shows a differential combiner circuit 100 according to a first embodiment herein.

[0030] The differential combiner circuit 100 comprises two baluns 101 and 102. Each balun has a lattice structure with two inductors and two capacitors, and each balun has three terminals. The first balun 101 has two inductors L1 and L3a, two capacitors C1 and C3a, a first terminal 1a, a second terminal 2a, a third terminal 3a. The second balun 102 has two inductors L2 and L3b, two capacitors C2 and C3b, a first terminal 1b, a second terminal 2b, a third terminal 3b. In each balun, between the first terminal and a signal ground is a capacitor C3a/C3b, between the first and second terminals is an inductor L1/L2, between the second and third terminals is a capacitor C1/C2, and between the third terminal and the signal ground is an inductor L3a/L3b.

[0031] The first terminals 1a, 1b of the first and second baluns form a first port of the differential combiner circuit 100.

[0032] The second terminals 2a, 2b of the first and second baluns form a second port of the differential combiner circuit 100.

[0033] The third terminals 3a, 3b of the first and second baluns form a third port of the differential combiner circuit 100.

[0034] The differential combiner circuit 100 further comprises two resistors R1 and R2, each connected between the first terminal 1a/1b of one balun and the third terminal 3b/3a of the other, i.e. they are cross-coupled.

[0035] Since the two baluns 101, 102 will be driven with differential signals at all ports of the differential combiner circuit 100, the two capacitors C3a, C3b to signal ground may be replaced by a single capacitor C3 with half the value between the first terminals 1a, 1b of the two baluns, and the two inductors L3a, L3b to the signal ground may be replaced in the same way with an inductor L3 with twice of the value between the third terminals 3a, 3b of the two baluns. FIG. 2 shows such a differential combiner circuit 200 according to a second embodiment herein.

[0036] The differential combiner circuit 200 comprises a first port having a first terminal 1a and a second terminal 1b; a second port having a first terminal 2a and a second terminal 2b; and a third port having a first terminal 3a and a second terminal 3b.

[0037] The differential combiner circuit 200 further comprises a first sub-circuit comprising a first inductor L1 connected between the first terminals 1a, 2a of the first and second ports, and a first capacitor C1 connected between the first terminals 2a, 3a of the second and third ports.

[0038] The differential combiner circuit 200 further comprises a second sub-circuit comprising a second inductor L2 connected between the second terminals 1b, 2b of the first and second ports, and a second capacitor C2 connected between the second terminals 2b, 3b of the second and third ports.

[0039] The differential combiner circuit 200 further comprises a third capacitor C3 connected between the first and second terminals 1a, 1b of the first port, and a third inductor L3 connected between the first and second terminals 3a, 3b of the third port.

[0040] The differential combiner circuit 200 further comprises a first resistor R1 connected between the first terminal 1a of the first port and the second terminal 3b of the third port, and a second resistor R2 connected between the second terminal 1b of the first port and the first terminal 3a of the third port.

[0041] As can be seen, the differential combiner circuit 200 according to the embodiments herein is implemented with a core of three inductors, three capacitors and two resistors. In the differential combiner circuit 200, two balun structures are formed. The first balun comprises the first sub-circuit with L1, C1, and a half of the third capacitor C3 with twice of the capacitance and a half of the third inductor L3 with half of the inductance. The second balun comprises the second sub-circuit with L2, C2, and a half of the third capacitor C3 with twice of the capacitance and a half of the third inductor L3 with half of the inductance. The second port of the differential combiner circuit 200 may serve as an antenna port coupled to an antenna. The first port of the differential combiner circuit 200 may serve as a receive RX port coupled to a receiver and the third port of the differential combiner circuit 200 may serve as a transmit TX port coupled to a transmitter or vice versa. Therefore, the two baluns are connected differentially to the antenna port and the two resistors are cross-coupled between the two baluns.

[0042] All inductors L1, L2, L3a, L3b and capacitors C1, C2, C3a, C3b in the differential combiner circuit 100, 200 may be given with equal inductance and capacitance values, e.g. an inductance value of L and a capacitance value of C. For the third capacitor C3 which is the combined of the two capacitors C3a, C3b, half of the capacitance value C, and for the third inductor L3 which is the combined of the two inductors L3a, L3b, twice of the inductance value L.

[0043] The differential combiner circuit 200 will provide high isolation centered at the resonance frequency=1/(2π√{square root over (LC)}). Its frequency of operation is not offset from the LC resonance, like in an L-match circuit, i.e. a matching network containing one inductor and one capacitor constructed in the shape of an L, where the offset depends on a circuit quality Q-value. The Q-value for all ports to be matched to a same port resistance is equal to 1/sqrt(2), and this low Q-value will inherently provide wideband operation. According to some embodiments, the two cross-coupled resistors R1, R2 should each have a value R.sub.iso equal to the differential port impedance for optimum isolation. However, other values may provide sufficient isolation as well, depending on requirements for a given application.

[0044] An example circuit has been designed and simulated to verify the functionality and performance of the differential combiner circuit 100, 200. The example circuit was designed with a center frequency of 2 GHz and a differential port impedance Rport of 100Ω. The inductance L is selected as

[00001]$\begin{array}{cc}L=\frac{R_{\mathrm{port}}}{2}\frac{1}{2\pi fQ}=50.Math.\frac{\sqrt{2}}{2\pi .Math.2.Math.{10}^9}=5.63\mathrm{nH}& \left(1\right)\end{array}$

And the capacitance C as

[00002]$\begin{array}{cc}C=\frac{1}{{\left(2\pi f\right)}^2.Math.L}=1.125\mathrm{pF}& \left(2\right)\end{array}$

The resistance R.sub.iso of the resistors R1 and R2 is selected, to provide optimum isolation, as

R.sub.iso=R.sub.port=100Ω  (3)

[0045] The negative resistance is obtained by cross-coupling, see the schematics in FIGS. 1 and 2, where R1 and R2 are cross-coupled resistors for isolation.

[0046] The example circuit has been simulated. FIG. 3 shows the simulated S-parameters, with L1=L2=5.63 nH, C1=C2=1.125 pF, C3=0.5*1.125 pF, and L3=2*5.63 nH, R1=R2=100Ω, R.sub.port=1000. The S31 curve is the S-parameter for TX and RX ports representing isolation between the TX and RX ports, the S21 curve represents signal transfer from Antenna port to RX port, and the S32 curve represents signal transfer from TX port to Antenna port.

[0047] As can be seen a wideband isolation is obtained for this simple circuit. The behavior is as expected with perfect isolation between RX and TX port at 2 GHz, where the losses between TX/RX and antenna port are equal to 3 dB. In a 100 MHz wide band, as indicated by the two star marks, the isolation exceeds 40 dB.

[0048] The principle of the differential combiner circuit 100, 200 may be explained and analysed with reference to FIG. 4. To analyze the circuit, a transfer from a signal voltage V.sub.TX at the transmit port to a current i.sub.RX in a short circuited receive port is investigated. The receive port is assumed to be perfectly isolated at the resonance frequency, and hence has no signal voltage, so a short circuit impedance can be used to simplify the analysis.

[0049] Circuit analysis shows that at the resonance frequency of L and C, the transfer from v.sub.TX to i.sub.RX becomes real valued, according to

[00003]$\begin{array}{cc}{i}_{\mathrm{RX}}=v_{\mathrm{TX}}.Math.\frac{R_{\mathrm{ant}}}{2}.Math.\frac{C}{L}& \left(4\right)\end{array}$

[0050] Where, R.sub.ant is antenna impedance. This current should be matched by the current injected by the isolation resistors R1, R2. That current should have an opposite phase, which is realized by the cross-coupling as shown in FIG. 2. The magnitude of the currents should be equal, so

[00004]$\begin{array}{cc}{R}_{\mathrm{iso}}=-\frac{v_{\mathrm{TX}}}{i_{\mathrm{RX}}}=-\frac{2L}{C.Math.R_{\mathrm{ant}}}& \left(5\right)\end{array}$

[0051] With the nominal antenna impedance of 100Ω, the isolation resistance becomes −100Ω. The isolation can also be achieved with other antenna impedances, if the isolation resistance is changed so it is inversely proportional to the antenna impedance as stated by equation (5). For instance, if the antenna impedance is halved to 50Ω the isolation resistance should be doubled to −200Ω.

[0052] FIG. 5 shows a simulation result, where the antenna impedance is swept from 50Ω to 200Ω and the isolation resistance is kept constant at −100Ω. The curves marked by the oval shape 501 are S31 curves for different antenna impedances from 50Ω to 200Ω. The curves marked by the oval shape 502 are S21 curves, and by the oval shape 503 are S32 curves.

[0053] FIG. 6 shows a simulation result, where the antenna impedance is swept from 50Ω to 200Ω and the isolation resistance is varied according to equation (5). The curves marked by the oval shape 601 are S31 curves for different antenna impedances from 50Ω to 200Ω. The curves marked by the oval shape 602 are S21 curves, and by the oval shape 603 are S32 curves.

[0054] As can be seen in FIGS. 5 and 6, the circuit behaves as expected. When setting the isolation resistance according to (5) perfect isolation can be maintained at the resonance frequency although the antenna impedance is changed.

[0055] When the antenna impedance has a reactive part, the antenna impedance R.sub.ant in FIG. 4 is accompanied by a capacitor or inductor, and the transfer from v.sub.TX to i.sub.RX will have a phase shift. This phase shifted current can be divided into an in-phase part cancelled by appropriately sized isolation resistors, and a quadrature phase part cancelled by capacitors in parallel with the isolation resistors. Depending on the sign of the antenna reactance the isolation capacitors can be cross-coupled or non-cross-coupled. It will thus be possible to compensate for inductive antenna loads without having to introduce additional inductors in the circuit.

[0056] FIG. 7 shows a differential combiner circuit 700 according to embodiments herein, where a first and second cross-coupled capacitors Cc1, Cc2 are in parallel with R1 and R2 respectively, a first non-cross-coupled capacitor Cnc1 is connected between the first terminals 1a, 3a of the first and third ports, a second non-cross-coupled capacitor Cnc2 is connected between the second terminals 1b, 3b of the first and third ports. The cross-coupled and non-cross-coupled capacitors are referred herein as isolation capacitors.

[0057] Rewriting equation (5) to cover also complex antenna impedances:

[00005]$\begin{array}{cc}{Z}_{\mathrm{iso}}=-\frac{v_{\mathrm{TX}}}{i_{\mathrm{RX}}}=-\frac{2L}{C.Math.Z_{\mathrm{ant}}}& \left(6\right)\end{array}$

[0058] To verify this, the antenna impedance is swept through the values 100-j40Ω, 100-j20Ω, 100Ω, 100+j20Ω, 100+j40Ω. Using equation (6), the isolation impedance is calculated to have 100Ω cross coupled resistors in parallel with 250Ω, 500Ω, infinity, −500Ω, −250Ω reactance. The reactance at the resonance frequency of 2 GHz is realized by non-cross-coupled capacitors of 318 fF, 159 fF, 0 fF, and cross-coupled capacitors of 159 fF and 318 fF, respectively. As can be seen the effect of antenna reactance is cancelled by a proportional capacitance, cross or non-cross coupled depending on reactance sign. The resistance value is in this case equal to the antenna impedance real part. So for the case when all ports connected to the differential combiner circuit have the same resistance, i.e. the RX, TX and antenna ports have the same nominal resistance, the isolation resistors R1, R2 then have a resistance equal to the port resistance. However, under other operating conditions the antenna impedance will vary around the nominal value, and then the isolation resistors and capacitors may be adjusted to compensate the antenna impedance variation and to maintain the isolation, according to the equations 5 and 6.

[0059] FIG. 8 shows simulation results. As can be seen the circuit behaves as expected and the antenna reactance can be compensated for. The curves marked by the oval shape 801 are S31 curves for different antenna impedances 100-j40Ω, 100-j20Ω, 100Ω, 100+j20Ω, 100+j40Ω. The curves marked by the oval shape 802 are S21 curves, and by the oval shape 803 are S32 curves.

[0060] This far the circuit has been simulated using ideal passive components, the loss has then been close to 3 dB. In an actual implementation, especially on an integrated circuit, the inductors will have substantial losses. The quality factor Q of the inductors may then be about 10. It is then important to simulate the circuit with such inductor quality factor Q to see if it lends itself well for integrated circuit implementation, and what performance can be expected. For this purpose, each inductor was connected with a parallel resistor of 1400Ω, and a series resistor of 3.50, corresponding to an inductor Q equal to 10 at 2 GHz. To compensate for the phase shift introduced by the resistive part of the inductors, the isolation capacitors were calculated using a value of j10Ω offset to the antenna impedance. The same sweep as in FIG. 8 is then performed.

[0061] FIG. 9 shows simulation results for non-ideal inductors having Q=10. The isolation capacitors value has been adjusted to keep the peak isolation for the signal with frequency at 2 GHz. The curves marked by the oval shape 901 are S31 curves for different antenna impedances 100-j40Ω, 100-j20Ω, 100Ω, 100+j20Ω, 100+j40Ω. The curves marked by the oval shape 902 are S21 curves, and by the oval shape 903 are S32 curves. As can be seen some isolation performance is lost, but more precise tuning may be performed on both real and imaginary part of the of the isolation impedance of the differential combiner circuit 700, tuning both the isolation resistors and capacitors to obtain higher narrow-band cancellation. As expected the losses have also increased. The loss at the center frequency for an inductor Q of 10 is about 3.7 dB. This should be compared to the loss in the ideal case, which is equal to 3 dB. The additional loss using an on-chip inductor is thus about 0.7 dB. It should also be noted that it may be possible to realized higher Q-values than 10 on chip, depending on frequency, semiconductor process, and available chip area. The loss will then be between 3 dB and 3.7 dB.

[0062] FIG. 10 shows the result after some more fine tuning to increase isolation. Here the capacitors in the differential combiner 700 have each been increased by 9%. The isolation capacitors have been calculated with an extra j30 in Zant when applying equation (6), and an additional 4Ω has been added to the isolation resistors. The curves marked by the oval shape 1001 are S31 curves for different antenna impedances 100-j40Ω, 100-j20Ω, 100Ω, 100+j20Ω, 100+j40Ω. The curves marked by the oval shape 1002 are S21 curves, and by the oval shape 1003 are S32 curves. As can be seen from FIG. 10, it is possible to achieve high isolation also with non-ideal on-chip inductors.

[0063] Deviations in antenna impedance will affect the isolation, since the magnitude and phase of the current from the transmitter to the receiver port is affected. To compensate for this the resistance in the isolation path may be made programmable, and two sets of programmable capacitors may be used, one cross-coupled and one without cross-coupling. In that way both capacitive and inductive loads may be handled with high isolation without using any additional inductors in the differential combiner circuit 100, 200, 700. Furthermore, the center or resonance frequency of the differential combiner circuit 100, 200, 700 may also be tuned by using programmable inductors and capacitors.

[0064] Therefore, according to some embodiments herein, the resistances of the first and second resistors R1, R2 may be variable or programmable.

[0065] The capacitance of the first, second and third capacitors C1, C2, C3 may be variable or programmable.

[0066] The inductance of the first, second and third inductors L1, L2, L3 may be variable or programmable.

[0067] The set of cross-coupled capacitors Cc1, Cc2 may be variable or programmable.

[0068] The set of non-cross-coupled capacitors Cnc1, Cnc2 may be variable or programmable.

[0069] To summarize, when the differential combiner 100, 200, 700 is in operation, a received signal at the antenna port, i.e. the second port 2a, 2b, will result in opposite phase signals at the first port 1a, 1b and third port 3a, 3b, if the frequency of the signal is equal to the resonance frequency of the differential combiner circuit 100, 200, 700. The resulting signals at 1a and 3b will then be in phase, so there will be no voltage between the terminals of the first resistor R1 due to the received signal. In the same way there will be no voltage between 1b and 3a and no voltage over the second resistor R2. The isolation resistors R1, R2 will thus have no effect on the signals in this case. The received signal power will then split equal between the receive and transmit ports, half the power ending up in the receive port, corresponding to the usual loss of 3 dB in an isolating combiner.

[0070] When a signal is injected by the transmitter, at the differential transmit port, the signal is isolated from the receive port. This occurs due to a cancellation between two paths, one through the LC-structure and one through the resistors. As explained above, when the receive port is to be isolated, it should have zero signal voltage, and thus can be seen as a signal ground. Then the signal currents from the two paths caused by a voltage at the transmitter port are checked. With a resistive antenna impedance and operating at the LC resonance frequency, there will be zero phase shift of the transfer from the transmit port voltage to the receive port current. With the cross coupled resistors there will be 180 degrees phase shift. Then by selecting the resistance value so that the magnitude of the two branch currents match, there will be a cancellation, hence isolating the receive port from the transmitter at the resonance frequency. The transmitter power will be shared equally between the resistors and the antenna port, having a 3 dB loss also for the signal transfer from the transmitter to the antenna.

[0071] The differential combiner circuit 100, 200, 700 may be used in a transceiver for full duplex or frequency division duplex. The second port of the differential combiner circuit 100, 200, 700 may serve as an antenna port coupled to an antenna. The first port of the differential combiner circuit 100, 200, 700 may serve as a receive port coupled to a receiver and the third port of the differential combiner circuit 100, 200, 700 may serve as a transmit port coupled to a transmitter or vice versa.

[0072] The differential combiner circuit 100, 200, 700 may be employed in various integrated circuits, electronic circuits, devices or apparatus. FIG. 11 shows a block diagram for an electronic device 1100. The electronic device 1100 comprises a transceiver 1110 which comprises the differential combiner circuit 100, 200, 700. The electronic device 1100 may comprise other units, where a memory 1120, a processing unit 1130 are shown. The electronic device 1100 may be a user equipment or a mobile device, a wireless communication device, or a radio base station for a cellular communication system.

[0073] The differential combiner circuit 100, 200, 700 according to the embodiments herein provides wide bandwidth, avoids use of transmission lines and transformers, and does not require a dummy load with programmable inductance. Despite its simplicity and low component count it supports fully differential circuitry, and it provides high isolation between receiver and transmitter. The differential combiner circuit is suitable for full integration as an on-chip isolator and provides low additional loss with low quality factor on-chip inductors. With an on-chip isolator like this, it becomes feasible to introduce full duplex or flexible frequency division duplex in low-cost short-range transceivers.

[0074] Those skilled in the art will understand that the differential combiner circuit 100, 200, 700 according to embodiments herein may be implemented by any semiconductor technology, e.g. Bi-polar, NMOS, PMOS, CMOS or Micro-Electro-Mechanical Systems (MEMS) technology etc.

[0075] The word “comprise” or “comprising”, when used herein, shall be interpreted as non-limiting, i.e. meaning “consist at least of”.

[0076] The embodiments herein are not limited to the above described preferred embodiments. Various alternatives, modifications and equivalents may be used. Therefore, the above embodiments should not be taken as limiting the scope of the invention, which is defined by the appended claims.