Inverter and method for generating an alternating current

Abstract

A method for generating an alternating electric current is provided. The method includes generating a plurality of component currents, superposing the component currents to form a summation current. Each component current is modulated by voltage pulses and the voltage pulses for each component current are generated by a component switching device by virtue of the component switching device generating the voltage pulses by switching between different input voltages. The method includes specifying a tolerance band for the summation current having an upper and a lower tolerance limit, where the summation current is detected and the switching of each component switching means is controlled to generate the voltage pulses for modulating the component current depending on the detected summation current with respect to the tolerance band. The plurality of component switching devices are switched at least partly or predominantly in a manner asynchronous with respect to one another.

Claims

1. A method for generating an alternating electric current comprising: generating a plurality of component currents, superposing the plurality of component currents to form a summation current, specifying a tolerance band for the summation current having an upper and a lower tolerance limit, detecting at least one difference current that is a difference between two component currents of the plurality of component currents, and detecting the summation current, wherein: each component current of the plurality of component currents is modulated by voltage pulses, and the voltage pulses are generated, for each component current, by a respective plurality of component switching devices, wherein a respective component switching device generates a respective voltage pulse by switching between different input voltages, the switching of each component switching device of the plurality of component switching devices is controlled to generate the respective voltage pulse for modulating the component current depending on the detected summation current with respect to the tolerance band, and the plurality of component switching devices are switched at least partly asynchronously with respect to each other, and the switching of the respective component switching device is performed depending on comparing the at least one difference current to a difference band having an upper difference limit and a lower difference limit for the at least one difference current.

2. The method as claimed in claim 1, comprising: switching at least one component switching device when the detected summation current reaches the upper tolerance limit or the lower tolerance limit.

3. The method as claimed in claim 1, comprising: selecting at least one of the plurality of component switching devices for switching based on a selection function that evaluates the plurality of component currents such that when the detected summation current reaches the upper tolerance limit or lower tolerance limit, the component switching device having a component current that is presently greatest in magnitude is selected for switching.

4. The method as claimed in claim 1, comprising: switching at least two of the plurality of component switching devices to opposite states when the at least one difference current reaches the upper difference limit or the lower difference limit.

5. The method as claimed in claim 2, comprising: monitoring the summation current to determine whether, after reaching the upper tolerance limit or the lower tolerance limit and after switching the at least one component switching device, the summation current does not leave the tolerance band, wherein at least one further component switching device is switched when the summation current leaves the tolerance band as a result of the summation current reaching an extended upper limit or an extended lower limit of a control band that surrounds the tolerance band.

6. The method as claimed in claim 1, wherein a difference between the upper difference limit and lower difference limit of the difference band is greater than a difference between the upper tolerance limit and lower tolerance limit of the tolerance band.

7. The method as claimed in claim 1, wherein the upper tolerance limit and lower tolerance limit are variable, a difference between the upper tolerance limit and lower tolerance limit is variable, or a difference between the upper difference limit and lower difference limit of the difference band is variable.

8. The method as claimed in claim 1, wherein each component switching device has a current output for outputting the component current and an electrical inductor for conducting the component current is arranged at the current output and electrical inductors of the plurality of component switching devices are magnetically coupled.

9. The method as claimed in claim 1, wherein: the plurality of component switching devices combine to form an inverter apparatus and the inverter apparatus outputs the summation current as an output current, and a plurality of inverter apparatuses including the inverter apparatus are connected in parallel and their respective output currents are superposed to form a total current for feeding into an electrical supply network.

10. The method as claimed in claim 9, wherein two respective component switching devices of the plurality of component switching devices are combined to form the inverter apparatus so that two component currents are superposed to form the summation current, wherein the inverter apparatus has two magnetically coupled inductors as output inductors.

11. The method as claimed in claim 10, wherein two component switching circuits are configured to: generate the two component currents, which are superposed to form the summation current, and wherein each of the two component switching circuits switches between a first position and a second position, wherein: the summation current increases when the two component switching circuits are both in the first position and together assume a positive position, the summation current decreases when the two component switching circuits are both in the second position and together assume a negative position, and the summation current substantially does not change when the two component switching circuits are in different switch positions and together assume a neutral position.

12. The method as claimed in claim 11, comprising: selecting between a first three-point operation, a second three-point operation and a two-point operation to modulate the summation current, wherein: in the first three-point operation, switching is between the positive and the neutral position, in the second three-point operation, switching is between the negative and the neutral position, and in the two-point operation, switching is between the positive and the negative position.

13. The method as claimed in claim 12, comprising: modulating the summation current in the two-point operation includes transitioning from modulation in the first three-point operation to modulation in the second three-point operation.

14. The method as claimed in claim 12, comprising: selecting between a modulation in the first three-point operation, a modulation in the second three-point operation and a modulation in the two-point operation based on a network voltage of an electrical network receiving an infeed or based on a phase position of the summation current in relation to the network voltage.

15. The method as claimed in claim 9, wherein each component switching device generates and outputs a three-phase summation current, wherein at least one of: the three-phase summation current is transformed to a transformed α/β/0 system, or a difference current in the transformed system is calculated.

16. The method as claimed in claim 1, wherein the summation current or a total current composed of a plurality of summation currents is fed into an electrical supply network so that the method for generating the alternating electric current is configured as a method for feeding electrical power into the electrical supply network.

17. An inverter for generating an alternating electric current, comprising: at least one DC voltage intermediate circuit having a first DC voltage and a second DC voltage, and a plurality of component switching devices, wherein each component switching device of the plurality of component switching devices generates a respective component current of a plurality of component currents, wherein: each component switching device of the plurality of component switching devices is configured to modulate the respective component current by voltage pulses generated by switching between the first and second DC voltage, a superposition device superposes the plurality of component currents to form a summation current, a current detection device detects the summation current, an output outputs the summation current as the alternating electric current, a process computer specifies a tolerance band for the detected summation current having an upper tolerance limit and a lower tolerance limit, and a controller is configured to control each component switching device based on the detected summation current and the upper and lower tolerance limits, wherein: the controller is operatively coupled to the process computer to control the component switching device in a manner guided by the process computer, the plurality of component switching devices are switched at least partly asynchronously with respect to each other, at least one difference current is detected, the at least one difference current being a difference between two component currents of the plurality of component currents, and the switching of the component switching device is performed depending on comparing the at least one difference current to a difference band having an upper difference limit and a lower difference limit for the at least one difference current.

18. The inverter as claimed in claim 17, wherein the process computer is configured to be coupled to further inverters so that the output summation current is superposed with further summation currents to form a total current.

19. The inverter as claimed in claim 17, wherein an inductor of a plurality of inductors is interconnected between each component switching device and the superposition device and the plurality of inductors are magnetically coupled.

20. The inverter as claimed in claim 17, wherein the inverter has two component switching devices.

21. An infeed arrangement, comprising: a plurality of inverters including: the inverter as claimed in claim 17; and one or more other inverters, wherein the plurality of inverters are connected in parallel at output devices of the plurality of inverters so that a plurality of summation currents of the plurality of inverters are superposed to form a total current.

22. The infeed arrangement as claimed in claim 21, wherein the process computer of the inverter and one or more other process computers of the one or more other inverters are coupled to each other to exchange information for coordinating generation of the plurality of summation currents between the plurality of inverters.

23. A wind power installation having an aerodynamic rotor and a generator for generating electrical power from wind and for feeding the electrical power as electric current into an electrical supply network, wherein the wind power installation includes the inverter as claimed in claim 17.

24. The method as claimed in claim 6, wherein a ratio of the difference between the upper difference limit and lower difference limit of the difference band to the difference between the upper tolerance limit and lower tolerance limit of the tolerance band is greater than 1.5.

Description

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

(1) The invention is described in more detail below by way of example on the basis of embodiments with reference to the accompanying figures.

(2) FIG. 1 shows a perspective illustration of a wind power installation.

(3) FIG. 2 shows a schematic 1-stranded or single-phase illustration of a model of an inverter having two component switching means.

(4) FIG. 3 shows two coupled inductances having a common, non-coupled inductance.

(5) FIG. 4 shows a further schematic illustration of an inverter.

(6) FIG. 5 illustrates a pulse pattern for demonstrating a method according to the invention.

(7) FIG. 6 shows a flowchart for demonstrating a method according to the invention.

(8) FIG. 7 shows a tolerance band and a difference band for demonstrating a method according to the invention.

DETAILED DESCRIPTION

(9) FIG. 1 shows a wind power installation 100 with a tower 102 and a nacelle 104. Arranged on the nacelle 104 is a rotor 106 with three rotor blades 108 and a spinner 110. During operation, the rotor 106 is set in rotation by the wind and thereby drives a generator in the nacelle 104.

(10) FIG. 2 schematically illustrates an inverter 2 having a first and second component switching means 11 and 12, respectively. The two component switching means 11, 12 can each switch between an upper voltage 4 or positive voltage 4 and a lower voltage 6 or negative voltage 6. As a result, voltage pulses, which can alternate namely between the upper voltage 4 and the lower voltage 6, can be generated at the first and second voltage node 13 and 14, respectively. For each component switching means 11 and 12, a component current i.sub.1,k,l results at the first voltage node and i.sub.2,k,l results at the second voltage node 14. Said two component currents i.sub.1,k,l and i.sub.2,k,l are superposed in the superposition means 16 to form the summation current i.sub.1,k,l+i.sub.2,k,l and are output at the output node 18 of the superposition means 16. Said summation current is then fed into an electrical supply network at the network node 20, which is denoted by an N. The two component currents and hence also the summation current consequently depend not only on the switching position of the component switching means 11, 12 but also on a voltage in the electrical supply network and in the process on a voltage at the network node 20. In principle, the method for generating an alternating current can also be used, however, for operating an electrical AC motor, for example.

(11) Both component switching means are supplied with power on the input side by a DC voltage intermediate circuit U.sub.dc, which in this case has a center tap M and is subdivided thereby into two voltages U.sub.dc/2 of equal magnitude. In this embodiment, both component switching means 11 and 12 are connected to the same DC voltage intermediate circuit 22.

(12) In the superposition means 16, it is possible to superpose the two component currents through two coupled inductances L.sub.ICT having a common, non-coupled inductance L.sub.F, as is illustrated demonstratively in FIG. 3. The double arrow with the letter k demonstrates the coupling of the two inductances L.sub.ICT. For example, the two coupled inductances L.sub.ICT of FIG. 3 could be connected at the first and second voltage node 13 and 14 in the superposition means 16 of FIG. 2. This is subsequently also taken as a basis for the explanation. For the purpose of demonstration, said two voltage nodes 13 and 14 are also shown in FIG. 3. The non-coupled inductance L.sub.F could accordingly be connected at the output node 18 of the superposition means 16 of FIG. 2 and this reference sign 18 is also shown accordingly in FIG. 3. Nevertheless, this, particularly the explanation of FIG. 3, serves for demonstration.

(13) Each of the coupled inductances L.sub.ICT forms an inductor for the first component switching means 11 and the second component switching means 12, respectively.

(14) A voltage at the first voltage node 13 consequently changes as a result of switching of the first component switching means 11. A voltage at the second voltage node 14 likewise changes as a result of switching of the second component switching means 12. Furthermore, a voltage at the connecting node 24 also changes. Expressed simply, the voltage values at the two voltage nodes 13 and 14 are each consequently switched between two values, as a result of which an alternation between three voltages can be produced at the connecting node 24. However, this should only serve for demonstration purposes since, whereas only two voltage values can actually be produced at the two voltage nodes 13 and 14 given a stable voltage of the DC voltage intermediate circuit 22, the voltage at the connecting node 24 also changes of course due to the change in the currents through the inductances shown in FIG. 3.

(15) FIG. 4 schematically shows an inverter 402, which is embodied in a three-phase manner. The inverter 402 also has a first and a second component switching means 411 and 412, respectively. Said two component switching means 411 and 412 each have a B6 bridge, which is illustrated only schematically, namely substantially by the six semiconductor switches HS. Further details, such as actuation lines or freewheeling diodes, are not illustrated for the sake of simplicity and, besides, a B6 bridge including the actuation thereof is known in principle to those skilled in the art. In any case, a respective branch having two semiconductor switches HS forms a switching element for a phase.

(16) The first component switching means 411 accordingly generates a component current i.sub.T1,1, i.sub.T1,2 and i.sub.T1,3, respectively, for each phase. The second component switching means 412 likewise accordingly generates a component current i.sub.T2,1, i.sub.T2,2 and i.sub.T2,3, respectively, for each phase. All of these component currents flow in each case through one of the six inductors D1 to D6 in order to then be superposed to form one of the summation currents i.sub.s1, i.sub.s2 and i.sub.s3, respectively. The three summation currents I.sub.s1 to I.sub.s3 together form a three-phase summation current, which can be fed into an electrical supply network, possibly after prior superposition with further three-phase summation currents.

(17) As power supply, both component switching means 411 and 412 receive a DC voltage intermediate circuit voltage U.sub.dc at a DC voltage intermediate circuit 422. Furthermore, intermediate circuit capacitors C1 to C4 are provided for voltage smoothing.

(18) The inductors D1 to D6 can be magnetically coupled in pairs so that the inductors D1 and D2 are coupled, the inductors D3 and D4 are coupled and the inductors D5 and D6 are coupled. It is also considered that the inductors D1 to D6 form two coupled three-phase inductors.

(19) A process computer 450 is provided to specify a tolerance band for the summation current having an upper and a lower tolerance limit. Furthermore, the inverter 402 comprises a control means 452 prepared to control each component switching means depending on the detected summation current and depending on the tolerance limit.

(20) FIG. 5 illustrates a section of a schematic illustration of a possible kind of modulation of a summation current. By way of example, a first summation current i.sub.s1 is shown here as summation current. To demonstrate voltage pulses, an illustrative profile of a voltage U′.sub.K is shown for the purpose of explanation. Said voltage profile U′.sub.K cannot actually be directly physically measured. It could be made to be able to be measured at the measurement point 211 of the indicated high-impedance voltage divider 212 between the voltage node 13 and 14 according to FIG. 2 using the measurement resistors 213 and 214. However, the voltage divider 212 is not provided and serves only for explanation.

(21) It should be mentioned that said FIG. 5 would like to explain the underlying principle based on a known three-point operation. In fact, it comes down to the generation of the summation current i.sub.s1. The actual voltage will also be able to be influenced by the current so that the illustration of FIG. 5, according to which the voltage assumes only three values, serves for demonstration.

(22) The component illustration begins at the time t.sub.1. At this time, it is assumed that the summation current i.sub.s1 has approximately the value of 0 and is intended to rise. Positive voltage pulses accordingly dominate initially. The illustration of the voltage profile U′.sub.K accordingly begins with a wide positive voltage pulse. A total voltage region U.sub.R is given as the amplitude, for example, so that the voltage ½U.sub.R to −½U.sub.R is sufficient. In any case, the illustrated positive voltage pulse at the time t.sub.1 is the result of both component switching means being switched to a positive or high voltage value by an inverter having two component switching means, as is shown in FIG. 2. If the voltage pulse decreases back to 0, as at the time t.sub.2, this means that one of the two component switching means 11 or 12, to refer to FIG. 2, has switched down to a low or negative voltage. Up to the time t.sub.3, a positive pulse pattern, which alternates between 0 and ½U.sub.R, is thus generated. This produces an increasing current i.sub.s1, which increases more weakly as the dominance of the respective positive voltage pulse decreases. Up to the time t.sub.3, an upper three-point operation is consequently illustrated, because there is switching only between 0 and a positive voltage.

(23) In any case, at the time t.sub.3, there is a switch from the positive voltage pulse illustrated there directly to an illustrated negative voltage pulse and back again shortly after. At the time t.sub.4, there is another switch from the positive voltage value directly to the negative voltage value. From the time t.sub.3 to the time t.sub.4, a two-point operation is consequently present. The component switching means 11 and 12 mentioned here by way of example thus each switch synchronously here. Said two-point operation is consequently intended to be kept as short as possible.

(24) From the time t.sub.4, a lower three-point operation then follows, in which there is a switch between the voltage 0 and the negative voltage. This is also to be understood as purely illustrative. Said lower three-point operation is consequently realized so that, in the case of the negative voltage value, the two component switching means 11 and 12 have switched to the lower voltage and, in the case of the value 0, one of said two component switching means 11 and 12 has switched to the upper value. It should be noted that, as explained more below, both in the case of the upper three-point operation between the times t.sub.1 and t.sub.3 and also in the case of the lower three-point operation between the times t.sub.4 and t.sub.5, the component switching means 11 and 12 mentioned by way of example can swap their position at phases, particularly in the case of long phases, in which the voltage assumes the value of 0. That is to say that between the component switching means 11 switching to a high voltage and the component switching means 12 switching to a low voltage, it is possible to switch to the state in which the first component switching means 11 is switched to a low voltage value and the second component switching means 12 is switched to a high voltage value, and vice versa.

(25) At the time t.sub.5, a short two-point operation could follow again.

(26) It can also be seen in FIG. 5 that said two-point operation is located in the shortest possible transition region between the upper three-point operation and the lower three-point operation or between a lower three-point operation and an upper three-point operation, as would follow at time t.sub.5.

(27) The two-point operation does not necessarily have to fall precisely within the region in which the summation current is at a maximum or minimum. The position of said two-point operation also depends namely on the network voltage and the phase position of the summation current with respect to the network voltage.

(28) It is mentioned, purely by way of precaution, that, in reality, significantly more switching pulses are of course selected for a half-wave of a sinusoidal current profile.

(29) FIG. 6 illustrates a procedure for executing the method for generating an alternating electric current. FIG. 6 shows here in a simplified manner a procedure 60, which is run through substantially continuously. The generated component currents and also the summation current superposed therefrom are detected in the measurement block 62. Based on the measurement values, a check is carried out in the tolerance block 64 to determine whether the summation current has reached a tolerance limit. When this is the case, there is a branch-off to the selection block 66, which selects the switch that should be switched. For simplification, an inverter according to FIG. 2 is assumed here. Then there is thus a selection in the selection block 66 as to whether the first component switching means 11 or the second component switching means 12 switches. If the two component switching means 11 and 12 are located in the same position, that is to say both up or both down, the component switching means whose current is greatest according to magnitude is selected. That is to say that if the two component switching means 11 and 12 are switched up and the first component current is greater than the second component current, the first component switching means 11 is switched.

(30) If the two component switching means 11 and 12 are in a different position, that is to say that the inverter is in a neutral position overall, in principle only one switch is considered for switching, namely that one that returns the summation current back to the tolerance band. That is to say that if, for example, the summation current in an upward movement impinges on the lower tolerance limit and if a component switching means is switched up and the other is switched down, the component switching means which is switched down can be switched up so that the current can be increased again as a result.

(31) Said switching is then implemented or initiated in the switching block 68. The loop then basically returns back to the measurement block 62.

(32) When it has been identified in the tolerance block 64 that the summation current does not impinge on a limit of the tolerance band, a check is carried out in the difference block 70 to determine whether a difference current impinges on a limit of the difference band. However, this takes place only when the neutral position is present, that is to say that both component switching means have different positions. If it has been identified that a limit of the difference band has been reached, the switch positions of the first and second component switching means 11 and 12 are changed in change block 72. In this case, it is assumed that the difference current, in any case in this example in which only two component switching means 11 and 12 are present, impinge on a limit of the difference band only when said component switching means have different positions since then the two currents are in opposite directions, which leads to a change in the difference current. If, for example, the difference block 70 should identify that the difference current impinges on a limit of the difference band more often than the tolerance block 64 identifies that the summation current impinges on a limit of the tolerance band, it is proposed to increase the difference band.

(33) In the method for generating the alternating current, an interception circuit is also implemented, which is not, however, present in the flowchart of FIG. 6. Said interruption circuit is constantly active and checks whether the summation current has left the tolerance band to a significant degree. Since the query in the tolerance block 64 is intended to return the summation current back to the tolerance band using the subsequent measures of the selection block 66 and switching block 68, said interruption circuit is not intended to be used in the normal case at all. Nevertheless, it is provided as a precaution. It functions so that a greater band is placed around the tolerance band, which greater band is referred to as control band, and so that a check is performed to determine whether said greater band is reached by the summation current. If this is the case, the summation current has to have left the tolerance band still further after it has already been identified in block 64 that the limits of the tolerance band have been reached and countermeasures of the blocks 66 and 68 have been initiated.

(34) FIG. 7 illustrates a simplified example of the switching criteria taken as a basis for the flowchart of FIG. 6. To this end, FIG. 7 shows a tolerance band 80 of a section of a summation current i.sub.s. The tolerance band 80 has an upper tolerance limit 82 and a lower tolerance limit 84.

(35) All of the illustrations in FIG. 7 are plotted over time t and the same time axis is taken as a basis for the illustration in FIG. 7. Dimensioning has been omitted but the summation current i.sub.s shows approximately an upper half-wave so that, in the event of a desired sinusoidal profile of 50 Hz, FIG. 7 illustrates approximately a hundredth of a second. However, it does not come down to this accuracy, especially since FIG. 7 reproduces the correlation in only a very simplified manner.

(36) Furthermore, FIG. 7 illustrates the switch positions of the component switching means 11 and 12 as switches S1 and S2. A plus sign indicates that the corresponding component switching means is switched up, namely to an upper or positive DC voltage, and a minus sign indicates that the relevant component switching means is switched down, namely to a lower or negative DC voltage.

(37) Furthermore, under the switch positions, a difference band 86 is shown, having an upper difference limit 88 and a lower difference limit 90.

(38) At the time t.sub.1, wherein said times do not correspond to those of FIG. 5, the two component switching means, that is to say the two switches S1 and S2, are switched up and the summation current i.sub.s increases. The two individual currents i.sub.1 and i.sub.2, which are each plotted in a graph below the difference band 86 as first component current i.sub.1 and second component current i.sub.2, also increase accordingly. It should be noted that the illustration is schematic and also the scaling of the currents i.sub.1, i.sub.2 and i.sub.s does not have to correspond exactly. However, the two component currents i.sub.1 and i.sub.2 are of the same scale in the graph of FIG. 7.

(39) In any case, the two component currents i.sub.1 and i.sub.2 increase at the time t1, wherein the first component current i.sub.1 is slightly greater than the second component current i.sub.2.

(40) At the time t.sub.2, the summation current i.sub.s reaches the upper tolerance limit 82 of the tolerance band 80. Since the first component current i.sub.1 is somewhat greater than the second component current i.sub.2, the first switch S1 is switched and consequently changes from plus to minus. The switch position of switch S2 remains unchanged. The first component current i.sub.1 then falls whereas the second component current i.sub.2 rises further. This leads to the difference current i.sub.d falling. In this case, the difference current i.sub.d is defined here as i.sub.d=i.sub.1−i.sub.2.

(41) Since the sum of the two component currents i.sub.1 and i.sub.2 is now approximately 0, the summation current i.sub.s does not change and initially has a horizontal profile.

(42) At the time t.sub.3, the difference current i.sub.d then reaches the lower difference limit 90. Switches S1 and S2 then swap their switch position. Switch S1 is thus switched up and S2 is switched down. The first component current i.sub.1 then increases and the second component current i.sub.2 falls. The summation current continues to remain at an approximately constant level here. The difference current rises again. At the time t.sub.4, the summation current i.sub.s reaches the lower tolerance limit 84. The second component switch S2 is then switched up so that both component switches S1 and S2 are then switched up again. At the time t.sub.5, the summation current i.sub.s then reaches the upper tolerance limit 82 again. In this case, the first component current i.sub.1 is again greater than the second component current t.sub.2 so that the first switch S1 is switched down.

(43) At the time t.sub.6, the difference current i.sub.d as a result reaches the lower difference limit again so that the switch positions S1 and S2 are exchanged. A short time later at the time t.sub.7, the summation current i.sub.s reaches the lower tolerance limit and the second switch S2 is consequently switched up again so that both switches are then switched up again.

(44) At the time t.sub.8 the summation current i.sub.s reaches the upper tolerance limit 82. This time, the second component current i.sub.2 is greater than the first component current i.sub.1 and the second switch S2, that is to say the second component switching means 12, is accordingly switched down.

(45) The first component current i.sub.1 consequently increases further whereas the second component current i.sub.2 falls. This leads to the difference current i.sub.d increasing and, at the time t.sub.9, the upper difference limit 88 being reached. Switches S1 and S2 then swap their position. At the time t.sub.10, the difference current i.sub.d then reaches the lower difference limit 90 and switches S1 and S2 swap their position again.

(46) At the time t.sub.11 the summation current i.sub.s reaches the upper tolerance limit 82 again and the only switch S1 that is switched up at this moment is accordingly switched down.

(47) At the time t.sub.12, the summation current i.sub.s reaches the lower tolerance limit 84, whereas both switches S1 and S2 are switched down. At this time, the first component current i.sub.1 is greater than the second component current i.sub.2. The second switch S2 is accordingly switched up in order to better balance the two component currents i.sub.1 and i.sub.2.

(48) This kind of circuit accordingly carries on continuously.

(49) This example of FIG. 7, which also serves only for illustration, differs from the example of FIG. 5 in that no two-point operation is carried out in the transition between the upper three-point operation and the lower three-point operation. The illustration of FIG. 7 basically shows an upper three-point operation up to the time t.sub.8. At the time t.sub.8, the upper three-point operation first assumes a center position, in which namely one of the two switches S1 and S2 are always switched up and one is always switched down. At the time t.sub.11, there is then a change from said neutral position to the lower three-point operation. It should be noted, however, that this is an illustration for explaining the method. The long region with a constant summation current i.sub.s from time t.sub.8 up to time t.sub.11 ought not to occur in reality because the tolerance band is significantly narrower in reality and as a result the switching frequency is significantly higher.

(50) In the embodiments, a solution that combines, in particular, two component switching means has consequently been described in detail. However, it is also very generally possible to combine a plurality of component switching means without departing from the teaching that is basically taken as a basis.

(51) In principle, a problem that consists in fitting two parallel-connected power sections with approximated sliding-mode controllers so that it acts as a three-point power converter is also taken as a basis here. That is to say that, in particular, both power sections can also have complementary switch positions for each phase.

(52) When such a configuration is fitted with a linear current controller, for example, the converter voltage functions as a manipulated variable. This can then be converted to discrete switching signals by a modulation algorithm, which implements the value prescribed by the controller in an averaged sense. In this case, in practice, all of the voltage levels of the three-point power converter are actually used. However, no sliding modes can thus be achieved, with the result that, for example, worse suppression of disturbances is achieved than is possible in the case of approximated sliding-mode controllers.

(53) In contrast, if an approximated sliding-mode controller, for example a tolerance band controller, is used to control the currents, there are two variants.

(54) According to the first variant, independent current controllers are used for both power sections. In the case of such a realization, all of the voltage levels of the three-point power converter can occur but this happens in an uncontrolled manner. An optional reduction in the average switching frequency would therefore not be possible.

(55) According to the second variant, a current controller for the resulting current of both power sections would be used so that both power sections switch practically in synchronous fashion. The occurrence of complementary switching positions is then practically excluded, which mostly leads, however, to a higher average switching frequency.

(56) These problems have also been recognized. Controlling the resulting current of both power sections and also the differential current is described herein. Tolerance bands can be prescribed independently of one another for the two currents, which has been recognized. In addition, it is intended to ensure, as far as possible, that complementary switch positions also occur for each phase so that the lowest possible average switching frequency is achieved. Furthermore, it is also intended to cover the case when the inductors of both power sections are magnetically coupled to one another.

(57) Concepts of the solution already described herein are, inter alia, that there is a superordinate controller for the summation current and a subordinate controller for the difference current. To control the summation current, the switch combination that leads to the lowest possible switching frequency is then selected. This has also already been described in detail by way of example.

(58) A teaching herein is consequently the perception of the parallel connection of the power sections, which can also be referred to herein synonymously as component switching means, as a three-point power converter from the point of view of the summation current and the design of a controller for this. In the case of the design of the controller, a magnetic coupling of the inductors can then be taken into account.

(59) An advantage herein is that the maximum adjusting range is not utilized immediately, as is often the case in approximated sliding-mode controllers. As a result, the average switching frequency can be reduced and the positive properties of a sliding-mode control process can remain unchanged at the same time, for example, the good suppression of disturbances and the relatively fast reaction capacity.